From 19bdc7dd0faa5a016977b6447d610ac847b69d2b Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 29 Aug 2018 19:47:19 -0500 Subject: [PATCH] radv/meta: Set num_components on image_store intrinsics Now that image load/store intrinsics are variable-width, we need to set num_components accordingly. In 15d39f474b890, both glsl_to_nir and spirv_to_nir were updated to properly set num_components but radv meta was left behind. Fixes: 15d39f474b890 "nir: Make image load/store intrinsics..." Reviewed-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Tested-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_bufimage.c | 4 ++++ src/amd/vulkan/radv_meta_fast_clear.c | 1 + src/amd/vulkan/radv_meta_resolve_cs.c | 1 + 3 files changed, 6 insertions(+) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index aa17c25833b..b596173fe18 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -116,6 +116,7 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *outval = &tex->dest.ssa; nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(coord); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); @@ -342,6 +343,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *outval = &tex->dest.ssa; nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(img_coord); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); @@ -557,6 +559,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *outval = &tex->dest.ssa; nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(dst_coord); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); @@ -753,6 +756,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d) global_id = nir_vec(&b, comps, 4); nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(global_id); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index b4cc900028e..9544ee94f5c 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -92,6 +92,7 @@ build_dcc_decompress_compute_shader(struct radv_device *dev) nir_ssa_def *outval = &tex->dest.ssa; nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(global_id); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index fca49a01bb0..2fcfb0aaeff 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -136,6 +136,7 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa); nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store); + store->num_components = 4; store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa); store->src[1] = nir_src_for_ssa(coord); store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); -- 2.30.2