From 19c9b69f9dcbde7d5071bdb05c8eb5f671db5179 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 May 2020 21:22:38 +0100 Subject: [PATCH] update comments --- libreriscv | 2 +- src/soc/fu/trap/pipe_data.py | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libreriscv b/libreriscv index 6ce15b77..3e665eb7 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 6ce15b77d086f4f2d0b945b032fbaa2096f2ef6f +Subproject commit 3e665eb7607d37b92567a445e795c4d7b6e00fc9 diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 751a1835..581040c4 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -26,10 +26,10 @@ class TrapInputData(IntegerData): class TrapOutputData(IntegerData): def __init__(self, pspec): super().__init__(pspec) - self.nia = Signal(64, reset_less=True) # RA - self.msr = Signal(64, reset_less=True) # RB/immediate - self.srr0 = Signal(64, reset_less=True) # RB/immediate - self.srr1 = Signal(64, reset_less=True) # RB/immediate + self.nia = Signal(64, reset_less=True) # NIA (Next PC) + self.msr = Signal(64, reset_less=True) # MSR + self.srr0 = Signal(64, reset_less=True) # SRR0 SPR + self.srr1 = Signal(64, reset_less=True) # SRR1 SPR self.should_trap = Signal(reset_less=True) def __iter__(self): -- 2.30.2