From 19d2ee777216e78024a2215c38b9a09ac1ccde88 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 3 Oct 2018 10:42:23 +0100 Subject: [PATCH] add in twin-predication identification pass in second predicate for twin-predication operands --- id_regs.py | 8 ++++++++ riscv/insn_template_sv.cc | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/id_regs.py b/id_regs.py index 21a3faa..734f029 100644 --- a/id_regs.py +++ b/id_regs.py @@ -105,6 +105,7 @@ if __name__ == '__main__': for (fname, insn) in files: regsname = "regs_%s.h" % insn regsname = os.path.join(insns_dir, regsname) + twin_predication = False with open(regsname, "w") as f: txt = find_registers(fname) txt += "\n#define INSN_%s\n" % insn.upper() @@ -112,6 +113,7 @@ if __name__ == '__main__': if insn in ['beq', 'bne', 'blt', 'bltu', 'bge', 'bgeu']: txt += "#define INSN_TYPE_BRANCH\n" if insn in ['lb', 'lbu', 'lw', 'lwu', 'ld', 'ldu']: + twin_predication = True txt += "#define INSN_TYPE_LOAD\n" elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']: txt += "\n#define INSN_TYPE_C_STACK_LD\n" @@ -119,10 +121,14 @@ if __name__ == '__main__': txt += "\n#define INSN_TYPE_C_STACK_ST\n" elif insn in ['c_lw', 'c_ld', 'c_lq', 'c_flw', 'c_fld']: txt += "\n#define INSN_TYPE_C_LD\n" + twin_predication = True elif insn in ['c_sw', 'c_sd', 'c_sq', 'c_fsw', 'c_fsd']: txt += "\n#define INSN_TYPE_C_ST\n" + twin_predication = True elif insn in ['c_beqz', 'c_bnez']: txt += "\n#define INSN_TYPE_C_BRANCH\n" + elif insn in ['c_mv']: + twin_predication = True elif insn.startswith("c_"): txt += "#define INSN_TYPE_C\n" elif insn.startswith("fmv") or \ @@ -133,4 +139,6 @@ if __name__ == '__main__': insn.startswith("flt") or \ insn.startswith("fle"): txt += "#define INSN_TYPE_FP_BRANCH\n" + if twin_predication: + txt += "\n#define INSN_CATEGORY_TWINPREDICATION\n" f.write(txt) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 7a1884c..7804625 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -19,10 +19,40 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) // REGS_PATTERN is generated by id_regs.py (per opcode) unsigned int floatintmap = REGS_PATTERN; reg_t dest_pred = ~0x0; - bool ldimm_sv = false; +#ifdef INSN_CATEGORY_TWINPREDICATION + reg_t src_pred = ~0x0; +#endif sv_insn_t insn(p, bits, floatintmap, - dest_pred, dest_pred, dest_pred, dest_pred); + dest_pred, +#ifdef INSN_CATEGORY_TWINPREDICATION +// twin-predication ONLY applies to dual-op operands: MV, FCVT, LD/ST. +// however we don't know which register any of those will use, so +// pass src_pred to each of rs1-3 and let the instruction sort it out. +src_pred, src_pred, src_pred +#else +dest_pred, dest_pred, dest_pred +#endif + ); bool zeroing; +#ifdef INSN_CATEGORY_TWINPREDICATION +#ifdef USING_REG_RS1 + #define SRCREG s_insn.rs1() +#endif +#ifdef USING_REG_RS2 + #define SRCREG s_insn.rs2() +#endif +#ifdef USING_REG_RS3 + #define SRCREG s_insn.rs3() +#endif +#if (defined(USING_REG_RVC_RS1) || defined(USING_REG_RVC_RS1S)) + #define SRCREG s_insn.rvc_rs1() +#endif +#if (defined(USING_REG_RVC_RS2) || defined(USING_REG_RVC_RS2S)) + #define SRCREG s_insn.rvc_rs2() +#endif + src_pred = insn.predicate(SRCREG, floatintmap & (REG_RS1|REG_RS2|REG_RS3), + zeroing); +#endif #if defined(USING_REG_RD) || defined(USING_REG_FRD) // use the ORIGINAL, i.e. NON-REDIRECTED, register here dest_pred = insn.predicate(s_insn.rd(), floatintmap & REG_RD, zeroing); -- 2.30.2