From 19e1f7db75cbcfc6269e14495b4a38608acbda7f Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 6 Sep 2022 08:24:46 +0100 Subject: [PATCH] --- openpower/sv/remap.mdwn | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index e4ad1c888..5cfbf4651 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -489,10 +489,18 @@ Creates the Schedules for Parallel Tree Reduction. * When bit 0 of `invxyz` is set, the order of the indices in the inner for-loop are reversed. This has the side-effect - of placing the final reduced result in the last element. + of placing the final reduced result in the last-predicated element. + It also has the indirect side-effect of swapping the source + registers: Left-operand index numbers will always exceed + Right-operand indices. + When clear, the reduced result will be in the first-predicated + element, and Left-operand indices will always be *less* than + Right-operand ones. * When bit 1 of `invxyz` is set, the order of the outer loop step is inverted: stepping begins at the nearest power-of two to half of the vector length and reduces by half each time. + When clear the step will begin at 2 and double on each + inner loop. ## FFT/DCT mode -- 2.30.2