From 19e43cbce353b63a05c3b7c39d83a2e32c9f911f Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Mon, 3 Feb 2020 15:50:39 -0500 Subject: [PATCH] Add some gcc_asserts for vector extract processing. 2020-02-03 Michael Meissner * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some gcc_asserts. --- gcc/ChangeLog | 5 +++++ gcc/config/rs6000/rs6000.c | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4ded82cd6fd..b66cec2b85f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2020-02-03 Michael Meissner + + * config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some + gcc_asserts. + 2020-02-03 Segher Boessenkool * config/rs6000/constraints.md: Improve documentation. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index fc36bb6714b..8f72350f331 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6768,6 +6768,9 @@ rs6000_adjust_vec_address (rtx scalar_reg, rtx new_addr; bool valid_addr_p; + gcc_assert (!reg_mentioned_p (base_tmp, addr)); + gcc_assert (!reg_mentioned_p (base_tmp, element)); + /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */ gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC); @@ -6777,6 +6780,10 @@ rs6000_adjust_vec_address (rtx scalar_reg, element_offset = GEN_INT (INTVAL (element) * scalar_size); else { + /* All insns should use the 'Q' constraint (address is a single register) + if the element number is not a constant. */ + gcc_assert (REG_P (addr) || SUBREG_P (addr)); + int byte_shift = exact_log2 (scalar_size); gcc_assert (byte_shift >= 0); -- 2.30.2