From 19e7bcee1742a40981a0b1c06447bca22646c294 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 15 Jan 2020 14:06:07 +0200 Subject: [PATCH] iris: implement gen12 post sync pipe control workaround Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a post-sync operation. v2: Restrict to A0 Signed-off-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_state.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 7222e724ac6..db4568c7777 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6864,7 +6864,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, imm); } - if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { + if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0*/)) && + IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * * "PIPECONTROL command with “Command Streamer Stall Enable” must be @@ -6873,6 +6874,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * PIPELINE_SELECT command is set to GPGPU mode of operation)." * * The same text exists a few rows below for Post Sync Op. + * + * On Gen12 this is GEN:BUG:1607156449. */ iris_emit_raw_pipe_control(batch, "workaround: CS stall before gpgpu post-sync", -- 2.30.2