From 19ffcba161e56566611e546b73e21f498be63fa5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 5 Dec 2018 16:08:12 -0800 Subject: [PATCH] mesa/st: Expose compute shaders when NIR support is advertised. We have a NIR path, and V3D doesn't have TGSI input for compute (only what TTN can handle for the various gallium-internal shaders). Reviewed-by: Kenneth Graunke Reviewed-by: Jordan Justen --- src/gallium/auxiliary/cso_cache/cso_context.c | 3 ++- src/mesa/state_tracker/st_extensions.c | 19 ++++++++++++------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c b/src/gallium/auxiliary/cso_cache/cso_context.c index 97cb77ee8e8..d9e1309c5cc 100644 --- a/src/gallium/auxiliary/cso_cache/cso_context.c +++ b/src/gallium/auxiliary/cso_cache/cso_context.c @@ -329,7 +329,8 @@ cso_create_context(struct pipe_context *pipe, unsigned u_vbuf_flags) int supported_irs = pipe->screen->get_shader_param(pipe->screen, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_SUPPORTED_IRS); - if (supported_irs & (1 << PIPE_SHADER_IR_TGSI)) { + if (supported_irs & ((1 << PIPE_SHADER_IR_TGSI) | + (1 << PIPE_SHADER_IR_NIR))) { ctx->has_compute_shader = TRUE; } } diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index 081c97f9610..8d936e4628f 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -183,7 +183,8 @@ void st_init_limits(struct pipe_screen *screen, continue; supported_irs = screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_SUPPORTED_IRS); - if (!(supported_irs & (1 << PIPE_SHADER_IR_TGSI))) + if (!(supported_irs & ((1 << PIPE_SHADER_IR_TGSI) | + (1 << PIPE_SHADER_IR_NIR)))) continue; } @@ -1416,18 +1417,22 @@ void st_init_extensions(struct pipe_screen *screen, int compute_supported_irs = screen->get_shader_param(screen, PIPE_SHADER_COMPUTE, PIPE_SHADER_CAP_SUPPORTED_IRS); - if (compute_supported_irs & (1 << PIPE_SHADER_IR_TGSI)) { + if (compute_supported_irs & ((1 << PIPE_SHADER_IR_TGSI) | + (1 << PIPE_SHADER_IR_NIR))) { + enum pipe_shader_ir ir = + (compute_supported_irs & PIPE_SHADER_IR_NIR) ? + PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI; uint64_t grid_size[3], block_size[3]; uint64_t max_local_size, max_threads_per_block; - screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, + screen->get_compute_param(screen, ir, PIPE_COMPUTE_CAP_MAX_GRID_SIZE, grid_size); - screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, + screen->get_compute_param(screen, ir, PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE, block_size); - screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, + screen->get_compute_param(screen, ir, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, &max_threads_per_block); - screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, + screen->get_compute_param(screen, ir, PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE, &max_local_size); @@ -1446,7 +1451,7 @@ void st_init_extensions(struct pipe_screen *screen, if (extensions->ARB_compute_shader) { uint64_t max_variable_threads_per_block = 0; - screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI, + screen->get_compute_param(screen, ir, PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK, &max_variable_threads_per_block); -- 2.30.2