From 1a008f905ada29e4f11b6180d8fa3e642c935099 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jun 2020 13:16:23 +0100 Subject: [PATCH] add extra missing args to ISA setup in alu test_pipe_caller --- src/soc/fu/alu/test/test_pipe_caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index f3e021f4..13f059eb 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -203,7 +203,8 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, 0) + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) -- 2.30.2