From 1a01326bf9a5d289751efc9879caaea2a2b441b3 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 29 Aug 2016 11:49:47 -0700 Subject: [PATCH] Rename tdata0--tdata2 to tdata1--tdata3. --- riscv/encoding.h | 11 +++++++---- riscv/gdbserver.cc | 8 ++++---- riscv/processor.cc | 10 ++++++---- riscv/processor.h | 1 + 4 files changed, 18 insertions(+), 12 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 2a66e51..ce0f17c 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -73,6 +73,9 @@ #define MCONTROL_STORE (1<<1) #define MCONTROL_LOAD (1<<0) +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 #define MCONTROL_ACTION_DEBUG_MODE 1 #define MCONTROL_ACTION_TRACE_START 2 @@ -703,9 +706,9 @@ #define CSR_MSTIME_DELTA 0x705 #define CSR_MSINSTRET_DELTA 0x706 #define CSR_TSELECT 0x7a0 -#define CSR_TDATA0 0x7a1 -#define CSR_TDATA1 0x7a2 -#define CSR_TDATA2 0x7a3 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 #define CSR_DCSR 0x7b0 #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 @@ -1012,9 +1015,9 @@ DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA) DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA) DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA) DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata0, CSR_TDATA0) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) DECLARE_CSR(dcsr, CSR_DCSR) DECLARE_CSR(dpc, CSR_DPC) DECLARE_CSR(dscratch, CSR_DSCRATCH) diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index db88d30..e7eafca 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -1069,7 +1069,7 @@ class hardware_breakpoint_insert_op_t : public operation_t return true; } - gs.dr_write32(0, csrr(S0, CSR_TDATA0)); + gs.dr_write32(0, csrr(S0, CSR_TDATA1)); gs.dr_write_store(1, S0, SLOT_DATA0); gs.dr_write_jump(2); state = STATE_CHECK_MCONTROL; @@ -1091,7 +1091,7 @@ class hardware_breakpoint_insert_op_t : public operation_t !get_field(mcontrol, MCONTROL_STORE)) { // Found an unused trigger. gs.dr_write_load(0, S0, SLOT_DATA1); - gs.dr_write32(1, csrw(S0, CSR_TDATA0)); + gs.dr_write32(1, csrw(S0, CSR_TDATA1)); gs.dr_write_jump(2); mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE); mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL); @@ -1115,7 +1115,7 @@ class hardware_breakpoint_insert_op_t : public operation_t case STATE_WRITE_ADDRESS: { gs.dr_write_load(0, S0, SLOT_DATA1); - gs.dr_write32(1, csrw(S0, CSR_TDATA1)); + gs.dr_write32(1, csrw(S0, CSR_TDATA2)); gs.dr_write_jump(2); gs.dr_write(SLOT_DATA1, bp.vaddr); gs.set_interrupt(0); @@ -1151,7 +1151,7 @@ class hardware_breakpoint_remove_op_t : public operation_t bool perform_step(unsigned int step) { gs.dr_write32(0, addi(S0, ZERO, bp.index)); gs.dr_write32(1, csrw(S0, CSR_TSELECT)); - gs.dr_write32(2, csrw(ZERO, CSR_TDATA0)); + gs.dr_write32(2, csrw(ZERO, CSR_TDATA1)); gs.dr_write_jump(3); gs.set_interrupt(0); return true; diff --git a/riscv/processor.cc b/riscv/processor.cc index 2abbb5a..04d483c 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -382,9 +382,10 @@ void processor_t::set_csr(int which, reg_t val) case CSR_MCAUSE: state.mcause = val; break; case CSR_MBADADDR: state.mbadaddr = val; break; case CSR_TSELECT: state.tselect = val; break; - case CSR_TDATA0: + case CSR_TDATA1: if (state.tselect < state.num_triggers) { mcontrol_t *mc = &state.mcontrol[state.tselect]; + mc->dmode = get_field(val, MCONTROL_DMODE(xlen)); mc->select = get_field(val, MCONTROL_SELECT); mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION); mc->chain = get_field(val, MCONTROL_CHAIN); @@ -400,7 +401,7 @@ void processor_t::set_csr(int which, reg_t val) trigger_updated(); } break; - case CSR_TDATA1: + case CSR_TDATA2: if (state.tselect < state.num_triggers) { state.tdata1[state.tselect] = val; } @@ -509,11 +510,12 @@ reg_t processor_t::get_csr(int which) case CSR_MEDELEG: return state.medeleg; case CSR_MIDELEG: return state.mideleg; case CSR_TSELECT: return state.tselect; - case CSR_TDATA0: + case CSR_TDATA1: if (state.tselect < state.num_triggers) { reg_t v = 0; mcontrol_t *mc = &state.mcontrol[state.tselect]; v = set_field(v, MCONTROL_TYPE(xlen), mc->type); + v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode); v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax); v = set_field(v, MCONTROL_SELECT, mc->select); v = set_field(v, MCONTROL_ACTION, mc->action); @@ -531,7 +533,7 @@ reg_t processor_t::get_csr(int which) return 0; } break; - case CSR_TDATA1: + case CSR_TDATA2: if (state.tselect < state.num_triggers) { return state.tdata1[state.tselect]; } else { diff --git a/riscv/processor.h b/riscv/processor.h index 41d778e..2eac770 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -67,6 +67,7 @@ typedef struct uint8_t type; uint8_t maskmax; bool select; + bool dmode; mcontrol_action_t action; bool chain; mcontrol_match_t match; -- 2.30.2