From 1a2973c4f314fdc0aa74d450d9360bf2732f0583 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 Nov 2023 19:43:26 +0000 Subject: [PATCH] bug #672: more code-comments --- src/openpower/decoder/isa/test_caller_svp64_pospopcount.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py index efc31ef5..5aebce3b 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py +++ b/src/openpower/decoder/isa/test_caller_svp64_pospopcount.py @@ -49,8 +49,8 @@ class PosPopCountTestCase(FHDLTestCase): "setvl 0,0,8,0,1,1", # set MVL=VL=8 "sv.popcntd/sw=8 *24,*8", # do the (now transposed) popcount "sv.add *16,*16,*24", # and accumulate in results - # branch back if still CTR - "sv.bc/all 16, *0, -0x28", # CTR mode, reduce VL by CTR + # branch back if CTR still non-zero. works even though VL=8 + "sv.bc/all 16, *0, -0x28", # reduce CTR by VL and stop if -ve ] ) lst = list(lst) -- 2.30.2