From 1a49f489a529e2c4a13ed20b86c3719760a7c0ac Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 19 Oct 2021 18:36:34 +0100 Subject: [PATCH] clarify --- SEP-210803722-Libre-SOC-8-core.mdwn | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn index 127249c55..735902e4f 100644 --- a/SEP-210803722-Libre-SOC-8-core.mdwn +++ b/SEP-210803722-Libre-SOC-8-core.mdwn @@ -53,7 +53,7 @@ We consider it strategically critical to develop processors in an entirely trans In addition to this, Libre-SOC has already been developing Mathematical Formal Correctness Proofs for the HDL of its early prototype designs, which, in combination with unrestricted access to the HDL Source Code, allow third parties including customers to perform their own verification of the ASIC's purpose (as opposed to the customer having to trust a manufacture that inherently has a direct conflict-of-interest in the form of its Shareholders and profits). Furthermore, we aim to experiment with built-in "tamper-checking" circuits that, on running a test programme on our evaluation test bed, will provide an Electro-Magnetic "signature". By publishing this "signature" and the test programs, customers can verify that their purchased ASICs have the same EMF "signature" and can detect immediately if the ASIC has been tampered with. In addition we will continue existing (TRL 2) research into Hardware-level Speculative Execution mitigation techniques. We feel that the full combination of these objectives meets the Hardware Security requirements of this Call. -This strategy does not end with just the HDL: thanks (again) to NLnet we have been collaborating already with Chips4Makers, LIP6 and CNRS (all funded by EU Grants), to advance the state-of-the-art for European VLSI Tool Technology, which we deeply appreciate is important to European Silicon Sovereignty. +This strategy does not end with just the HDL: thanks (again) to NLnet we have been collaborating already with Chips4Makers, LIP6 and CNRS (all funded by EU Grants), to advance the state-of-the-art for European VLSI Tool Technology, which is important to European Silicon Sovereignty. https://www.europarl.europa.eu/RegData/etudes/BRIE/2020/651992/EPRS_BRI(2020)651992_EN.pdf @@ -384,11 +384,6 @@ Work Packages: # 3.1 Work plan and resources - - - - - Tables for section 3.1 @@ -410,13 +405,10 @@ Table 3.1a: List of work packages |11 |HELIX GPS Cor. |6 |HELIX |248 |1 |36 | | | | |Total months |1512 | | | - ## 1. NLnet - Table 3.1b(1) - |Work Package Number |1 | | ---- | -------- | |Lead beneficiary |NLnet | -- 2.30.2