From 1a623701469c08e72685d44a4ebed9157ab4bfe2 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 13 Feb 2017 09:53:23 -0800 Subject: [PATCH] Abstract register read mostly working. Fails with not supported for 128-bit. Fails with exception (on rv32) with 64-bit. Succeeds (on rv32) with 32-bit. --- riscv/debug_module.cc | 220 ++++++++++++++++++++++++++++++++++++------ riscv/debug_module.h | 46 ++++++++- riscv/decode.h | 12 ++- riscv/jtag_dtm.cc | 2 +- riscv/processor.cc | 14 ++- riscv/sim.cc | 2 +- 6 files changed, 254 insertions(+), 42 deletions(-) diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index e9619c4..1a165e4 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -13,20 +13,75 @@ # define D(x) #endif +///////////////////////// debug_module_data_t + +debug_module_data_t::debug_module_data_t() +{ + memset(data, 0, sizeof(data)); +} + +bool debug_module_data_t::load(reg_t addr, size_t len, uint8_t* bytes) +{ + D(fprintf(stderr, "debug_module_data_t load 0x%lx bytes at 0x%lx\n", len, + addr)); + + if (addr + len < sizeof(data)) { + memcpy(bytes, data + addr, len); + return true; + } + + fprintf(stderr, "ERROR: invalid load from debug_module_data_t: %zd bytes at 0x%016" + PRIx64 "\n", len, addr); + + return false; +} + +bool debug_module_data_t::store(reg_t addr, size_t len, const uint8_t* bytes) +{ + D(fprintf(stderr, "debug_module_data_t store 0x%lx bytes at 0x%lx\n", len, + addr)); + + if (addr + len < sizeof(data)) { + memcpy(data + addr, bytes, len); + return true; + } + + fprintf(stderr, "ERROR: invalid store to debug_module_data_t: %zd bytes at 0x%016" + PRIx64 "\n", len, addr); + return false; +} + +uint32_t debug_module_data_t::read32(reg_t addr) const +{ + assert(addr + 4 <= sizeof(data)); + return data[addr] | + (data[addr + 1] << 8) | + (data[addr + 2] << 16) | + (data[addr + 3] << 24); +} + +void debug_module_data_t::write32(reg_t addr, uint32_t value) +{ + fprintf(stderr, "debug_module_data_t::write32(0x%lx, 0x%x)\n", addr, value); + assert(addr + 4 <= sizeof(data)); + data[addr] = value & 0xff; + data[addr + 1] = (value >> 8) & 0xff; + data[addr + 2] = (value >> 16) & 0xff; + data[addr + 3] = (value >> 24) & 0xff; +} + +///////////////////////// debug_module_t + debug_module_t::debug_module_t(sim_t *sim) : sim(sim) { dmcontrol = {0}; dmcontrol.version = 1; - for (unsigned i = 0; i < 1024; i++) { - write32(debug_rom_entry, i, jal(0, 0)); + for (unsigned i = 0; i < DEBUG_ROM_ENTRY_SIZE / 4; i++) { + write32(debug_rom_entry, i, jal(ZERO, 0)); halted[i] = false; } - for (unsigned i = 0; i < datacount; i++) { - data[i] = 0; - } - for (unsigned i = 0; i < progsize; i++) { ibuf[i] = 0; } @@ -41,24 +96,54 @@ void debug_module_t::reset() proc->halt_request = false; } - dmcontrol.haltreq = 0; - dmcontrol.reset = 0; - dmcontrol.dmactive = 0; - dmcontrol.hartsel = 0; + dmcontrol = {0}; dmcontrol.authenticated = 1; dmcontrol.version = 1; - dmcontrol.authbusy = 0; dmcontrol.authtype = dmcontrol.AUTHTYPE_NOAUTH; - abstractcs = datacount << DMI_ABSTRACTCS_DATACOUNT_OFFSET; + + abstractcs = {0}; + abstractcs.datacount = sizeof(dmdata.data) / 4; +} + +void debug_module_t::add_device(bus_t *bus) { + bus->add_device(DEBUG_START, this); + bus->add_device(DEBUG_EXCHANGE, &dmdata); } bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) { + D(fprintf(stderr, "load 0x%lx bytes at 0x%lx\n", + len, addr)); addr = DEBUG_START + addr; - if (addr >= DEBUG_ROM_ENTRY && addr <= DEBUG_ROM_CODE) { + if (addr >= DEBUG_ROM_ENTRY && + addr < DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE) { halted[(addr - DEBUG_ROM_ENTRY) / 4] = true; memcpy(bytes, debug_rom_entry + addr - DEBUG_ROM_ENTRY, len); + + if (read32(debug_rom_entry, dmcontrol.hartsel) == jal(ZERO, 0)) { + // We're here in an infinite loop. That means that whatever abstract + // command has complete. + abstractcs.busy = false; + } + return true; + } + + // Restore the jump-to-self loop. + write32(debug_rom_entry, dmcontrol.hartsel, jal(ZERO, 0)); + + if (addr >= DEBUG_ROM_CODE && + addr < DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE) { + memcpy(bytes, debug_rom_code + addr - DEBUG_ROM_CODE, len); + return true; + } + + if (addr >= DEBUG_ROM_EXCEPTION && + addr < DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE) { + memcpy(bytes, debug_rom_exception + addr - DEBUG_ROM_EXCEPTION, len); + if (abstractcs.cmderr == abstractcs.CMDERR_NONE) { + abstractcs.cmderr = abstractcs.CMDERR_EXCEPTION; + } return true; } @@ -72,14 +157,6 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) { addr = DEBUG_START + addr; - if (addr & (len-1)) { - fprintf(stderr, "ERROR: unaligned store to debug module: %zd bytes at 0x%016" - PRIx64 "\n", len, addr); - return false; - } - - // memcpy(debug_ram + addr - DEBUG_RAM_START, bytes, len); - fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; @@ -118,8 +195,8 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) { uint32_t result = 0; D(fprintf(stderr, "dmi_read(0x%x) -> ", address)); - if (address >= DMI_DATA0 && address < DMI_DATA0 + datacount) { - result = data[address - DMI_DATA0]; + if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { + result = dmdata.read32(4 * (address - DMI_DATA0)); } else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) { result = ibuf[address - DMI_IBUF0]; } else { @@ -149,11 +226,24 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) } break; case DMI_ABSTRACTCS: - result = abstractcs; + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC7, abstractcs.autoexec7); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC6, abstractcs.autoexec6); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC5, abstractcs.autoexec5); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC4, abstractcs.autoexec4); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC3, abstractcs.autoexec3); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC2, abstractcs.autoexec2); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC1, abstractcs.autoexec1); + result = set_field(result, DMI_ABSTRACTCS_AUTOEXEC0, abstractcs.autoexec0); + result = set_field(result, DMI_ABSTRACTCS_CMDERR, abstractcs.cmderr); + result = set_field(result, DMI_ABSTRACTCS_BUSY, abstractcs.busy); + result = set_field(result, DMI_ABSTRACTCS_DATACOUNT, abstractcs.datacount); break; case DMI_ACCESSCS: result = progsize << DMI_ACCESSCS_PROGSIZE_OFFSET; break; + case DMI_COMMAND: + result = 0; + break; default: D(fprintf(stderr, "error\n")); return false; @@ -166,14 +256,74 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) bool debug_module_t::perform_abstract_command(uint32_t command) { - return false; + if (abstractcs.cmderr != abstractcs.CMDERR_NONE) + return true; + if (abstractcs.busy) { + abstractcs.cmderr = abstractcs.CMDERR_BUSY; + return true; + } + + if ((command >> 24) == 0) { + // register access + unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE); + bool write = get_field(command, AC_ACCESS_REGISTER_WRITE); + unsigned regno = get_field(command, AC_ACCESS_REGISTER_REGNO); + + if (regno < 0x1000 || regno >= 0x1020) { + abstractcs.cmderr = abstractcs.CMDERR_NOTSUP; + return true; + } + + unsigned regnum = regno - 0x1000; + + if (!halted[dmcontrol.hartsel]) { + abstractcs.cmderr = abstractcs.CMDERR_HALTRESUME; + return true; + } + + switch (size) { + case 2: + if (write) + write32(debug_rom_code, 0, lw(regnum, ZERO, DEBUG_EXCHANGE)); + else + write32(debug_rom_code, 0, sw(regnum, ZERO, DEBUG_EXCHANGE)); + break; + case 3: + if (write) + write32(debug_rom_code, 0, ld(regnum, ZERO, DEBUG_EXCHANGE)); + else + write32(debug_rom_code, 0, sd(regnum, ZERO, DEBUG_EXCHANGE)); + break; + /* + case 4: + if (write) + write32(debug_rom_code, 0, lq(regnum, ZERO, DEBUG_EXCHANGE)); + else + write32(debug_rom_code, 0, sq(regnum, ZERO, DEBUG_EXCHANGE)); + break; + */ + default: + abstractcs.cmderr = abstractcs.CMDERR_NOTSUP; + return true; + } + write32(debug_rom_code, 1, ebreak()); + + write32(debug_rom_entry, dmcontrol.hartsel, + jal(ZERO, DEBUG_ROM_CODE - (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel))); + write32(debug_rom_exception, dmcontrol.hartsel, + jal(ZERO, (DEBUG_ROM_ENTRY + 4 * dmcontrol.hartsel) - DEBUG_ROM_EXCEPTION)); + abstractcs.busy = true; + } else { + abstractcs.cmderr = abstractcs.CMDERR_NOTSUP; + } + return true; } bool debug_module_t::dmi_write(unsigned address, uint32_t value) { D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value)); - if (address >= DMI_DATA0 && address < DMI_DATA0 + datacount) { - data[address - DMI_DATA0] = value; + if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { + dmdata.write32(4 * (address - DMI_DATA0), value); return true; } else if (address >= DMI_IBUF0 && address < DMI_IBUF0 + progsize) { ibuf[address - DMI_IBUF0] = value; @@ -197,8 +347,22 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) } return true; - case DMI_ABSTRACTCS: + case DMI_COMMAND: return perform_abstract_command(value); + + case DMI_ABSTRACTCS: + abstractcs.autoexec7 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC7); + abstractcs.autoexec6 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC6); + abstractcs.autoexec5 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC5); + abstractcs.autoexec4 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC4); + abstractcs.autoexec3 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC3); + abstractcs.autoexec2 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC2); + abstractcs.autoexec1 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC1); + abstractcs.autoexec0 = get_field(value, DMI_ABSTRACTCS_AUTOEXEC0); + if (get_field(value, DMI_ABSTRACTCS_CMDERR) == abstractcs.CMDERR_NONE) { + abstractcs.cmderr = abstractcs.CMDERR_NONE; + } + break; } } return false; diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 5fae6a5..15ff66c 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -29,11 +29,48 @@ typedef struct { unsigned version; } dmcontrol_t; +typedef struct { + bool autoexec7; + bool autoexec6; + bool autoexec5; + bool autoexec4; + bool autoexec3; + bool autoexec2; + bool autoexec1; + bool autoexec0; + enum { + CMDERR_NONE = 0, + CMDERR_BUSY = 1, + CMDERR_NOTSUP = 2, + CMDERR_EXCEPTION = 3, + CMDERR_HALTRESUME = 4, + CMDERR_OTHER = 7 + } cmderr; + bool busy; + unsigned datacount; +} abstractcs_t; + +class debug_module_data_t : public abstract_device_t +{ + public: + debug_module_data_t(); + + bool load(reg_t addr, size_t len, uint8_t* bytes); + bool store(reg_t addr, size_t len, const uint8_t* bytes); + + uint32_t read32(reg_t addr) const; + void write32(reg_t addr, uint32_t value); + + uint8_t data[DEBUG_EXCHANGE_SIZE]; +}; + class debug_module_t : public abstract_device_t { public: debug_module_t(sim_t *sim); + void add_device(bus_t *bus); + bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); @@ -69,18 +106,19 @@ class debug_module_t : public abstract_device_t std::set interrupt; // Track which halt notifications from debugger to module are set. std::set halt_notification; - uint8_t debug_rom_entry[1024 * 4]; + uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE]; + uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE]; + uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE]; bool halted[1024]; + debug_module_data_t dmdata; void write32(uint8_t *rom, unsigned int index, uint32_t value); uint32_t read32(uint8_t *rom, unsigned int index); - static const unsigned datacount = 8; static const unsigned progsize = 8; dmcontrol_t dmcontrol; - uint32_t abstractcs; - uint32_t data[datacount]; + abstractcs_t abstractcs; uint32_t ibuf[progsize]; processor_t *current_proc() const; diff --git a/riscv/decode.h b/riscv/decode.h index c34b07e..e78a587 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -227,11 +227,17 @@ private: #define DEBUG_START 0x20000 #define DEBUG_ROM_ENTRY DEBUG_START -#define DEBUG_ROM_CODE (DEBUG_ROM_ENTRY + 1024 * 4) -#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_CODE + 4) -#define DEBUG_RAM_START (DEBUG_ROM_EXCEPTION + 256) +#define DEBUG_ROM_ENTRY_SIZE (1024 * 4) +#define DEBUG_ROM_CODE (DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE) +#define DEBUG_ROM_CODE_SIZE 256 +#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_CODE + DEBUG_ROM_CODE_SIZE) +#define DEBUG_ROM_EXCEPTION_SIZE 4 +#define DEBUG_RAM_START (DEBUG_ROM_EXCEPTION + DEBUG_ROM_EXCEPTION_SIZE) #define DEBUG_RAM_SIZE 64 #define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) #define DEBUG_END DEBUG_RAM_END +#define DEBUG_EXCHANGE 0x400 +#define DEBUG_EXCHANGE_SIZE 0x20 + #endif diff --git a/riscv/jtag_dtm.cc b/riscv/jtag_dtm.cc index 3750f9d..2ce194c 100644 --- a/riscv/jtag_dtm.cc +++ b/riscv/jtag_dtm.cc @@ -5,7 +5,7 @@ #include "debug_module.h" #include "debug_defines.h" -#if 1 +#if 0 # define D(x) x #else # define D(x) diff --git a/riscv/processor.cc b/riscv/processor.cc index 82f7444..064c452 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -213,6 +213,15 @@ void processor_t::take_trap(trap_t& t, reg_t epc) t.get_badaddr()); } + if (state.dcsr.cause) { + if (t.cause() == CAUSE_BREAKPOINT) { + state.pc = debug_rom_entry(); + } else { + state.pc = DEBUG_ROM_EXCEPTION; + } + return; + } + if (t.cause() == CAUSE_BREAKPOINT && ( (state.prv == PRV_M && state.dcsr.ebreakm) || (state.prv == PRV_H && state.dcsr.ebreakh) || @@ -222,11 +231,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) return; } - if (state.dcsr.cause) { - state.pc = DEBUG_ROM_EXCEPTION; - return; - } - // by default, trap to M-mode, unless delegated to S-mode reg_t bit = t.cause(); reg_t deleg = state.medeleg; diff --git a/riscv/sim.cc b/riscv/sim.cc index 461ae6a..033f12b 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -41,7 +41,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n", memsz, memsz0); - bus.add_device(DEBUG_START, &debug_module); + debug_module.add_device(&bus); debug_mmu = new mmu_t(this, NULL); -- 2.30.2