From 1a71417b89f20f5637f60b6a032f8ba9cfc95378 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 5 Nov 2019 15:48:48 -0800 Subject: [PATCH] fastmodel: Handle "special" vector regs without calling into IRIS. These registers don't have an architectural equivalent, but they may need to be accessed by generic code, for instance the code that checkpoints a thread context. Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/fastmodel/iris/arm/thread_context.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index c48ade817..4ef879488 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -190,6 +190,11 @@ const ArmISA::VecRegContainer & ArmThreadContext::readVecReg(const RegId ®_id) const { const RegIndex idx = reg_id.index(); + // Ignore accesses to registers which aren't architected. gem5 defines a + // few extra registers which it uses internally in the implementation of + // some instructions. + if (idx >= vecRegIds.size()) + return vecRegs.at(idx); ArmISA::VecRegContainer ® = vecRegs.at(idx); iris::ResourceReadResult result; -- 2.30.2