From 1a7ed57c840dcb0401f1a67c6763a89f7d2686d2 Mon Sep 17 00:00:00 2001
From: Tamar Christina <tamar.christina@arm.com>
Date: Thu, 9 Nov 2017 15:45:00 +0000
Subject: [PATCH] Add the operand encoding types for the new Armv8.2-a
 back-ported instructions. These are to be used later when the new
 instructions are added.

opcodes/
	* aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
	(QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
	(QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
	(QL_STLW, QL_STLX): New.
---
 opcodes/ChangeLog     |  7 ++++
 opcodes/aarch64-tbl.h | 90 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d2998700c0c..4056d884081 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-11-09  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
+	(QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
+	(QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
+	(QL_STLW, QL_STLX): New.
+
 2017-11-09  Tamar Christina  <tamar.christina@arm.com>
 
 	* aarch64-asm.h (ins_addr_offset): New.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5ebd788e1f3..41f7275bf08 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1995,6 +1995,96 @@
   QLF3(V_2S, V_8B,  S_B),\
   QLF3(V_4S, V_16B, S_B),\
 }
+
+/* e.g. SHA512H <Qd>, <Qn>, <Vm>.2D.  */
+#define QL_SHA512UPT			\
+{				\
+  QLF3(S_Q, S_Q, V_2D),		\
+}
+
+/* e.g. SHA512SU0 <Vd.2D>, <Vn>.2D.  */
+#define QL_V2SAME2D		\
+{				\
+  QLF2(V_2D, V_2D),		\
+}
+
+/* e.g. SHA512SU1 <Vd>.2D, <Vn>.2D, <Vm>.2D>.  */
+#define QL_V3SAME2D		\
+{				\
+  QLF3(V_2D, V_2D, V_2D),	\
+}
+
+/* e.g. EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B.  */
+#define QL_V4SAME16B			\
+{					\
+  QLF4(V_16B, V_16B, V_16B, V_16B),	\
+}
+
+/* e.g. SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S.  */
+#define QL_V4SAME4S			\
+{					\
+  QLF4(V_4S, V_4S, V_4S, V_4S),		\
+}
+
+/* e.g. XAR <Vd>.2D, <Vn>.2D, <Vm>.2D, #<imm6>.  */
+#define QL_XAR			\
+{				\
+  QLF4(V_2D, V_2D, V_2D, imm_0_63),	\
+}
+
+/* e.g. SM3TT1A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>].  */
+#define QL_SM3TT	\
+{			\
+  QLF3(V_4S, V_4S, S_S),\
+}
+
+/* e.g. FMLAL  <Vd>.2S, <Vn>.2H, <Vm>.2H.  */
+#define QL_V3FML2S \
+{		   \
+  QLF3(V_2S, V_2H, V_2H),\
+}
+
+/* e.g. FMLAL  <Vd>.4S, <Vn>.4H, <Vm>.4H.  */
+#define QL_V3FML4S \
+{		   \
+  QLF3(V_4S, V_4H, V_4H),\
+}
+
+/* e.g. FMLAL  <Vd>.2S, <Vn>.2H, <Vm>.H[<index>].  */
+#define QL_V2FML2S \
+{		   \
+  QLF3(V_2S, V_2H, S_H),\
+}
+
+/* e.g. FMLAL  <Vd>.4S, <Vn>.4H, <Vm>.H[<index>].  */
+#define QL_V2FML4S \
+{		   \
+  QLF3(V_4S, V_4H, S_H),\
+}
+
+/* e.g. RMIF <Xn>, #<shift>, #<mask>.  */
+#define QL_RMIF  \
+{		  \
+  QLF3(X, imm_0_63, imm_0_15),\
+}
+
+/* e.g. SETF8 <Wn>.  */
+#define QL_SETF \
+{		\
+  QLF1(W),	\
+}
+
+/* e.g. STLURB <Wt>, [<Xn|SP>{,#<simm>}].  */
+#define QL_STLW \
+{		\
+  QLF2(W, NIL),	\
+}
+
+/* e.g. STLURB <Xt>, [<Xn|SP>{,#<simm>}].  */
+#define QL_STLX \
+{		\
+  QLF2(X, NIL),	\
+}
 
 /* Opcode table.  */
 
-- 
2.30.2