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a/simple_v_extension/openpower_2020.tex b/simple_v_extension/openpower_2020.tex index 7bed556f1..f2b614215 100644 --- a/simple_v_extension/openpower_2020.tex +++ b/simple_v_extension/openpower_2020.tex @@ -125,7 +125,7 @@ \begin{itemize} \item Hybrid - integrated. The CPU \textit{is} the GPU.\\ The GPU \textit{is} the CPU. The VPU \textit{is} the CPU.\\ - \textit{There is No Separate VPU/GPU Pipeline} + \textit{There is No Separate VPU/GPU Pipeline}\\ \vspace{9pt} \item written in nmigen (a python-based HDL). Not VHDL\\ not Verilog (definitely not Chisel3/Scala)\\ @@ -142,9 +142,11 @@ \begin{itemize} \item CDC 6600 is a design from 1965. The \textit{augmentations} are not.\\ - Help from Mitch Alsup includes "precise exceptions", \\ + Help from Mitch Alsup includes \textit{precise exceptions}, \\ multi-issue and more. Academic literature on 6600 utterly misleading. - 6600 Scoreboards completely underestimated. + 6600 Scoreboards completely underestimated (Seymour Cray and + James Thornton + solved problems they didn't realise existed elsewhere!) \item Front-end Vector ISA, back-end "Predicated (masked) SIMD"\\ nmigen (python OO) strategically critical to achieving this. \item Out-of-order combined with Simple-V allows scalar operations\\ @@ -155,7 +157,54 @@ \end{itemize} } +\frame{\frametitle{Why nmigen? (but first: evaluate other HDLs)} + \begin{itemize} + \item Verilog: designed in the 1980s purely for doing unit tests (!) + \item VHDL: again, a 1980s-era "Procedural" language (BASIC, Fortran). + Does now have "records" which is nice. + \item Chisel3 / Scala: OO, but very obscure (20th on index) + \item pyrtl: not large enough community + \item MyHDL: subset of python only + \vspace{9pt} + \item Slowly forming a set of criteria: must be OO (python), must have + wide adoption (python), must have good well-established + programming practices already in place (python), must be + easy to learn (python) + \item HDL itself although a much smaller community must have the same + criteria. Only nmigen meets that criteria. + + \end{itemize} +} + +\frame{\frametitle{Why nmigen?} + + \begin{itemize} + \item Uses python to build an AST (Abstract Syntax Tree). + Actually hands that over to yosys (to create ILANG file) + after which verilog can (if necessary) be created + \item Deterministic synthesiseable behaviour (Signals are declared + with their reset pattern: no more forgetting "if rst" block). + \item python OO programming techniques can be deployed. classes + and functions created which pass in parameters which change + what HDL is created (IEEE754 FP16 / 32 / 64 for example) + \item python-based for-loops can e.g. read CSV files then generate + a hierarchical nested suite of HDL Switch / Case statements + (this is how the Libre-soc PowerISA decoder is implemented) + \item extreme OO abstraction can even be used to create "dynamic + partitioned Signals" that have the same operator-overloaded + "add", "subtract", "greater-than" operators + + \end{itemize} +} + +\frame{\frametitle{nmigen PowerISA Decoder} + +\begin{center} +\includegraphics[width=0.55\textwidth]{2020-09-09_21-04.png} +\end{center} + +} \frame{\frametitle{Summary} \begin{itemize} -- 2.30.2