From 1aa846282682a085fe5ff7e9eff6a2c69b0c0226 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Thu, 26 Mar 2020 13:31:38 +0100 Subject: [PATCH] Re: [libre-riscv-dev] cache SRAM organisation --- 5d/832a18daf516839bee02cfbd1e355da6966e09 | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 5d/832a18daf516839bee02cfbd1e355da6966e09 diff --git a/5d/832a18daf516839bee02cfbd1e355da6966e09 b/5d/832a18daf516839bee02cfbd1e355da6966e09 new file mode 100644 index 0000000..7b6fc42 --- /dev/null +++ b/5d/832a18daf516839bee02cfbd1e355da6966e09 @@ -0,0 +1,93 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Thu, 26 Mar 2020 12:31:41 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jHRfg-00060n-Ub; Thu, 26 Mar 2020 12:31:40 +0000 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) id 1jHRfe-00060h-SJ + for libre-riscv-dev@lists.libre-riscv.org; Thu, 26 Mar 2020 12:31:38 +0000 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 9D8D311C05B7 + for ; + Thu, 26 Mar 2020 13:31:38 +0100 (CET) +Message-ID: <350514fc6cf0b578804b85775beb8c0e039cab1e.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Thu, 26 Mar 2020 13:31:38 +0100 +In-Reply-To: +References: + <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> + + <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> + + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] cache SRAM organisation +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============6270029082426105516==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============6270029082426105516== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-hp0XbRkY5ds+MbwWugCO" + + +--=-hp0XbRkY5ds+MbwWugCO +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +(Sorry send to early) + + +> .In theory on a single port SRAM + +In theory on a single port SRAM the write data input and the Q data output = +could be on opposite sides of the block but I will make sure that these pin= +s are on the same side of the block and close together so you don't need mu= +ch wire to connect a pass-through MUX. + +greets, +Staf. + + + +--=-hp0XbRkY5ds+MbwWugCO-- + + + +--===============6270029082426105516== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============6270029082426105516==-- + + + -- 2.30.2