From 1aaefeaf954e9548f4ed0fc13d2ff6ee7de8235a Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 9 Jan 2024 11:43:55 +0000
Subject: [PATCH] Bug 1244: added images

---
 .../fosdem2024_ddffirst.tex                   | 32 +++++++++++--------
 1 file changed, 19 insertions(+), 13 deletions(-)

diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
index 56b43a1b5..4548aa842 100644
--- a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
+++ b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
@@ -98,17 +98,6 @@
 
 
 
-\frame{\frametitle{Simple SBC-style SoC}
-
-\begin{center}
-\includegraphics[width=0.6\textwidth]{pospopcount.png}
-\end{center}
-
-}
-
-
-
-
 \begin{frame}[fragile]
 \frametitle{Simple-V CMPI in a nutshell}
 
@@ -141,8 +130,8 @@ function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
         \item ARM SVE: https://arxiv.org/pdf/1803.06185.pdf
         \item more: wikipedia Vector processor page: Fault/Fail First
         \vspace{10pt}
-		\item Load/Store is Memory to/from Register, \\
-              what about Register to Register?
+		\item Load/Store is Memory to/from Register, what about
+              Register to Register?
         \item Register-to-register: "Data-Dependent Fail-First."
         \item Z80 LDIR: Mem-Register, CPIR: Register-Register
 	\end{itemize}
@@ -190,6 +179,23 @@ for (i = 0; i < VL; i++)
 	\lstinputlisting[language={}]{pospopcount.c}
 	
 }
+
+\frame{\frametitle{Simple SBC-style SoC}
+	
+	\begin{center}
+		\includegraphics[width=0.6\textwidth]{pospopcount.png}
+	\end{center}
+	
+}
+
+\frame{\frametitle{Simple SBC-style SoC}
+	
+	\begin{center}
+		\includegraphics[width=0.6\textwidth]{array_popcnt.png}
+	\end{center}
+	
+}
+
 \frame{\frametitle{Pospopcount.s}
 
 
-- 
2.30.2