From 1aca708a10492637b144adc79a9351c37add6f0a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 May 2020 18:51:08 +0100 Subject: [PATCH] div probably uses ALU not Logical, needs double-checking though --- src/soc/fu/div/pipe_data.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py index e634a505..52ac0d92 100644 --- a/src/soc/fu/div/pipe_data.py +++ b/src/soc/fu/div/pipe_data.py @@ -1,10 +1,10 @@ from nmigen import Signal, Const from soc.fu.pipe_data import IntegerData from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec -from soc.fu.logical.pipe_data import LogicalInputData +from soc.fu.alu.pipe_data import ALUInputData # TODO: check this from soc.fu.logical.logical_input_record import CompLogicalOpSubset class DivPipeSpec(CommonPipeSpec): - regspec = (LogicalInputData.regspec, ALUOutputData.regspec) + regspec = (ALUInputData.regspec, ALUOutputData.regspec) opsubsetkls = CompLogicalOpSubset -- 2.30.2