From 1adfb304b97bb036f2e4312fbbf47de11f05b861 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 21 Nov 2020 21:53:52 +0000 Subject: [PATCH] --- openpower/sv/vector_swizzle.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn index 5b578b7e0..451699412 100644 --- a/openpower/sv/vector_swizzle.mdwn +++ b/openpower/sv/vector_swizzle.mdwn @@ -5,7 +5,7 @@ 3D GPU operations on batches of vec2, vec3 and vec4 often require re-ordering of the elements in an "out of lane" fashion with respect to standard high performance non-GPU-centric Vector Processors. Examples include: * Normalisation of Vectors of XYZ with respect to one dimension -* Alteration of ARGB pixel vectors wuth respect to opacity (A) +* Alteration of ARGB pixel vectors with respect to opacity (A) * Adjustment of YUV vectors with respect to luminosity and many more. Lane-based Vector Processors not having the 2/3/4 inter-lane crossing have some difficulty processing such data and require it to be pushed into memory and retrieved, which is prohibitively costly in both instructions, time, and power consumption. -- 2.30.2