From 1aec5f49bab3f7974b38a5ff58e75e35670b1fb3 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 12 Jul 2018 13:14:39 +0100
Subject: [PATCH] add slides

---
 shakti/m_class/AC97.mdwn                    |  1 +
 shakti/m_class/ULPI.mdwn                    |  2 +-
 shakti/m_class/USB3.mdwn                    |  2 +-
 shakti/m_class/libre_riscv_chennai_2018.tex | 37 +++++++++++++++++----
 4 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/shakti/m_class/AC97.mdwn b/shakti/m_class/AC97.mdwn
index 0c4ec5e3a..68dd80780 100644
--- a/shakti/m_class/AC97.mdwn
+++ b/shakti/m_class/AC97.mdwn
@@ -5,6 +5,7 @@
 * <https://en.wikipedia.org/wiki/AC%2797>
 * <http://hands.com/~lkcl/ac97_r23.pdf> AC97 datasheet
 * <http://realtek.info/pdf/alc850.pdf> example AC97 8-channel datasheet
+* <https://github.com/www-asics-ws/mpac>
 
 
 Question: how does AC97 fit in with [[I2S]]?
diff --git a/shakti/m_class/ULPI.mdwn b/shakti/m_class/ULPI.mdwn
index 483cfc687..6e9d7bf2d 100644
--- a/shakti/m_class/ULPI.mdwn
+++ b/shakti/m_class/ULPI.mdwn
@@ -25,5 +25,5 @@ BSD I guess...(fix me)
 * <https://github.com/mossmann/daisho/blob/master/sw/fpga/common/usb3/usb2_ulpi.v> (BSD)
 * <https://opencores.org/project,usb>
 * <https://github.com/alexforencich/verilog-wishbone>
-
+* <https://github.com/www-asics-ws/usb2_dev>
 
diff --git a/shakti/m_class/USB3.mdwn b/shakti/m_class/USB3.mdwn
index 49a88000b..51a3436a4 100644
--- a/shakti/m_class/USB3.mdwn
+++ b/shakti/m_class/USB3.mdwn
@@ -1,4 +1,4 @@
 # USB3 (Pipe)
 
 * TUSB1310A example PHY <http://www.ti.com/lit/gpn/tusb1310a>
-
+* Daisho <https://github.com/mossmann/daisho>
diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex
index a65a0d869..ab62b58f1 100644
--- a/shakti/m_class/libre_riscv_chennai_2018.tex
+++ b/shakti/m_class/libre_riscv_chennai_2018.tex
@@ -27,14 +27,18 @@
 \frame{\frametitle{Credits and Acknowledgements}
 
  \begin{itemize}
-   \item The Designers of RISC-V\vspace{8pt}
-   \item The RISC-V Foundation\vspace{8pt}
-   \item The Shakti Group, and IIT Madras RISE Group\vspace{8pt}
-   \item Prof. G S Madhusudan\vspace{8pt}
-   \item Neel Gala\vspace{8pt}
-   \item Rishabh Jain\vspace{8pt}
-   \item Members of the RISC-V Open Groups (SW/HW/ISA)\vspace{8pt}
+   \item The Designers of RISC-V
+   \item The RISC-V Foundation
+   \item The Shakti Group, and IIT Madras RISE Group
+   \item Prof. G S Madhusudan
+   \item Neel Gala
+   \item Rishabh Jain
+   \item Members of the RISC-V Open Groups (SW/HW/ISA)
    \item Libre and Open Software and Hardware Communities
+   \item Richard Herveille (RoaLogic), Edmund Humenberger, Clifford Wolf
+	     (Symbiotica EDA), Rudi (Asics.ws),
+	     Alex Forenchich, LowRISC Team
+    \item Anonymous Sponsor
   \end{itemize}
 }
 
@@ -345,6 +349,25 @@
 }
 
 
+\frame{\frametitle{Interesting Missing Stuff [2] - AC97/I2S, USB2 PHY}
+
+
+\begin{itemize}
+   \item Rudi (Asics.ws) donating time to create a Multi-Protocol
+	     Audio Controller: AC97, PCM, PDM, I2S\\
+	   http://libre-riscv.org/shakti/m\_class/AC97/
+	\item USB2 is... convoluted.  UTMI-ULPI-USB2 PHY\\
+		USB2-PHY not confirmed (Rudi has one)\\
+		Also Rudi has DDR (8-pin) variant of ULPI
+	   http://libre-riscv.org/shakti/m\_class/ULPI/
+	\item USB3 not necessarily a good idea to put into Libre-RISCV\\
+		Daisho USB3 Pipe exists, TUSB1310a PHY is 175 pin FBGA!
+	\item Libre SD/MMC typically at "Open" Level 20MB/sec appx.
+		Full spec and eMMC requires membership.
+  \end{itemize}
+}
+
+
 \frame{\frametitle{TODO}
 
  \begin{itemize}
-- 
2.30.2