From 1af966836af3e4c21fbf212c0d4b91120b0e8184 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 22 Dec 2020 14:54:36 +0000 Subject: [PATCH] rename to memory from add --- experiments12/Makefile | 10 +++++----- experiments12/{add.py => memory.py} | 8 +++++++- experiments12/nets.txt | 2 +- 3 files changed, 13 insertions(+), 7 deletions(-) rename experiments12/{add.py => memory.py} (68%) diff --git a/experiments12/Makefile b/experiments12/Makefile index 2343504..acd76db 100755 --- a/experiments12/Makefile +++ b/experiments12/Makefile @@ -6,7 +6,7 @@ # YOSYS_FLATTEN = Yes CHIP = chip - CORE = add + CORE = memory MARGIN = 2 BOOMOPT = # -A BOOGOPT = @@ -18,14 +18,14 @@ # RM_CHIP = Yes NETLISTS = $(shell cat nets.txt) -# PATTERNS = add_r +# PATTERNS = memory_r include ./mk/design-flow.mk -blif: add.blif -vst: add.vst +blif: memory.blif +vst: memory.vst lvx: lvx-chip_cts_r druc: druc-chip_cts_r @@ -40,4 +40,4 @@ cif: chip_cts_r.cif view: cgt-chip_cts_r -sim: asimut-add_cts_r +sim: asimut-memory_cts_r diff --git a/experiments12/add.py b/experiments12/memory.py similarity index 68% rename from experiments12/add.py rename to experiments12/memory.py index 68aecc1..84fcdcf 100644 --- a/experiments12/add.py +++ b/experiments12/memory.py @@ -11,6 +11,12 @@ class ADD(Elaboratable): def elaborate(self, platform): m = Module() m.d.sync += self.f.eq(self.a + self.b) + #a = Signal(9) + #q = Signal(64) + #d = Signal(64) + #we = Signal(8) + #sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we) + #m.submodules += sram return m @@ -21,4 +27,4 @@ def create_ilang(dut, ports, test_name): if __name__ == "__main__": alu = ADD(width=4) - create_ilang(alu, [alu.a, alu.b, alu.f], "add") + create_ilang(alu, [alu.a, alu.b, alu.f], "memory") diff --git a/experiments12/nets.txt b/experiments12/nets.txt index 76d4bb8..2142c3a 100644 --- a/experiments12/nets.txt +++ b/experiments12/nets.txt @@ -1 +1 @@ -add +memory -- 2.30.2