From 1b0dcfa9aa662dec60f1c07d8d611064b0eb5911 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 29 Mar 2023 22:27:46 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index dca3bed20..319ff875c 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -286,17 +286,19 @@ an instruction Defined Word space must have the exact same Instruction and exact same Instruction Encoding in all spaces (including being RESERVED if UnVectoriseable) or not be allocated at all. This is required as an inviolate hard rule governing Primary Opcode 9 -that may not be revoked under any circumstances* +that may not be revoked under any circumstances. A useful way to think +of this is that the Prefix Encoding is, like the 8086 REP instruction, +an independent 32-bit Defined Word.* # Remapped Encoding (`RM[0:23]`) In the SVP64 Vector Prefix spaces, the 24 bits 8-31 are termed `RM`. Bits 32-37 are the Primary Opcode of the Suffix "Defined Word". 38-63 are the remainder of the Defined Word. Note that the new EXT232-263 SVP64 area it is obviously mandatory -that bit 32 is required to be set. +that bit 32 is required to be set to 1. | 0-5 | 6 | 7 | 8-31 | 32-37 | 38-64 |Description | -|-----|---|---|----------|--------|----------|----------------------------------| +|-----|---|---|----------|--------|----------|-----------------------| | PO | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263 | | PO | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063 | -- 2.30.2