From 1b1edcfa616bfdff456dd08199063cc551e6edf9 Mon Sep 17 00:00:00 2001 From: David Edelsohn Date: Mon, 10 Feb 2003 15:13:01 -0500 Subject: [PATCH] - Really commit ctz patch. From-SVN: r62649 --- gcc/config/rs6000/rs6000.md | 70 +++++++++++++++++++++++++++---------- 1 file changed, 51 insertions(+), 19 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 142159d6fe5..f8144232096 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2364,15 +2364,21 @@ (const_int 0)))] "") -(define_expand "ffssi2" +(define_insn "clzsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] + "" + "{cntlz|cntlzw} %0,%1") + +(define_expand "ctzsi2" [(set (match_dup 2) - (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) + (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (parallel [(set (match_dup 3) (and:SI (match_dup 1) - (match_dup 2))) - (clobber (scratch:CC))]) + (match_dup 2))) + (clobber (scratch:CC))]) (set (match_dup 4) (clz:SI (match_dup 3))) (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (minus:SI (const_int 32) (match_dup 4)))] + (minus:SI (const_int 31) (match_dup 4)))] "" { operands[2] = gen_reg_rtx (SImode); @@ -2380,12 +2386,22 @@ operands[4] = gen_reg_rtx (SImode); }) -(define_insn "clzsi2" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] +(define_expand "ffssi2" + [(set (match_dup 2) + (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) + (parallel [(set (match_dup 3) (and:SI (match_dup 1) + (match_dup 2))) + (clobber (scratch:CC))]) + (set (match_dup 4) (clz:SI (match_dup 3))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (minus:SI (const_int 32) (match_dup 4)))] "" - "{cntlz|cntlzw} %0,%1") - + { + operands[2] = gen_reg_rtx (SImode); + operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_reg_rtx (SImode); + }) + (define_expand "mulsi3" [(use (match_operand:SI 0 "gpc_reg_operand" "")) (use (match_operand:SI 1 "gpc_reg_operand" "")) @@ -6739,15 +6755,21 @@ (const_int 0)))] "") -(define_expand "ffsdi2" +(define_insn "clzdi2" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] + "TARGET_POWERPC64" + "cntlzd %0,%1") + +(define_expand "ctzdi2" [(set (match_dup 2) - (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) + (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) (parallel [(set (match_dup 3) (and:DI (match_dup 1) - (match_dup 2))) - (clobber (scratch:CC))]) + (match_dup 2))) + (clobber (scratch:CC))]) (set (match_dup 4) (clz:DI (match_dup 3))) (set (match_operand:DI 0 "gpc_reg_operand" "=r") - (minus:DI (const_int 64) (match_dup 4)))] + (minus:DI (const_int 63) (match_dup 4)))] "TARGET_POWERPC64" { operands[2] = gen_reg_rtx (DImode); @@ -6755,11 +6777,21 @@ operands[4] = gen_reg_rtx (DImode); }) -(define_insn "clzdi2" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] +(define_expand "ffsdi2" + [(set (match_dup 2) + (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) + (parallel [(set (match_dup 3) (and:DI (match_dup 1) + (match_dup 2))) + (clobber (scratch:CC))]) + (set (match_dup 4) (clz:DI (match_dup 3))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r") + (minus:DI (const_int 64) (match_dup 4)))] "TARGET_POWERPC64" - "cntlzd %0,%1") + { + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_reg_rtx (DImode); + operands[4] = gen_reg_rtx (DImode); + }) (define_insn "muldi3" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") -- 2.30.2