From 1b23890e0d8022747061d805ac471e4ac73dc7b9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 16 Jan 2019 22:05:52 +0100 Subject: [PATCH] soc/cores/clock: allow ClockSignal to be used for clkin --- litex/soc/cores/clock.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index a007bf74..44858447 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -33,7 +33,7 @@ class S7Clocking(Module, AutoCSR): def register_clkin(self, clkin, freq): self.clkin = Signal() - if isinstance(clkin, Signal): + if isinstance(clkin, (Signal, ClockSignal)): self.comb += self.clkin.eq(clkin) elif isinstance(clkin, Record): self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin) @@ -224,7 +224,7 @@ class USClocking(Module, AutoCSR): def register_clkin(self, clkin, freq): self.clkin = Signal() - if isinstance(clkin, Signal): + if isinstance(clkin, (Signal, ClockSignal)): self.comb += self.clkin.eq(clkin) elif isinstance(clkin, Record): self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin) @@ -413,7 +413,7 @@ class ECP5PLL(Module): assert freq >= clki_freq_min assert freq <= clki_freq_max self.clkin = Signal() - if isinstance(clkin, Signal): + if isinstance(clkin, (Signal, ClockSignal)): self.comb += self.clkin.eq(clkin) else: raise ValueError -- 2.30.2