From 1b5caf56fb8bbf20ecf3d9b0ae03ba9cf543c7f4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 11 Feb 2020 17:50:26 +0100 Subject: [PATCH] soc: fix busword typo --- litex/soc/integration/soc.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index c448ebf8..e4c36ae9 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -812,9 +812,9 @@ class SoC(Module): # Add Memory regions for name, memory, mapaddr, mmap in self.csr_bankarray.srams: self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion( - origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr), - busworkd = self.csr.data_width, - obj = memory)) + origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr), + busword = self.csr.data_width, + obj = memory)) # Sort CSR regions by origin self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)} -- 2.30.2