From 1b629cb65999f25bd5664c44181a165c84362ffa Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Mon, 8 Jun 2020 18:48:25 +0200 Subject: [PATCH] Connect dramcore to SoC bus in ECPIX-5 example --- examples/ecpix5.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/ecpix5.py b/examples/ecpix5.py index d4251bc..3848436 100644 --- a/examples/ecpix5.py +++ b/examples/ecpix5.py @@ -152,7 +152,9 @@ class DDR3SoC(CPUSoC, Elaboratable): geom_settings = ddrmodule.geom_settings, timing_settings = ddrmodule.timing_settings, clk_freq = clk_freq) - #self._decoder.add(self.dramcore.bus, addr=dramcore_addr) + self._decoder.add(self.dramcore.bus, addr=dramcore_addr) + + self.dramport = self.dramcore.crossbar.get_port() self.memory_map = self._decoder.bus.memory_map -- 2.30.2