From 1b64bfa933745294667158d0ce22180780b2a22e Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 7 Feb 2011 19:23:11 -0800
Subject: [PATCH] Stats: Back out broken update.

---
 .../ref/alpha/linux/inorder-timing/config.ini |   13 +-
 .../ref/alpha/linux/inorder-timing/simout     |    8 +-
 .../ref/alpha/linux/inorder-timing/stats.txt  |   10 +-
 .../ref/alpha/linux/o3-timing/config.ini      |   13 +-
 .../00.hello/ref/alpha/linux/o3-timing/simout |    8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |   31 +-
 .../ref/alpha/linux/simple-atomic/config.ini  |   11 +-
 .../ref/alpha/linux/simple-atomic/simout      |    8 +-
 .../ref/alpha/linux/simple-atomic/stats.txt   |   24 +-
 .../config.ini                                |   14 +-
 .../ruby.stats                                |   30 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   26 +-
 .../config.ini                                |   68 +-
 .../ruby.stats                                |   54 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   26 +-
 .../config.ini                                |   68 +-
 .../ruby.stats                                |   94 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    8 +-
 .../stats.txt                                 |   26 +-
 .../config.ini                                |   95 +-
 .../ruby.stats                                |  164 +--
 .../simple-timing-ruby-MOESI_hammer/simout    |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   30 +-
 .../alpha/linux/simple-timing-ruby/config.ini |  186 ++-
 .../alpha/linux/simple-timing-ruby/ruby.stats |  300 ++---
 .../ref/alpha/linux/simple-timing-ruby/simout |    8 +-
 .../alpha/linux/simple-timing-ruby/stats.txt  |   26 +-
 .../ref/alpha/linux/simple-timing/config.ini  |   13 +-
 .../ref/alpha/linux/simple-timing/simout      |   12 +-
 .../ref/alpha/linux/simple-timing/stats.txt   |   26 +-
 .../ref/alpha/tru64/o3-timing/config.ini      |   13 +-
 .../00.hello/ref/alpha/tru64/o3-timing/simout |    8 +-
 .../ref/alpha/tru64/o3-timing/stats.txt       |   30 +-
 .../ref/alpha/tru64/simple-atomic/config.ini  |   13 +-
 .../ref/alpha/tru64/simple-atomic/simout      |   10 +-
 .../ref/alpha/tru64/simple-atomic/stats.txt   |   24 +-
 .../config.ini                                |   14 +-
 .../ruby.stats                                |   26 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   26 +-
 .../config.ini                                |   68 +-
 .../ruby.stats                                |   46 +-
 .../simout                                    |    8 +-
 .../stats.txt                                 |   26 +-
 .../config.ini                                |   68 +-
 .../ruby.stats                                |   62 +-
 .../simple-timing-ruby-MOESI_CMP_token/simout |    8 +-
 .../stats.txt                                 |   24 +-
 .../config.ini                                |   97 +-
 .../ruby.stats                                |  164 +--
 .../simple-timing-ruby-MOESI_hammer/simout    |   10 +-
 .../simple-timing-ruby-MOESI_hammer/stats.txt |   30 +-
 .../alpha/tru64/simple-timing-ruby/config.ini |  186 ++-
 .../alpha/tru64/simple-timing-ruby/ruby.stats |  308 +++--
 .../ref/alpha/tru64/simple-timing-ruby/simout |    8 +-
 .../alpha/tru64/simple-timing-ruby/stats.txt  |   24 +-
 .../ref/alpha/tru64/simple-timing/config.ini  |   13 +-
 .../ref/alpha/tru64/simple-timing/simout      |   12 +-
 .../ref/alpha/tru64/simple-timing/stats.txt   |   26 +-
 .../ref/arm/linux/o3-timing/config.ini        |   13 +-
 .../00.hello/ref/arm/linux/o3-timing/simout   |    8 +-
 .../ref/arm/linux/o3-timing/stats.txt         |   30 +-
 .../ref/arm/linux/simple-atomic/config.ini    |   13 +-
 .../ref/arm/linux/simple-atomic/simout        |   10 +-
 .../ref/arm/linux/simple-atomic/stats.txt     |   24 +-
 .../ref/arm/linux/simple-timing/config.ini    |   13 +-
 .../ref/arm/linux/simple-timing/simout        |    8 +-
 .../ref/arm/linux/simple-timing/stats.txt     |   26 +-
 .../ref/mips/linux/inorder-timing/config.ini  |   13 +-
 .../ref/mips/linux/inorder-timing/simout      |    8 +-
 .../ref/mips/linux/inorder-timing/stats.txt   |   10 +-
 .../ref/mips/linux/o3-timing/config.ini       |   13 +-
 .../00.hello/ref/mips/linux/o3-timing/simout  |    8 +-
 .../ref/mips/linux/o3-timing/stats.txt        |   30 +-
 .../ref/mips/linux/simple-atomic/config.ini   |   11 +-
 .../ref/mips/linux/simple-atomic/simout       |    8 +-
 .../ref/mips/linux/simple-atomic/stats.txt    |   24 +-
 .../mips/linux/simple-timing-ruby/config.ini  |  189 ++-
 .../ref/mips/linux/simple-timing-ruby/simout  |    8 +-
 .../mips/linux/simple-timing-ruby/stats.txt   |   26 +-
 .../ref/mips/linux/simple-timing/config.ini   |   13 +-
 .../ref/mips/linux/simple-timing/simout       |   12 +-
 .../ref/mips/linux/simple-timing/stats.txt    |   26 +-
 .../ref/power/linux/o3-timing/config.ini      |   13 +-
 .../00.hello/ref/power/linux/o3-timing/simerr |    2 +-
 .../00.hello/ref/power/linux/o3-timing/simout |    8 +-
 .../ref/power/linux/o3-timing/stats.txt       |   29 +-
 .../ref/power/linux/simple-atomic/config.ini  |   11 +-
 .../ref/power/linux/simple-atomic/simerr      |    2 +-
 .../ref/power/linux/simple-atomic/simout      |    8 +-
 .../ref/power/linux/simple-atomic/stats.txt   |   26 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   11 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   24 +-
 .../sparc/linux/simple-timing-ruby/config.ini |  189 ++-
 .../sparc/linux/simple-timing-ruby/ruby.stats |  312 +++--
 .../ref/sparc/linux/simple-timing-ruby/simout |    8 +-
 .../sparc/linux/simple-timing-ruby/stats.txt  |   24 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   13 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   24 +-
 .../00.hello/ref/x86/linux/o3-timing/simerr   |   16 +-
 .../00.hello/ref/x86/linux/o3-timing/simout   |   14 +-
 .../ref/x86/linux/o3-timing/stats.txt         |  437 ++++++
 .../ref/x86/linux/simple-atomic/config.ini    |    9 +-
 .../ref/x86/linux/simple-atomic/simout        |   10 +-
 .../ref/x86/linux/simple-atomic/stats.txt     |   26 +-
 .../x86/linux/simple-timing-ruby/config.ini   |   10 +-
 .../x86/linux/simple-timing-ruby/ruby.stats   |   49 +-
 .../ref/x86/linux/simple-timing-ruby/simout   |   10 +-
 .../x86/linux/simple-timing-ruby/stats.txt    |   26 +-
 .../ref/x86/linux/simple-timing/config.ini    |    9 +-
 .../ref/x86/linux/simple-timing/simout        |   10 +-
 .../ref/x86/linux/simple-timing/stats.txt     |   26 +-
 .../ref/alpha/linux/o3-timing/config.ini      |   15 +-
 .../ref/alpha/linux/o3-timing/simout          |    8 +-
 .../ref/alpha/linux/o3-timing/stats.txt       |   37 +-
 .../ref/sparc/linux/o3-timing/config.ini      |   13 +-
 .../ref/sparc/linux/o3-timing/simout          |    8 +-
 .../ref/sparc/linux/o3-timing/stats.txt       |   28 +-
 .../ref/sparc/linux/simple-atomic/config.ini  |   11 +-
 .../ref/sparc/linux/simple-atomic/simout      |    8 +-
 .../ref/sparc/linux/simple-atomic/stats.txt   |   24 +-
 .../ref/sparc/linux/simple-timing/config.ini  |   13 +-
 .../ref/sparc/linux/simple-timing/simout      |   12 +-
 .../ref/sparc/linux/simple-timing/stats.txt   |   26 +-
 .../tsunami-simple-atomic-dual/config.ini     |   25 +-
 .../linux/tsunami-simple-atomic-dual/simerr   |    4 -
 .../linux/tsunami-simple-atomic-dual/simout   |   12 +-
 .../tsunami-simple-atomic-dual/stats.txt      |   44 +-
 .../linux/tsunami-simple-atomic/config.ini    |   25 +-
 .../alpha/linux/tsunami-simple-atomic/simerr  |    4 -
 .../alpha/linux/tsunami-simple-atomic/simout  |   12 +-
 .../linux/tsunami-simple-atomic/stats.txt     |   26 +-
 .../tsunami-simple-timing-dual/config.ini     |   25 +-
 .../linux/tsunami-simple-timing-dual/simerr   |    4 -
 .../linux/tsunami-simple-timing-dual/simout   |   12 +-
 .../tsunami-simple-timing-dual/stats.txt      |   44 +-
 .../linux/tsunami-simple-timing/config.ini    |   25 +-
 .../alpha/linux/tsunami-simple-timing/simerr  |    4 -
 .../alpha/linux/tsunami-simple-timing/simout  |   12 +-
 .../linux/tsunami-simple-timing/stats.txt     |   26 +-
 .../linux/realview-simple-atomic/config.ini   |   15 +-
 .../arm/linux/realview-simple-atomic/simerr   |   44 +-
 .../arm/linux/realview-simple-atomic/simout   |   14 +-
 .../linux/realview-simple-atomic/stats.txt    |  399 ++++++
 .../arm/linux/realview-simple-atomic/status   |    2 +-
 .../linux/realview-simple-timing/config.ini   |   15 +-
 .../arm/linux/realview-simple-timing/simerr   |   50 +-
 .../arm/linux/realview-simple-timing/simout   |   12 +-
 .../linux/realview-simple-timing/stats.txt    |  483 +++++++
 .../ref/alpha/eio/simple-atomic/config.ini    |   13 +-
 .../ref/alpha/eio/simple-atomic/simout        |    8 +-
 .../ref/alpha/eio/simple-atomic/stats.txt     |   26 +-
 .../ref/alpha/eio/simple-timing/config.ini    |   13 +-
 .../ref/alpha/eio/simple-timing/simout        |    8 +-
 .../ref/alpha/eio/simple-timing/stats.txt     |   26 +-
 .../ref/alpha/eio/simple-atomic-mp/config.ini |   19 +-
 .../ref/alpha/eio/simple-atomic-mp/simerr     |    5 +-
 .../ref/alpha/eio/simple-atomic-mp/simout     |    8 +-
 .../ref/alpha/eio/simple-atomic-mp/stats.txt  |   80 +-
 .../ref/alpha/eio/simple-timing-mp/config.ini |   19 +-
 .../ref/alpha/eio/simple-timing-mp/simerr     |    4 +-
 .../ref/alpha/eio/simple-timing-mp/simout     |    8 +-
 .../ref/alpha/eio/simple-timing-mp/stats.txt  |   80 +-
 .../ref/sparc/linux/o3-timing-mp/config.ini   |   13 +-
 .../ref/sparc/linux/o3-timing-mp/simout       |    8 +-
 .../ref/sparc/linux/o3-timing-mp/stats.txt    |   92 +-
 .../sparc/linux/simple-atomic-mp/config.ini   |   13 +-
 .../ref/sparc/linux/simple-atomic-mp/simout   |   12 +-
 .../sparc/linux/simple-atomic-mp/stats.txt    |   80 +-
 .../sparc/linux/simple-timing-mp/config.ini   |   13 +-
 .../ref/sparc/linux/simple-timing-mp/simout   |   12 +-
 .../sparc/linux/simple-timing-mp/stats.txt    |   80 +-
 .../config.ini                                |   19 +-
 .../ruby.stats                                |   37 +-
 .../memtest-ruby-MESI_CMP_directory/simerr    |   89 +-
 .../memtest-ruby-MESI_CMP_directory/simout    |    9 +-
 .../memtest-ruby-MESI_CMP_directory/stats.txt |   34 +
 .../config.ini                                |   30 +-
 .../ruby.stats                                |  997 +++++++-------
 .../memtest-ruby-MOESI_CMP_directory/simerr   |  146 +-
 .../memtest-ruby-MOESI_CMP_directory/simout   |   10 +-
 .../stats.txt                                 |   42 +-
 .../memtest-ruby-MOESI_CMP_token/config.ini   |   30 +-
 .../memtest-ruby-MOESI_CMP_token/ruby.stats   | 1178 ++++++++---------
 .../linux/memtest-ruby-MOESI_CMP_token/simerr |  146 +-
 .../linux/memtest-ruby-MOESI_CMP_token/simout |   10 +-
 .../memtest-ruby-MOESI_CMP_token/stats.txt    |   40 +-
 .../memtest-ruby-MOESI_hammer/config.ini      |   31 +-
 .../memtest-ruby-MOESI_hammer/ruby.stats      |  999 +++++++-------
 .../linux/memtest-ruby-MOESI_hammer/simerr    |  146 +-
 .../linux/memtest-ruby-MOESI_hammer/simout    |   10 +-
 .../linux/memtest-ruby-MOESI_hammer/stats.txt |   40 +-
 .../ref/alpha/linux/memtest-ruby/config.ini   |   30 +-
 .../ref/alpha/linux/memtest-ruby/ruby.stats   |  459 ++++---
 .../ref/alpha/linux/memtest-ruby/simerr       |  146 +-
 .../ref/alpha/linux/memtest-ruby/simout       |   10 +-
 .../ref/alpha/linux/memtest-ruby/stats.txt    |   42 +-
 .../ref/alpha/linux/memtest/config.ini        |   11 +-
 .../50.memtest/ref/alpha/linux/memtest/simout |   10 +-
 .../ref/alpha/linux/memtest/stats.txt         |    6 +-
 .../config.ini                                |   12 +-
 .../ruby.stats                                |   28 +-
 .../rubytest-ruby-MESI_CMP_directory/simout   |    8 +-
 .../stats.txt                                 |    6 +-
 .../config.ini                                |   71 +-
 .../ruby.stats                                |   54 +-
 .../rubytest-ruby-MOESI_CMP_directory/simout  |    8 +-
 .../stats.txt                                 |    6 +-
 .../rubytest-ruby-MOESI_CMP_token/config.ini  |   71 +-
 .../rubytest-ruby-MOESI_CMP_token/ruby.stats  |  505 +++----
 .../rubytest-ruby-MOESI_CMP_token/simout      |   10 +-
 .../rubytest-ruby-MOESI_CMP_token/stats.txt   |   10 +-
 .../rubytest-ruby-MOESI_hammer/config.ini     |  102 +-
 .../rubytest-ruby-MOESI_hammer/ruby.stats     |  355 +++--
 .../linux/rubytest-ruby-MOESI_hammer/simout   |   10 +-
 .../rubytest-ruby-MOESI_hammer/stats.txt      |   10 +-
 .../ref/alpha/linux/rubytest-ruby/config.ini  |   81 +-
 .../ref/alpha/linux/rubytest-ruby/ruby.stats  |   48 +-
 .../ref/alpha/linux/rubytest-ruby/simout      |    8 +-
 .../ref/alpha/linux/rubytest-ruby/stats.txt   |    4 +-
 .../twosys-tsunami-simple-atomic/config.ini   |   50 +-
 .../linux/twosys-tsunami-simple-atomic/simerr |    4 -
 .../linux/twosys-tsunami-simple-atomic/simout |   14 +-
 .../twosys-tsunami-simple-atomic/stats.txt    |   86 +-
 228 files changed, 6374 insertions(+), 6831 deletions(-)

diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
index f00cd0f73..0558e754e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
@@ -201,7 +192,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
index 117dad2a4..98307cd85 100755
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:08
-M5 executing on SC2B0617
+M5 compiled Jan 24 2011 18:18:02
+M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
+M5 started Jan 24 2011 18:18:03
+M5 executing on zooks
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 311784102..be248d562 100644
--- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  43704                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205152                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-host_tick_rate                              151823848                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  36108                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 155860                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
+host_tick_rate                              125462283                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
@@ -267,8 +267,6 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                            44578                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                             7154                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
index 38874d4cc..da67d287f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -493,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
index fd3be687d..7b6a1125b 100755
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:02
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:24:57
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 127f68020..72be64488 100644
--- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  94328                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205636                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                              182630766                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  10121                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203516                       # Number of bytes of host memory used
+host_seconds                                     0.63                       # Real time elapsed on the host
+host_tick_rate                               19665204                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6386                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        12265                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      6403                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls              127                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  6321                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1185                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2050                       # Number of memory references committed
@@ -172,8 +169,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                13149                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1774                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 35292.253521                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622                       # average ReadReq mshr miss latency
@@ -273,8 +268,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          394                       #
 system.cpu.iew.memOrderViolationEvents             63                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          303                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            125                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    11489                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    6462                       # number of integer regfile writes
 system.cpu.ipc                               0.257230                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.257230                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            2      0.02%      0.02% # Type of FU issued
@@ -366,14 +359,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        13149                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.373520                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   9351                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              31807                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         8672                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             14983                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      10848                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9273                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
@@ -465,11 +450,7 @@ system.cpu.memDep0.conflictingLoads                34                       # Nu
 system.cpu.memDep0.conflictingStores               26                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2242                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1259                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                            24826                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4583                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               8                       # Number of times rename has blocked due to IQ full
@@ -482,14 +463,10 @@ system.cpu.rename.RENAME:RunCycles               2180                       # Nu
 system.cpu.rename.RENAME:SquashCycles             884                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            270                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              4300                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           17                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        15016                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          406                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           28                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                694                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        22718                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22732                       # The number of ROB writes
 system.cpu.timesIdled                             239                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 061058913..d867b793e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
index 962ffeead..0053084d5 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:39
-M5 executing on SC2B0617
+M5 compiled Feb 24 2010 23:12:40
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:01:37
+M5 executing on SC2B0619
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index b18d5e0d7..301281a5e 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1335558                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 196940                       # Number of bytes of host memory used
+host_inst_rate                                1228467                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 182556                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              634873618                       # Simulator tick rate (ticks/s)
+host_tick_rate                              587751371                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             6431                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       6431                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index c905c3ec3..2d9b77211 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -195,7 +186,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 1702ba0da..1eb50eecd 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:15
+Real time: Jan/13/2011 22:36:30
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
 
-Virtual_time_in_seconds: 0.5
-Virtual_time_in_minutes: 0.00833333
-Virtual_time_in_hours:   0.000138889
-Virtual_time_in_days:    5.78704e-06
+Virtual_time_in_seconds: 1.2
+Virtual_time_in_minutes: 0.02
+Virtual_time_in_hours:   0.000333333
+Virtual_time_in_days:    1.38889e-05
 
 Ruby_current_time: 275313
 Ruby_start_time: 0
 Ruby_cycles: 275313
 
-mbytes_resident: 37.0586
-mbytes_total: 210.465
-resident_ratio: 0.176117
+mbytes_resident: 22.0195
+mbytes_total: 156.82
+resident_ratio: 0.140462
 
 ruby_cycles_executed: [ 275314 ]
 
@@ -117,12 +117,12 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average:     0 | standa
 Resource Usage
 --------------
 page_size: 4096
-user_time: 0
+user_time: 1
 system_time: 0
-page_reclaims: 10709
+page_reclaims: 6300
 page_faults: 0
 swaps: 0
-block_inputs: 8
+block_inputs: 0
 block_outputs: 0
 
 Network Stats
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 9f667afd3..4d60ccfef 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:58
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:15
-M5 executing on SC2B0617
+M5 compiled Jan 13 2011 22:36:25
+M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
+M5 started Jan 13 2011 22:36:28
+M5 executing on scamorza.cs.wisc.edu
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 3903d25dc..be34966e1 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  28908                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215520                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
-host_tick_rate                                1241810                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   4080                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 160588                       # Number of bytes of host memory used
+host_seconds                                     1.57                       # Real time elapsed on the host
+host_tick_rate                                 175338                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000275                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           275313                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     275313                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index cb765942a..756bebd28 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -117,19 +108,32 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 buffer_size=0
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=3
@@ -137,7 +141,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=3
@@ -173,13 +177,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -189,18 +194,13 @@ randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -216,9 +216,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index f59e796d0..c3c1c36bf 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, unordered
 virtual_net_1: active, unordered
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:43:55
+Real time: Aug/05/2010 10:35:39
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.5
-Virtual_time_in_minutes: 0.00833333
-Virtual_time_in_hours:   0.000138889
-Virtual_time_in_days:    5.78704e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours:   0.000122222
+Virtual_time_in_days:    5.09259e-06
 
 Ruby_current_time: 223854
 Ruby_start_time: 0
 Ruby_cycles: 223854
 
-mbytes_resident: 37.1484
-mbytes_total: 210.605
-resident_ratio: 0.176426
+mbytes_resident: 34.9609
+mbytes_total: 34.9688
+resident_ratio: 1
 
 ruby_cycles_executed: [ 223855 ]
 
@@ -119,8 +119,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10697
-page_faults: 0
+page_reclaims: 7630
+page_faults: 2184
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.349752
   outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
 
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
 
  --- L1Cache ---
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index e3601434c..7e21d792f 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:43:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:54
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:34:54
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:35:39
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 3c3d87dff..add084384 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  25740                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215664                       # Number of bytes of host memory used
-host_seconds                                     0.25                       # Real time elapsed on the host
-host_tick_rate                                 899131                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  23717                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212528                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
+host_tick_rate                                 829037                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000224                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           223854                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     223854                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index d946bdc6f..d5555ef31 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -120,9 +111,9 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 N_tokens=2
 buffer_size=0
 dynamic_timeout_enabled=true
@@ -134,11 +125,24 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -146,7 +150,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -184,13 +188,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -200,18 +205,13 @@ randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 2fcd6b0f8..39236835d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:27:50
+Real time: Aug/05/2010 10:42:35
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.38
-Virtual_time_in_minutes: 0.00633333
-Virtual_time_in_hours:   0.000105556
-Virtual_time_in_days:    4.39815e-06
+Virtual_time_in_seconds: 0.27
+Virtual_time_in_minutes: 0.0045
+Virtual_time_in_hours:   7.5e-05
+Virtual_time_in_days:    3.125e-06
 
 Ruby_current_time: 243131
 Ruby_start_time: 0
 Ruby_cycles: 243131
 
-mbytes_resident: 37.0664
-mbytes_total: 210.492
-resident_ratio: 0.176131
+mbytes_resident: 34.8711
+mbytes_total: 34.8789
+resident_ratio: 1
 
 ruby_cycles_executed: [ 243132 ]
 
@@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average:     2 | standard deviation: 0 | 0 0 7084 ]
 miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average:    21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ]
-miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -89,13 +89,13 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 ave
 imcomplete_dir_Times: 1300
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average:     2 | standard deviation: 0 | 0 0 5768 ]
 miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average:    21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average:     2 | standard deviation: 0 | 0 0 660 ]
 miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average:    21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ]
-miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average:     2 | standard deviation: 0 | 0 0 656 ]
 miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average:    21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ]
-miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -127,10 +127,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10675
-page_faults: 0
+page_reclaims: 7568
+page_faults: 2181
 swaps: 0
-block_inputs: 16
+block_inputs: 0
 block_outputs: 0
 
 Network Stats
@@ -197,28 +197,28 @@ links_utilized_percent_switch_3: 0.209297
   outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 646
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 646
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
 
-  system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode:   646    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   646    100%
 
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 734
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 734
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   71.5259%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   28.4741%
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   71.5259%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   28.4741%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   734    100%
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   734    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -226,7 +226,7 @@ Load [1185 ] 1185
 Ifetch [6414 ] 6414
 Store [865 ] 865
 Atomic [0 ] 0
-L1_Replacement [1365 ] 1365
+L1_Replacement [1384 ] 1384
 Data_Shared [48 ] 48
 Data_Owner [0 ] 0
 Data_All_Tokens [1332 ] 1332
@@ -356,7 +356,7 @@ M_W  Load [102 ] 102
 M_W  Ifetch [2271 ] 2271
 M_W  Store [25 ] 25
 M_W  Atomic [0 ] 0
-M_W  L1_Replacement [8 ] 8
+M_W  L1_Replacement [21 ] 21
 M_W  Transient_GETX [0 ] 0
 M_W  Transient_Local_GETX [0 ] 0
 M_W  Transient_GETS [0 ] 0
@@ -373,7 +373,7 @@ MM_W  Load [21 ] 21
 MM_W  Ifetch [0 ] 0
 MM_W  Store [265 ] 265
 MM_W  Atomic [0 ] 0
-MM_W  L1_Replacement [3 ] 3
+MM_W  L1_Replacement [9 ] 9
 MM_W  Transient_GETX [0 ] 0
 MM_W  Transient_Local_GETX [0 ] 0
 MM_W  Transient_GETS [0 ] 0
@@ -743,18 +743,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_reads: 1301
   memory_writes: 241
   memory_refreshes: 507
-  memory_total_request_delays: 709
-  memory_delays_per_request: 0.459792
+  memory_total_request_delays: 714
+  memory_delays_per_request: 0.463035
   memory_delays_in_input_queue: 240
   memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 469
-  memory_stalls_for_bank_busy: 141
+  memory_delays_stalled_at_head_of_bank_queue: 474
+  memory_stalls_for_bank_busy: 148
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 33
-  memory_stalls_for_bus: 279
+  memory_stalls_for_arbitration: 30
+  memory_stalls_for_bus: 278
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 16
+  memory_stalls_for_read_write_turnaround: 18
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 80  17  45  54  54  148  45  17  20  22  33  34  54  53  44  33  40  22  21  28  28  42  73  34  32  25  34  75  101  159  19  56  
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 6145bf8f6..bfe534678 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:27:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:27:50
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:42:35
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 1da30c4d1..4330907be 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  49047                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215548                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-host_tick_rate                                1859468                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  45740                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 212336                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
+host_tick_rate                                1736538                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000243                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           243131                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     243131                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index b25662a67..a5602ce6c 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -79,7 +70,6 @@ type=Directory_Controller
 children=directory memBuffer probeFilter
 buffer_size=0
 directory=system.dir_cntrl0.directory
-full_bit_dir_enabled=false
 memBuffer=system.dir_cntrl0.memBuffer
 memory_controller_latency=2
 number_of_TBEs=256
@@ -128,18 +118,17 @@ start_index_bit=6
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L2cacheMemory
-L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
-L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 L2cacheMemory=system.l1_cntrl0.L2cacheMemory
 buffer_size=0
 cache_response_latency=10
 issue_latency=2
-l2_cache_hit_latency=10
 no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
@@ -151,37 +140,12 @@ replacement_policy=PSEUDO_LRU
 size=512
 start_index_bit=6
 
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
-
-[system.ruby]
-type=RubySystem
-children=cpu_ruby_ports network profiler tracer
-block_size_bytes=64
-clock=1
-mem_size=134217728
-network=system.ruby.network
-no_mem_vec=false
-profiler=system.ruby.profiler
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
+[system.l1_cntrl0.sequencer]
 type=RubySequencer
 children=dcache icache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
+dcache=system.l1_cntrl0.sequencer.dcache
 deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.icache
+icache=system.l1_cntrl0.sequencer.icache
 max_outstanding_requests=16
 physmem=system.physmem
 using_ruby_tester=false
@@ -189,7 +153,7 @@ version=0
 physMemPort=system.physmem.port[0]
 port=system.cpu.icache_port system.cpu.dcache_port
 
-[system.ruby.cpu_ruby_ports.dcache]
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -197,7 +161,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.ruby.cpu_ruby_ports.icache]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -205,6 +169,39 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+no_mem_vec=false
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
@@ -219,9 +216,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
 num_int_nodes=3
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 608b45c67..422144bd2 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:21
+Real time: Aug/05/2010 11:09:30
 
 Profiler Stats
 --------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.4
-Virtual_time_in_minutes: 0.00666667
-Virtual_time_in_hours:   0.000111111
-Virtual_time_in_days:    4.62963e-06
+Virtual_time_in_seconds: 0.61
+Virtual_time_in_minutes: 0.0101667
+Virtual_time_in_hours:   0.000169444
+Virtual_time_in_days:    7.06019e-06
 
-Ruby_current_time: 208400
+Ruby_current_time: 207970
 Ruby_start_time: 0
-Ruby_cycles: 208400
+Ruby_cycles: 207970
 
-mbytes_resident: 36.6992
-mbytes_total: 209.844
-resident_ratio: 0.174944
+mbytes_resident: 34.3633
+mbytes_total: 206.125
+resident_ratio: 0.166768
 
-ruby_cycles_executed: [ 208401 ]
+ruby_cycles_executed: [ 207971 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average:     2 | standard deviation: 0 | 0 0 7102 ]
-miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
-miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ]
+miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ]
+miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 imcomplete_dir_Times: 1158
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average:     2 | standard deviation: 0 | 0 0 5768 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ]
+miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average:     2 | standard deviation: 0 | 0 0 660 ]
-miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
-miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ]
+miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average:     2 | standard deviation: 0 | 0 0 674 ]
-miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
-miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ]
+miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -126,7 +126,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10651
+page_reclaims: 9927
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -144,9 +144,9 @@ total_msgs: 20718 total_bytes: 430512
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.111054
-  links_utilized_percent_switch_0_link_0: 0.0694218 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.152687 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.111284
+  links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.111054
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.157929
-  links_utilized_percent_switch_1_link_0: 0.0381718 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.277687 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.158256
+  links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1
@@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.157929
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.215187
-  links_utilized_percent_switch_2_link_0: 0.277687 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.152687 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.215632
+  links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
@@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215187
   outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.icache
-  system.ruby.cpu_ruby_ports.icache_total_misses: 646
-  system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646
-  system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 646
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 646
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   646    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   646    100%
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 716
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 716
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   73.324%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   26.676%
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   73.324%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   26.676%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   716    100%
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   716    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 1362
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362
+  system.l1_cntrl0.L2cacheMemory_total_misses: 1159
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   38.5463%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   14.0235%
-  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   47.4302%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   36.2381%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   13.6324%
+  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   50.1294%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   1362    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   1159    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [1193 ] 1193
-Ifetch [6425 ] 6425
-Store [892 ] 892
+Load [1201 ] 1201
+Ifetch [6436 ] 6436
+Store [919 ] 919
 L2_Replacement [1143 ] 1143
 L1_to_L2 [1354 ] 1354
 Trigger_L2_to_L1D [138 ] 138
@@ -231,7 +231,6 @@ Other_GETX [0 ] 0
 Other_GETS [0 ] 0
 Merged_GETS [0 ] 0
 Other_GETS_No_Mig [0 ] 0
-NC_DMA_GETS [0 ] 0
 Invalidate [0 ] 0
 Ack [0 ] 0
 Shared_Ack [0 ] 0
@@ -254,7 +253,6 @@ I  Trigger_L2_to_L1I [0 ] 0
 I  Other_GETX [0 ] 0
 I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
-I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
 
 S  Load [0 ] 0
@@ -267,7 +265,6 @@ S  Trigger_L2_to_L1I [0 ] 0
 S  Other_GETX [0 ] 0
 S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
-S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
 
 O  Load [0 ] 0
@@ -281,7 +278,6 @@ O  Other_GETX [0 ] 0
 O  Other_GETS [0 ] 0
 O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
-O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
 
 M  Load [368 ] 368
@@ -295,7 +291,6 @@ M  Other_GETX [0 ] 0
 M  Other_GETS [0 ] 0
 M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
-M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
 
 MM  Load [397 ] 397
@@ -309,7 +304,6 @@ MM  Other_GETX [0 ] 0
 MM  Other_GETS [0 ] 0
 MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
-MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
 
 IM  Load [0 ] 0
@@ -320,7 +314,6 @@ IM  L1_to_L2 [0 ] 0
 IM  Other_GETX [0 ] 0
 IM  Other_GETS [0 ] 0
 IM  Other_GETS_No_Mig [0 ] 0
-IM  NC_DMA_GETS [0 ] 0
 IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
@@ -334,11 +327,9 @@ SM  L1_to_L2 [0 ] 0
 SM  Other_GETX [0 ] 0
 SM  Other_GETS [0 ] 0
 SM  Other_GETS_No_Mig [0 ] 0
-SM  NC_DMA_GETS [0 ] 0
 SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -349,7 +340,6 @@ OM  Other_GETX [0 ] 0
 OM  Other_GETS [0 ] 0
 OM  Merged_GETS [0 ] 0
 OM  Other_GETS_No_Mig [0 ] 0
-OM  NC_DMA_GETS [0 ] 0
 OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
@@ -387,7 +377,6 @@ IS  L1_to_L2 [0 ] 0
 IS  Other_GETX [0 ] 0
 IS  Other_GETS [0 ] 0
 IS  Other_GETS_No_Mig [0 ] 0
-IS  NC_DMA_GETS [0 ] 0
 IS  Invalidate [0 ] 0
 IS  Ack [0 ] 0
 IS  Shared_Ack [0 ] 0
@@ -414,20 +403,18 @@ OI  Other_GETX [0 ] 0
 OI  Other_GETS [0 ] 0
 OI  Merged_GETS [0 ] 0
 OI  Other_GETS_No_Mig [0 ] 0
-OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
 
-MI  Load [8 ] 8
-MI  Ifetch [11 ] 11
-MI  Store [27 ] 27
+MI  Load [16 ] 16
+MI  Ifetch [22 ] 22
+MI  Store [54 ] 54
 MI  L2_Replacement [0 ] 0
 MI  L1_to_L2 [0 ] 0
 MI  Other_GETX [0 ] 0
 MI  Other_GETS [0 ] 0
 MI  Merged_GETS [0 ] 0
 MI  Other_GETS_No_Mig [0 ] 0
-MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
 MI  Writeback_Ack [1143 ] 1143
 
@@ -439,7 +426,6 @@ II  L1_to_L2 [0 ] 0
 II  Other_GETX [0 ] 0
 II  Other_GETS [0 ] 0
 II  Other_GETS_No_Mig [0 ] 0
-II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
@@ -454,7 +440,6 @@ IT  Other_GETX [0 ] 0
 IT  Other_GETS [0 ] 0
 IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
-IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
 
 ST  Load [0 ] 0
@@ -467,7 +452,6 @@ ST  Other_GETX [0 ] 0
 ST  Other_GETS [0 ] 0
 ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
-ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
 
 OT  Load [0 ] 0
@@ -480,7 +464,6 @@ OT  Other_GETX [0 ] 0
 OT  Other_GETS [0 ] 0
 OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
-OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
 
 MT  Load [0 ] 0
@@ -493,7 +476,6 @@ MT  Other_GETX [0 ] 0
 MT  Other_GETS [0 ] 0
 MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
-MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
 
 MMT  Load [0 ] 0
@@ -506,7 +488,6 @@ MMT  Other_GETX [0 ] 0
 MMT  Other_GETS [0 ] 0
 MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
-MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
@@ -521,19 +502,19 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 1379
   memory_reads: 1159
   memory_writes: 220
-  memory_refreshes: 435
-  memory_total_request_delays: 495
-  memory_delays_per_request: 0.358956
-  memory_delays_in_input_queue: 3
+  memory_refreshes: 434
+  memory_total_request_delays: 471
+  memory_delays_per_request: 0.341552
+  memory_delays_in_input_queue: 15
   memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 492
-  memory_stalls_for_bank_busy: 124
+  memory_delays_stalled_at_head_of_bank_queue: 456
+  memory_stalls_for_bank_busy: 86
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 23
+  memory_stalls_for_arbitration: 30
   memory_stalls_for_bus: 78
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 267
+  memory_stalls_for_read_write_turnaround: 262
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 75  17  45  40  54  101  33  16  20  22  32  34  53  50  39  31  39  22  21  27  28  38  81  22  31  23  32  72  89  126  14  52  
 
@@ -644,8 +625,6 @@ NO_B_X  PUT [0 ] 0
 NO_B_X  UnblockS [0 ] 0
 NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
-NO_B_X  DMA_READ [0 ] 0
-NO_B_X  DMA_WRITE [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -669,7 +648,6 @@ O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
 O_B  UnblockS [0 ] 0
-O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index b5f7a90c7..01467c4b7 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:21
+M5 compiled Aug  5 2010 11:09:13
+M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates
+M5 started Aug  5 2010 11:09:30
 M5 executing on SC2B0617
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 208400 because target called exit()
+Exiting @ tick 207970 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 1397975f6..8112f9791 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  47973                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214884                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-host_tick_rate                                1559052                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  31390                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211076                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                                1018487                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000208                       # Number of seconds simulated
-sim_ticks                                      208400                       # Number of ticks simulated
+sim_ticks                                      207970                       # Number of ticks simulated
 system.cpu.dtb.data_accesses                     2060                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                         2050                       # DTB hits
@@ -42,25 +42,9 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                           208400                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     208400                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numCycles                           207970                       # number of cpu cycles simulated
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index af87896a7..3438ec60f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -74,59 +65,6 @@ simpoint=0
 system=system
 uid=100
 
-[system.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.dir_cntrl0.directory
-directory_latency=12
-memBuffer=system.dir_cntrl0.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=6
-size=134217728
-use_map=false
-version=0
-
-[system.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
-[system.l1_cntrl0]
-type=L1Cache_Controller
-buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
-transitions_per_cycle=32
-version=0
-
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -135,48 +73,34 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
-no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=false
+adaptive_routing=true
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -187,7 +111,6 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -195,20 +118,93 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.l1_cntrl0
+ext_node=system.ruby.network.topology.ext_links0.ext_node
 int_node=0
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.dir_cntrl0
+ext_node=system.ruby.network.topology.ext_links1.ext_node
 int_node=1
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index aaf8192d1..d9b6ae533 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -18,9 +18,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: active, ordered
+virtual_net_3: inactive
 virtual_net_4: active, ordered
-virtual_net_5: inactive
+virtual_net_5: active, ordered
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:39
+Real time: Jan/28/2010 10:15:29
 
 Profiler Stats
 --------------
@@ -43,20 +43,31 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.37
-Virtual_time_in_minutes: 0.00616667
-Virtual_time_in_hours:   0.000102778
-Virtual_time_in_days:    4.28241e-06
+Virtual_time_in_seconds: 0.5
+Virtual_time_in_minutes: 0.00833333
+Virtual_time_in_hours:   0.000138889
+Virtual_time_in_days:    5.78704e-06
 
 Ruby_current_time: 342698
 Ruby_start_time: 0
 Ruby_cycles: 342698
 
-mbytes_resident: 36.6797
-mbytes_total: 209.906
-resident_ratio: 0.17478
+mbytes_resident: 34.2148
+mbytes_total: 34.2227
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 342699 [ 342699 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
 
-ruby_cycles_executed: [ 342699 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -70,27 +81,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 6734 average:     3 | standard deviation: 0 | 0 0 0 6734 ]
-miss_latency_Directory: [binsize: 2 max: 377 count: 1730 average: 181.521 | standard deviation: 26.4115 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 0
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-imcomplete_dir_Times: 1729
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 5684 average:     3 | standard deviation: 0 | 0 0 0 5684 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 730 average: 181.192 | standard deviation: 25.9199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 458 average:     3 | standard deviation: 0 | 0 0 0 458 ]
-miss_latency_LD_Directory: [binsize: 2 max: 375 count: 727 average: 178.4 | standard deviation: 21.0913 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 592 average:     3 | standard deviation: 0 | 0 0 0 592 ]
-miss_latency_ST_Directory: [binsize: 2 max: 377 count: 273 average: 190.714 | standard deviation: 36.5384 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,8 +115,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10613
-page_faults: 0
+page_reclaims: 7357
+page_faults: 2195
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -131,22 +124,16 @@ block_outputs: 0
 Network Stats
 -------------
 
-total_msg_count_Control: 5190 41520
-total_msg_count_Data: 5178 372816
-total_msg_count_Response_Data: 5190 373680
-total_msg_count_Writeback_Control: 5178 41424
-total_msgs: 20736 total_bytes: 829440
-
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.157486
   links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -154,10 +141,10 @@ links_utilized_percent_switch_1: 0.157661
   links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -165,64 +152,66 @@ links_utilized_percent_switch_2: 0.252117
   links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 0 0 0 1730 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 0 1726 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 1730
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1730
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   42.0231%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   15.7803%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   42.1965%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   42.0231%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   15.7803%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   42.1965%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1730    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   1730    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
 
- --- L1Cache ---
+ --- L1Cache 0 ---
  - Event Counts -
-Load [1185 ] 1185
-Ifetch [6414 ] 6414
-Store [865 ] 865
-Data [1730 ] 1730
-Fwd_GETX [0 ] 0
-Inv [0 ] 0
-Replacement [1726 ] 1726
-Writeback_Ack [1726 ] 1726
-Writeback_Nack [0 ] 0
+Load  1185
+Ifetch  6414
+Store  865
+Data  1730
+Fwd_GETX  0
+Inv  0
+Replacement  1726
+Writeback_Ack  1726
+Writeback_Nack  0
 
  - Transitions -
-I  Load [727 ] 727
-I  Ifetch [730 ] 730
-I  Store [273 ] 273
-I  Inv [0 ] 0
-I  Replacement [0 ] 0
+I  Load  727
+I  Ifetch  730
+I  Store  273
+I  Inv  0 <-- 
+I  Replacement  0 <-- 
 
-II  Writeback_Nack [0 ] 0
+II  Writeback_Nack  0 <-- 
 
-M  Load [458 ] 458
-M  Ifetch [5684 ] 5684
-M  Store [592 ] 592
-M  Fwd_GETX [0 ] 0
-M  Inv [0 ] 0
-M  Replacement [1726 ] 1726
+M  Load  458
+M  Ifetch  5684
+M  Store  592
+M  Fwd_GETX  0 <-- 
+M  Inv  0 <-- 
+M  Replacement  1726
 
-MI  Fwd_GETX [0 ] 0
-MI  Inv [0 ] 0
-MI  Writeback_Ack [1726 ] 1726
-MI  Writeback_Nack [0 ] 0
+MI  Fwd_GETX  0 <-- 
+MI  Inv  0 <-- 
+MI  Writeback_Ack  1726
+MI  Writeback_Nack  0 <-- 
 
-MII  Fwd_GETX [0 ] 0
+MII  Fwd_GETX  0 <-- 
 
-IS  Data [1457 ] 1457
+IS  Data  1457
 
-IM  Data [273 ] 273
+IM  Data  273
 
-Memory controller: system.dir_cntrl0.memBuffer:
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_total_requests: 3456
   memory_reads: 1730
   memory_writes: 1726
@@ -242,69 +231,70 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 162  36  92  110  106  362  98  36  32  34  83  92  110  104  84  86  83  53  50  58  64  124  212  72  66  50  122  190  220  325  42  98  
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
-GETX [1730 ] 1730
-GETS [0 ] 0
-PUTX [1726 ] 1726
-PUTX_NotOwner [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [1730 ] 1730
-Memory_Ack [1726 ] 1726
+GETX  1730
+GETS  0
+PUTX  1726
+PUTX_NotOwner  0
+DMA_READ  0
+DMA_WRITE  0
+Memory_Data  1730
+Memory_Ack  1726
 
  - Transitions -
-I  GETX [1730 ] 1730
-I  PUTX_NotOwner [0 ] 0
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  PUTX [1726 ] 1726
-M  PUTX_NotOwner [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-M_DRD  GETX [0 ] 0
-M_DRD  PUTX [0 ] 0
-
-M_DWR  GETX [0 ] 0
-M_DWR  PUTX [0 ] 0
-
-M_DWRI  GETX [0 ] 0
-M_DWRI  Memory_Ack [0 ] 0
-
-M_DRDI  GETX [0 ] 0
-M_DRDI  Memory_Ack [0 ] 0
-
-IM  GETX [0 ] 0
-IM  GETS [0 ] 0
-IM  PUTX [0 ] 0
-IM  PUTX_NotOwner [0 ] 0
-IM  DMA_READ [0 ] 0
-IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [1730 ] 1730
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTX_NotOwner [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [1726 ] 1726
-
-ID  GETX [0 ] 0
-ID  GETS [0 ] 0
-ID  PUTX [0 ] 0
-ID  PUTX_NotOwner [0 ] 0
-ID  DMA_READ [0 ] 0
-ID  DMA_WRITE [0 ] 0
-ID  Memory_Data [0 ] 0
-
-ID_W  GETX [0 ] 0
-ID_W  GETS [0 ] 0
-ID_W  PUTX [0 ] 0
-ID_W  PUTX_NotOwner [0 ] 0
-ID_W  DMA_READ [0 ] 0
-ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+I  GETX  1730
+I  PUTX_NotOwner  0 <-- 
+I  DMA_READ  0 <-- 
+I  DMA_WRITE  0 <-- 
+
+M  GETX  0 <-- 
+M  PUTX  1726
+M  PUTX_NotOwner  0 <-- 
+M  DMA_READ  0 <-- 
+M  DMA_WRITE  0 <-- 
+
+M_DRD  GETX  0 <-- 
+M_DRD  PUTX  0 <-- 
+
+M_DWR  GETX  0 <-- 
+M_DWR  PUTX  0 <-- 
+
+M_DWRI  GETX  0 <-- 
+M_DWRI  Memory_Ack  0 <-- 
+
+M_DRDI  GETX  0 <-- 
+M_DRDI  Memory_Ack  0 <-- 
+
+IM  GETX  0 <-- 
+IM  GETS  0 <-- 
+IM  PUTX  0 <-- 
+IM  PUTX_NotOwner  0 <-- 
+IM  DMA_READ  0 <-- 
+IM  DMA_WRITE  0 <-- 
+IM  Memory_Data  1730
+
+MI  GETX  0 <-- 
+MI  GETS  0 <-- 
+MI  PUTX  0 <-- 
+MI  PUTX_NotOwner  0 <-- 
+MI  DMA_READ  0 <-- 
+MI  DMA_WRITE  0 <-- 
+MI  Memory_Ack  1726
+
+ID  GETX  0 <-- 
+ID  GETS  0 <-- 
+ID  PUTX  0 <-- 
+ID  PUTX_NotOwner  0 <-- 
+ID  DMA_READ  0 <-- 
+ID  DMA_WRITE  0 <-- 
+ID  Memory_Data  0 <-- 
+
+ID_W  GETX  0 <-- 
+ID_W  GETS  0 <-- 
+ID_W  PUTX  0 <-- 
+ID_W  PUTX_NotOwner  0 <-- 
+ID_W  DMA_READ  0 <-- 
+ID_W  DMA_WRITE  0 <-- 
+ID_W  Memory_Ack  0 <-- 
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 0e29e87af..b8009485a 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:38
-M5 executing on SC2B0617
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 10:15:28
+M5 executing on svvint07
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 1cd8c8088..d59a173b9 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  54314                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214948                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                2902474                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  19405                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215700                       # Number of bytes of host memory used
+host_seconds                                     0.33                       # Real time elapsed on the host
+host_tick_rate                                1038428                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000343                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           342698                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     342698                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index 6422e99b3..17f796bc5 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
index 277e384f7..2df06d2e2 100755
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:57
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:59:22
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 0a93b2c31..0a6e1d861 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 560476                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204672                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2823041396                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 332796                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204128                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1691799077                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        6404                       # Number of instructions simulated
 sim_seconds                                  0.000033                       # Number of seconds simulated
@@ -227,24 +227,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            66014                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      66014                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
-system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             6404                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
-system.cpu.num_int_insts                         6331                       # number of integer instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1192                       # Number of load instructions
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_store_insts                        868                       # Number of store instructions
+system.cpu.num_refs                              2060                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 2b9fce4f2..2ddfc3365 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -493,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
index e774ba11e..fe2af5e09 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:36
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:48:46
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 311a86bd4..2363f1511 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  78818                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204536                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-host_tick_rate                              238897798                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  61982                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202420                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+host_tick_rate                              188319059                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2387                       # Number of instructions simulated
 sim_seconds                                  0.000007                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total         6328                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      2576                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      6                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls               71                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  2367                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                       415                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                        709                       # Number of memory references committed
@@ -172,7 +169,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                 6701                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses                782                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36074.786325                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403                       # average ReadReq mshr miss latency
@@ -272,8 +268,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          141                       #
 system.cpu.iew.memOrderViolationEvents             13                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          109                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             55                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                     4283                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2601                       # number of integer regfile writes
 system.cpu.ipc                               0.163482                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.163482                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -365,14 +359,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total         6701                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.248682                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   3659                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              14008                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         3396                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes              5997                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       4276                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      3631                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
@@ -463,11 +449,7 @@ system.cpu.memDep0.conflictingLoads                16                       # Nu
 system.cpu.memDep0.conflictingStores               16                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                  793                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                 435                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.numCycles                            14601                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles               63                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           1768                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               3                       # Number of times rename has blocked due to IQ full
@@ -480,14 +462,10 @@ system.cpu.rename.RENAME:RunCycles                901                       # Nu
 system.cpu.rename.RENAME:SquashCycles             373                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles             15                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              1713                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           12                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups         5502                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          146                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            8                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                 78                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            6                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        10620                       # The number of ROB reads
-system.cpu.rob.rob_writes                        9524                       # The number of ROB writes
 system.cpu.timesIdled                             152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 6bac111b6..ac9cc91a1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -66,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
index 7d6e98afc..532375cf9 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,10 +7,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:47
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 21:30:55
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 21:32:40
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index 3874b2441..d0028e484 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 849934                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 196124                       # Number of bytes of host memory used
+host_inst_rate                                 759729                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 228516                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              396667686                       # Simulator tick rate (ticks/s)
+host_tick_rate                              362937063                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             2596                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       2596                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index b7bfb0aae..a4ed53868 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -195,7 +186,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 027313a2c..4efa8de79 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:15
+Real time: Jan/13/2011 22:36:30
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
 
-Virtual_time_in_seconds: 0.37
-Virtual_time_in_minutes: 0.00616667
-Virtual_time_in_hours:   0.000102778
-Virtual_time_in_days:    4.28241e-06
+Virtual_time_in_seconds: 0.79
+Virtual_time_in_minutes: 0.0131667
+Virtual_time_in_hours:   0.000219444
+Virtual_time_in_days:    9.14352e-06
 
 Ruby_current_time: 103637
 Ruby_start_time: 0
 Ruby_cycles: 103637
 
-mbytes_resident: 35.7305
-mbytes_total: 209.473
-resident_ratio: 0.170611
+mbytes_resident: 20.9219
+mbytes_total: 156.062
+resident_ratio: 0.134111
 
 ruby_cycles_executed: [ 103638 ]
 
@@ -119,7 +119,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10361
+page_reclaims: 6028
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index be2d10449..5c8b35b72 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:58
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:15
-M5 executing on SC2B0617
+M5 compiled Jan 13 2011 22:36:25
+M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
+M5 started Jan 13 2011 22:36:28
+M5 executing on scamorza.cs.wisc.edu
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 25c8ba580..5b40ee1fb 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  29262                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214504                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                1174597                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   2534                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 159812                       # Number of bytes of host memory used
+host_seconds                                     1.02                       # Real time elapsed on the host
+host_tick_rate                                 101843                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000104                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           103637                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     103637                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index dae855509..59f975e1e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -117,19 +108,32 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 buffer_size=0
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=3
@@ -137,7 +141,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=3
@@ -173,13 +177,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -189,18 +194,13 @@ randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -216,9 +216,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 494e34e3f..86aa94fb6 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, unordered
 virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:43:54
+Real time: Aug/05/2010 10:37:10
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.34
-Virtual_time_in_minutes: 0.00566667
-Virtual_time_in_hours:   9.44444e-05
-Virtual_time_in_days:    3.93519e-06
+Virtual_time_in_seconds: 0.41
+Virtual_time_in_minutes: 0.00683333
+Virtual_time_in_hours:   0.000113889
+Virtual_time_in_days:    4.74537e-06
 
 Ruby_current_time: 85988
 Ruby_start_time: 0
 Ruby_cycles: 85988
 
-mbytes_resident: 35.8281
-mbytes_total: 209.613
-resident_ratio: 0.170962
+mbytes_resident: 33.6484
+mbytes_total: 33.6562
+resident_ratio: 1
 
 ruby_cycles_executed: [ 85989 ]
 
@@ -119,8 +119,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10369
-page_faults: 0
+page_reclaims: 7386
+page_faults: 2090
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645
   outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
 
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
 
  --- L1Cache ---
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index b4ee3d335..c8e6b0646 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:43:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:54
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:34:54
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:37:10
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 9e38951ad..bc9801bf7 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  22051                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214648                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-host_tick_rate                                 734783                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  19822                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211548                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                                 661411                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000086                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            85988                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      85988                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 537819260..1971d2a44 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -120,9 +111,9 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 N_tokens=2
 buffer_size=0
 dynamic_timeout_enabled=true
@@ -134,11 +125,24 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -146,7 +150,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -184,13 +188,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -200,18 +205,13 @@ randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -227,9 +227,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 9d8b157dc..dbdcc6601 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:27:50
+Real time: Aug/05/2010 10:43:25
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.33
-Virtual_time_in_minutes: 0.0055
-Virtual_time_in_hours:   9.16667e-05
-Virtual_time_in_days:    3.81944e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours:   6.94444e-05
+Virtual_time_in_days:    2.89352e-06
 
 Ruby_current_time: 92099
 Ruby_start_time: 0
 Ruby_cycles: 92099
 
-mbytes_resident: 35.7734
-mbytes_total: 209.453
-resident_ratio: 0.170832
+mbytes_resident: 33.5859
+mbytes_total: 33.5938
+resident_ratio: 1
 
 ruby_cycles_executed: [ 92100 ]
 
@@ -127,10 +127,10 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10358
-page_faults: 0
+page_reclaims: 7341
+page_faults: 2084
 swaps: 0
-block_inputs: 16
+block_inputs: 0
 block_outputs: 0
 
 Network Stats
@@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739
   outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 270
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 270
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
 
-  system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode:   270    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   270    100%
 
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 243
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 243
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   74.8971%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   25.1029%
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   74.8971%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   25.1029%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   243    100%
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   243    100%
 
  --- L1Cache ---
  - Event Counts -
@@ -222,7 +222,7 @@ Load [415 ] 415
 Ifetch [2585 ] 2585
 Store [294 ] 294
 Atomic [0 ] 0
-L1_Replacement [503 ] 503
+L1_Replacement [506 ] 506
 Data_Shared [18 ] 18
 Data_Owner [0 ] 0
 Data_All_Tokens [495 ] 495
@@ -352,7 +352,7 @@ M_W  Load [47 ] 47
 M_W  Ifetch [1038 ] 1038
 M_W  Store [6 ] 6
 M_W  Atomic [0 ] 0
-M_W  L1_Replacement [1 ] 1
+M_W  L1_Replacement [4 ] 4
 M_W  Transient_GETX [0 ] 0
 M_W  Transient_Local_GETX [0 ] 0
 M_W  Transient_GETS [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index aa7eff126..9cf458143 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:27:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:27:50
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:43:25
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e986a3c8f..e8b218502 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  45706                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 214484                       # Number of bytes of host memory used
+host_inst_rate                                  42948                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211392                       # Number of bytes of host memory used
 host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                                1628169                       # Simulator tick rate (ticks/s)
+host_tick_rate                                1534907                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000092                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            92099                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      92099                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 08f882272..4d36728d7 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.l1_cntrl0.sequencer.port[1]
+icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -79,7 +70,6 @@ type=Directory_Controller
 children=directory memBuffer probeFilter
 buffer_size=0
 directory=system.dir_cntrl0.directory
-full_bit_dir_enabled=false
 memBuffer=system.dir_cntrl0.memBuffer
 memory_controller_latency=2
 number_of_TBEs=256
@@ -128,18 +118,17 @@ start_index_bit=6
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L2cacheMemory
-L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
-L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 L2cacheMemory=system.l1_cntrl0.L2cacheMemory
 buffer_size=0
 cache_response_latency=10
 issue_latency=2
-l2_cache_hit_latency=10
 no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
@@ -151,37 +140,12 @@ replacement_policy=PSEUDO_LRU
 size=512
 start_index_bit=6
 
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
-
-[system.ruby]
-type=RubySystem
-children=cpu_ruby_ports network profiler tracer
-block_size_bytes=64
-clock=1
-mem_size=134217728
-network=system.ruby.network
-no_mem_vec=false
-profiler=system.ruby.profiler
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
+[system.l1_cntrl0.sequencer]
 type=RubySequencer
 children=dcache icache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
+dcache=system.l1_cntrl0.sequencer.dcache
 deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.icache
+icache=system.l1_cntrl0.sequencer.icache
 max_outstanding_requests=16
 physmem=system.physmem
 using_ruby_tester=false
@@ -189,7 +153,7 @@ version=0
 physMemPort=system.physmem.port[0]
 port=system.cpu.icache_port system.cpu.dcache_port
 
-[system.ruby.cpu_ruby_ports.dcache]
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -197,7 +161,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.ruby.cpu_ruby_ports.icache]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -205,6 +169,39 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+no_mem_vec=false
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
@@ -219,9 +216,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
 num_int_nodes=3
 print_config=false
 
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 7f9bbf1b9..6e53a933a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:21
+Real time: Aug/05/2010 14:44:19
 
 Profiler Stats
 --------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.31
-Virtual_time_in_minutes: 0.00516667
-Virtual_time_in_hours:   8.61111e-05
-Virtual_time_in_days:    3.58796e-06
+Virtual_time_in_seconds: 0.21
+Virtual_time_in_minutes: 0.0035
+Virtual_time_in_hours:   5.83333e-05
+Virtual_time_in_days:    2.43056e-06
 
-Ruby_current_time: 78448
+Ruby_current_time: 78408
 Ruby_start_time: 0
-Ruby_cycles: 78448
+Ruby_cycles: 78408
 
-mbytes_resident: 35.418
-mbytes_total: 208.91
-resident_ratio: 0.169593
+mbytes_resident: 33.3242
+mbytes_total: 33.332
+resident_ratio: 1
 
-ruby_cycles_executed: [ 78449 ]
+ruby_cycles_executed: [ 78409 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
-miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
+miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average:     2 | standard deviation: 0 | 0 0 2784 ]
-miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
-miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
+miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 imcomplete_dir_Times: 440
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average:     2 | standard deviation: 0 | 0 0 2315 ]
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
-miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ]
 miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average:     2 | standard deviation: 0 | 0 0 233 ]
-miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
-miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
+miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average:     2 | standard deviation: 0 | 0 0 236 ]
-miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average:    13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
-miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average:    12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
+miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -126,8 +126,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10333
-page_faults: 0
+page_reclaims: 7298
+page_faults: 2071
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.110822
-  links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.110878
+  links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110822
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.158983
-  links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.159064
+  links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
@@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.158983
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.215844
-  links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.215954
+  links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1
 
   outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
@@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215844
   outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.icache
-  system.ruby.cpu_ruby_ports.icache_total_misses: 270
-  system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
-  system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 270
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 270
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   270    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   270    100%
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 240
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 240
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   75.8333%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   24.1667%
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   75.8333%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   24.1667%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   240    100%
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   240    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 510
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
+  system.l1_cntrl0.L2cacheMemory_total_misses: 441
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   35.6863%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   11.3725%
-  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   52.9412%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   33.1066%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   10.6576%
+  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   56.2358%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   510    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   441    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [422 ] 422
-Ifetch [2591 ] 2591
-Store [298 ] 298
+Load [428 ] 428
+Ifetch [2597 ] 2597
+Store [302 ] 302
 L2_Replacement [425 ] 425
 L1_to_L2 [502 ] 502
 Trigger_L2_to_L1D [47 ] 47
@@ -231,7 +231,6 @@ Other_GETX [0 ] 0
 Other_GETS [0 ] 0
 Merged_GETS [0 ] 0
 Other_GETS_No_Mig [0 ] 0
-NC_DMA_GETS [0 ] 0
 Invalidate [0 ] 0
 Ack [0 ] 0
 Shared_Ack [0 ] 0
@@ -254,7 +253,6 @@ I  Trigger_L2_to_L1I [0 ] 0
 I  Other_GETX [0 ] 0
 I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
-I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
 
 S  Load [0 ] 0
@@ -267,7 +265,6 @@ S  Trigger_L2_to_L1I [0 ] 0
 S  Other_GETX [0 ] 0
 S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
-S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
 
 O  Load [0 ] 0
@@ -281,7 +278,6 @@ O  Other_GETX [0 ] 0
 O  Other_GETS [0 ] 0
 O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
-O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
 
 M  Load [131 ] 131
@@ -295,7 +291,6 @@ M  Other_GETX [0 ] 0
 M  Other_GETS [0 ] 0
 M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
-M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
 
 MM  Load [138 ] 138
@@ -309,7 +304,6 @@ MM  Other_GETX [0 ] 0
 MM  Other_GETS [0 ] 0
 MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
-MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
 
 IM  Load [0 ] 0
@@ -320,7 +314,6 @@ IM  L1_to_L2 [0 ] 0
 IM  Other_GETX [0 ] 0
 IM  Other_GETS [0 ] 0
 IM  Other_GETS_No_Mig [0 ] 0
-IM  NC_DMA_GETS [0 ] 0
 IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
@@ -334,11 +327,9 @@ SM  L1_to_L2 [0 ] 0
 SM  Other_GETX [0 ] 0
 SM  Other_GETS [0 ] 0
 SM  Other_GETS_No_Mig [0 ] 0
-SM  NC_DMA_GETS [0 ] 0
 SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -349,7 +340,6 @@ OM  Other_GETX [0 ] 0
 OM  Other_GETS [0 ] 0
 OM  Merged_GETS [0 ] 0
 OM  Other_GETS_No_Mig [0 ] 0
-OM  NC_DMA_GETS [0 ] 0
 OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
@@ -387,7 +377,6 @@ IS  L1_to_L2 [0 ] 0
 IS  Other_GETX [0 ] 0
 IS  Other_GETS [0 ] 0
 IS  Other_GETS_No_Mig [0 ] 0
-IS  NC_DMA_GETS [0 ] 0
 IS  Invalidate [0 ] 0
 IS  Ack [0 ] 0
 IS  Shared_Ack [0 ] 0
@@ -414,20 +403,18 @@ OI  Other_GETX [0 ] 0
 OI  Other_GETS [0 ] 0
 OI  Merged_GETS [0 ] 0
 OI  Other_GETS_No_Mig [0 ] 0
-OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
 
-MI  Load [7 ] 7
-MI  Ifetch [6 ] 6
-MI  Store [4 ] 4
+MI  Load [13 ] 13
+MI  Ifetch [12 ] 12
+MI  Store [8 ] 8
 MI  L2_Replacement [0 ] 0
 MI  L1_to_L2 [0 ] 0
 MI  Other_GETX [0 ] 0
 MI  Other_GETS [0 ] 0
 MI  Merged_GETS [0 ] 0
 MI  Other_GETS_No_Mig [0 ] 0
-MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
 MI  Writeback_Ack [425 ] 425
 
@@ -439,7 +426,6 @@ II  L1_to_L2 [0 ] 0
 II  Other_GETX [0 ] 0
 II  Other_GETS [0 ] 0
 II  Other_GETS_No_Mig [0 ] 0
-II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
@@ -454,7 +440,6 @@ IT  Other_GETX [0 ] 0
 IT  Other_GETS [0 ] 0
 IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
-IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
 
 ST  Load [0 ] 0
@@ -467,7 +452,6 @@ ST  Other_GETX [0 ] 0
 ST  Other_GETS [0 ] 0
 ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
-ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
 
 OT  Load [0 ] 0
@@ -480,7 +464,6 @@ OT  Other_GETX [0 ] 0
 OT  Other_GETS [0 ] 0
 OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
-OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
 
 MT  Load [0 ] 0
@@ -493,7 +476,6 @@ MT  Other_GETX [0 ] 0
 MT  Other_GETS [0 ] 0
 MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
-MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
 
 MMT  Load [0 ] 0
@@ -506,7 +488,6 @@ MMT  Other_GETX [0 ] 0
 MMT  Other_GETS [0 ] 0
 MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
-MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
@@ -522,18 +503,18 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_reads: 441
   memory_writes: 81
   memory_refreshes: 164
-  memory_total_request_delays: 151
-  memory_delays_per_request: 0.289272
+  memory_total_request_delays: 147
+  memory_delays_per_request: 0.281609
   memory_delays_in_input_queue: 2
   memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 149
-  memory_stalls_for_bank_busy: 22
+  memory_delays_stalled_at_head_of_bank_queue: 145
+  memory_stalls_for_bank_busy: 27
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 7
-  memory_stalls_for_bus: 26
+  memory_stalls_for_arbitration: 6
+  memory_stalls_for_bus: 23
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 94
+  memory_stalls_for_read_write_turnaround: 89
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 18  10  0  36  20  19  31  22  5  4  7  4  22  41  22  3  4  6  7  13  10  18  14  41  16  5  5  12  13  18  14  62  
 
@@ -644,8 +625,6 @@ NO_B_X  PUT [0 ] 0
 NO_B_X  UnblockS [0 ] 0
 NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
-NO_B_X  DMA_READ [0 ] 0
-NO_B_X  DMA_WRITE [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -669,7 +648,6 @@ O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
 O_B  UnblockS [0 ] 0
-O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index aaa603cbd..76a97a409 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -5,13 +5,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:21
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 14:43:33
+M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
+M5 started Aug  5 2010 14:44:19
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 78448 because target called exit()
+Exiting @ tick 78408 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index e005e2d30..58de899ed 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  52381                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213928                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                1589078                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  42947                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211060                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                                1306713                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000078                       # Number of seconds simulated
-sim_ticks                                       78448                       # Number of ticks simulated
+sim_ticks                                       78408                       # Number of ticks simulated
 system.cpu.dtb.data_accesses                      717                       # DTB accesses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_hits                          709                       # DTB hits
@@ -42,25 +42,9 @@ system.cpu.itb.write_acv                            0                       # DT
 system.cpu.itb.write_hits                           0                       # DTB write hits
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                            78448                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      78448                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
+system.cpu.numCycles                            78408                       # number of cpu cycles simulated
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 69aa148c6..4c150fde0 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+children=cpu physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -74,59 +65,6 @@ simpoint=0
 system=system
 uid=100
 
-[system.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.dir_cntrl0.directory
-directory_latency=12
-memBuffer=system.dir_cntrl0.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=6
-size=134217728
-use_map=false
-version=0
-
-[system.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
-[system.l1_cntrl0]
-type=L1Cache_Controller
-buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
-transitions_per_cycle=32
-version=0
-
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -135,48 +73,34 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
-no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=false
+adaptive_routing=true
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -187,7 +111,6 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -195,20 +118,93 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.l1_cntrl0
+ext_node=system.ruby.network.topology.ext_links0.ext_node
 int_node=0
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.dir_cntrl0
+ext_node=system.ruby.network.topology.ext_links1.ext_node
 int_node=1
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index b4aefc92b..edd5bdfcc 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -18,9 +18,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: active, ordered
+virtual_net_3: inactive
 virtual_net_4: active, ordered
-virtual_net_5: inactive
+virtual_net_5: active, ordered
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -34,29 +34,40 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:40
+Real time: Jan/28/2010 10:26:06
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.32
-Virtual_time_in_minutes: 0.00533333
-Virtual_time_in_hours:   8.88889e-05
-Virtual_time_in_days:    3.7037e-06
+Virtual_time_in_seconds: 0.25
+Virtual_time_in_minutes: 0.00416667
+Virtual_time_in_hours:   6.94444e-05
+Virtual_time_in_days:    2.89352e-06
 
 Ruby_current_time: 123378
 Ruby_start_time: 0
 Ruby_cycles: 123378
 
-mbytes_resident: 35.3594
-mbytes_total: 208.918
-resident_ratio: 0.169287
+mbytes_resident: 32.8828
+mbytes_total: 32.8906
+resident_ratio: 1
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 123379 [ 123379 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
 
-ruby_cycles_executed: [ 123379 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -70,27 +81,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 2668 average:     3 | standard deviation: 0 | 0 0 0 2668 ]
-miss_latency_Directory: [binsize: 2 max: 375 count: 626 average: 179.042 | standard deviation: 22.5462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 0
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-imcomplete_dir_Times: 625
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2288 average:     3 | standard deviation: 0 | 0 0 0 2288 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 375 count: 297 average: 178.556 | standard deviation: 21.9279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 170 average:     3 | standard deviation: 0 | 0 0 0 170 ]
-miss_latency_LD_Directory: [binsize: 2 max: 281 count: 245 average: 179.678 | standard deviation: 23.5327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 210 average:     3 | standard deviation: 0 | 0 0 0 210 ]
-miss_latency_ST_Directory: [binsize: 2 max: 265 count: 84 average: 178.905 | standard deviation: 21.977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,8 +115,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10291
-page_faults: 0
+page_reclaims: 7118
+page_faults: 2103
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -131,22 +124,16 @@ block_outputs: 0
 Network Stats
 -------------
 
-total_msg_count_Control: 1878 15024
-total_msg_count_Data: 1866 134352
-total_msg_count_Response_Data: 1878 135216
-total_msg_count_Writeback_Control: 1866 14928
-total_msgs: 7488 total_bytes: 299520
-
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.157808
   links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -154,10 +141,10 @@ links_utilized_percent_switch_1: 0.158294
   links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -165,64 +152,66 @@ links_utilized_percent_switch_2: 0.252881
   links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 0 0 0 626 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 0 622 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 626
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 626
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   39.1374%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.4185%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   47.4441%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   39.1374%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   13.4185%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   47.4441%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   626    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   626    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
 
- --- L1Cache ---
+ --- L1Cache 0 ---
  - Event Counts -
-Load [415 ] 415
-Ifetch [2585 ] 2585
-Store [294 ] 294
-Data [626 ] 626
-Fwd_GETX [0 ] 0
-Inv [0 ] 0
-Replacement [622 ] 622
-Writeback_Ack [622 ] 622
-Writeback_Nack [0 ] 0
+Load  415
+Ifetch  2585
+Store  294
+Data  626
+Fwd_GETX  0
+Inv  0
+Replacement  622
+Writeback_Ack  622
+Writeback_Nack  0
 
  - Transitions -
-I  Load [245 ] 245
-I  Ifetch [297 ] 297
-I  Store [84 ] 84
-I  Inv [0 ] 0
-I  Replacement [0 ] 0
+I  Load  245
+I  Ifetch  297
+I  Store  84
+I  Inv  0 <-- 
+I  Replacement  0 <-- 
 
-II  Writeback_Nack [0 ] 0
+II  Writeback_Nack  0 <-- 
 
-M  Load [170 ] 170
-M  Ifetch [2288 ] 2288
-M  Store [210 ] 210
-M  Fwd_GETX [0 ] 0
-M  Inv [0 ] 0
-M  Replacement [622 ] 622
+M  Load  170
+M  Ifetch  2288
+M  Store  210
+M  Fwd_GETX  0 <-- 
+M  Inv  0 <-- 
+M  Replacement  622
 
-MI  Fwd_GETX [0 ] 0
-MI  Inv [0 ] 0
-MI  Writeback_Ack [622 ] 622
-MI  Writeback_Nack [0 ] 0
+MI  Fwd_GETX  0 <-- 
+MI  Inv  0 <-- 
+MI  Writeback_Ack  622
+MI  Writeback_Nack  0 <-- 
 
-MII  Fwd_GETX [0 ] 0
+MII  Fwd_GETX  0 <-- 
 
-IS  Data [542 ] 542
+IS  Data  542
 
-IM  Data [84 ] 84
+IM  Data  84
 
-Memory controller: system.dir_cntrl0.memBuffer:
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_total_requests: 1248
   memory_reads: 626
   memory_writes: 622
@@ -242,69 +231,70 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 55  40  0  100  42  42  88  45  14  10  14  10  46  82  38  6  22  14  14  48  20  52  26  92  34  10  12  24  28  44  38  138  
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
-GETX [626 ] 626
-GETS [0 ] 0
-PUTX [622 ] 622
-PUTX_NotOwner [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [626 ] 626
-Memory_Ack [622 ] 622
+GETX  626
+GETS  0
+PUTX  622
+PUTX_NotOwner  0
+DMA_READ  0
+DMA_WRITE  0
+Memory_Data  626
+Memory_Ack  622
 
  - Transitions -
-I  GETX [626 ] 626
-I  PUTX_NotOwner [0 ] 0
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  PUTX [622 ] 622
-M  PUTX_NotOwner [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-M_DRD  GETX [0 ] 0
-M_DRD  PUTX [0 ] 0
-
-M_DWR  GETX [0 ] 0
-M_DWR  PUTX [0 ] 0
-
-M_DWRI  GETX [0 ] 0
-M_DWRI  Memory_Ack [0 ] 0
-
-M_DRDI  GETX [0 ] 0
-M_DRDI  Memory_Ack [0 ] 0
-
-IM  GETX [0 ] 0
-IM  GETS [0 ] 0
-IM  PUTX [0 ] 0
-IM  PUTX_NotOwner [0 ] 0
-IM  DMA_READ [0 ] 0
-IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [626 ] 626
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTX_NotOwner [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [622 ] 622
-
-ID  GETX [0 ] 0
-ID  GETS [0 ] 0
-ID  PUTX [0 ] 0
-ID  PUTX_NotOwner [0 ] 0
-ID  DMA_READ [0 ] 0
-ID  DMA_WRITE [0 ] 0
-ID  Memory_Data [0 ] 0
-
-ID_W  GETX [0 ] 0
-ID_W  GETS [0 ] 0
-ID_W  PUTX [0 ] 0
-ID_W  PUTX_NotOwner [0 ] 0
-ID_W  DMA_READ [0 ] 0
-ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+I  GETX  626
+I  PUTX_NotOwner  0 <-- 
+I  DMA_READ  0 <-- 
+I  DMA_WRITE  0 <-- 
+
+M  GETX  0 <-- 
+M  PUTX  622
+M  PUTX_NotOwner  0 <-- 
+M  DMA_READ  0 <-- 
+M  DMA_WRITE  0 <-- 
+
+M_DRD  GETX  0 <-- 
+M_DRD  PUTX  0 <-- 
+
+M_DWR  GETX  0 <-- 
+M_DWR  PUTX  0 <-- 
+
+M_DWRI  GETX  0 <-- 
+M_DWRI  Memory_Ack  0 <-- 
+
+M_DRDI  GETX  0 <-- 
+M_DRDI  Memory_Ack  0 <-- 
+
+IM  GETX  0 <-- 
+IM  GETS  0 <-- 
+IM  PUTX  0 <-- 
+IM  PUTX_NotOwner  0 <-- 
+IM  DMA_READ  0 <-- 
+IM  DMA_WRITE  0 <-- 
+IM  Memory_Data  626
+
+MI  GETX  0 <-- 
+MI  GETS  0 <-- 
+MI  PUTX  0 <-- 
+MI  PUTX_NotOwner  0 <-- 
+MI  DMA_READ  0 <-- 
+MI  DMA_WRITE  0 <-- 
+MI  Memory_Ack  622
+
+ID  GETX  0 <-- 
+ID  GETS  0 <-- 
+ID  PUTX  0 <-- 
+ID  PUTX_NotOwner  0 <-- 
+ID  DMA_READ  0 <-- 
+ID  DMA_WRITE  0 <-- 
+ID  Memory_Data  0 <-- 
+
+ID_W  GETX  0 <-- 
+ID_W  GETS  0 <-- 
+ID_W  PUTX  0 <-- 
+ID_W  PUTX_NotOwner  0 <-- 
+ID_W  DMA_READ  0 <-- 
+ID_W  DMA_WRITE  0 <-- 
+ID_W  Memory_Ack  0 <-- 
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 6eeddaa9f..994f7ec2d 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:39
-M5 executing on SC2B0617
+M5 compiled Jan 27 2010 22:23:20
+M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
+M5 started Jan 28 2010 10:26:06
+M5 executing on svvint07
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index ef8e53c20..dd60f4239 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  50430                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213936                       # Number of bytes of host memory used
+host_inst_rate                                  51538                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214632                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
-host_tick_rate                                2406014                       # Simulator tick rate (ticks/s)
+host_tick_rate                                2467461                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000123                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           123378                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     123378                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index f6e43920a..c142fa659 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
index c6d73c335..6dd6e994b 100755
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:01
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 3dca8b0f4..f08ca087e 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 391701                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203856                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2449817385                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  97740                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203308                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+host_tick_rate                              629585132                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        2577                       # Number of instructions simulated
 sim_seconds                                  0.000017                       # Number of seconds simulated
@@ -226,24 +226,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            33538                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      33538                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          238                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
-system.cpu.num_fp_insts                             6                       # number of float instructions
-system.cpu.num_fp_register_reads                    6                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                         140                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             2577                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
-system.cpu.num_int_insts                         2375                       # number of integer instructions
-system.cpu.num_int_register_reads                2998                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               1768                       # number of times the integer registers were written
-system.cpu.num_load_insts                         419                       # Number of load instructions
-system.cpu.num_mem_refs                           717                       # number of memory refs
-system.cpu.num_store_insts                        298                       # Number of store instructions
+system.cpu.num_refs                               717                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               4                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
index 63d0e5c85..9981924d0 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -493,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
index 55c02fbce..898cae0a1 100755
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:30:08
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:42
-M5 executing on SC2B0617
+M5 compiled Jan 11 2011 18:16:01
+M5 revision b39a8457b332 7816 default ext/o3_regressions.patch qtip tip
+M5 started Jan 12 2011 04:32:17
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
index eae82995f..dbec33d6c 100644
--- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  76010                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216532                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-host_tick_rate                              138961844                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  59213                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 247916                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                              108401013                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5620                       # Number of instructions simulated
 sim_seconds                                  0.000010                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        10656                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5620                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     16                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  4889                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1207                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2145                       # Number of memory references committed
@@ -174,7 +171,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                11818                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.icache.ReadReq_accesses               1675                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 34635.549872                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209                       # average ReadReq mshr miss latency
@@ -274,8 +270,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          708                       #
 system.cpu.iew.memOrderViolationEvents             34                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          609                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             33                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    19236                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5710                       # number of integer regfile writes
 system.cpu.ipc                               0.272340                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.272340                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -367,14 +361,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        11818                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.440202                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  54                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 58                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   9243                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              30172                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         7972                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             17831                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      11904                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      9084                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                   2                       # Number of non-speculative instructions added to the IQ
@@ -472,11 +458,7 @@ system.cpu.memDep0.conflictingLoads                12                       # Nu
 system.cpu.memDep0.conflictingStores               11                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2545                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1646                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                   15396                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      3                       # number of misc regfile writes
 system.cpu.numCycles                            20636                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              346                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           4006                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents              46                       # Number of times rename has blocked due to IQ full
@@ -489,14 +471,10 @@ system.cpu.rename.RENAME:RunCycles               2314                       # Nu
 system.cpu.rename.RENAME:SquashCycles            1162                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            187                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              6085                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups          744                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        36764                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          271                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts            4                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                537                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts            1                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        22070                       # The number of ROB reads
-system.cpu.rob.rob_writes                       24470                       # The number of ROB writes
 system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
index 43c98eb5b..0aafa817f 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -66,7 +57,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
index 1becc5526..7deff62bb 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:30:08
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:42
-M5 executing on SC2B0617
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
+M5 compiled Oct 11 2010 18:37:23
+M5 revision c4e3d74d9a68 7726 default ext/mp_boot.patch qtip tip
+M5 started Oct 11 2010 18:37:39
+M5 executing on aus-bc3-b4
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
index 6adade7a3..415af9a3d 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 942479                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207780                       # Number of bytes of host memory used
+host_inst_rate                                 402550                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 249936                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              453681328                       # Simulator tick rate (ticks/s)
+host_tick_rate                              197047093                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5620                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -53,24 +53,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5633                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5633                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5620                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4889                       # number of integer instructions
-system.cpu.num_int_register_reads               14091                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1207                       # Number of load instructions
-system.cpu.num_mem_refs                          2145                       # number of memory refs
-system.cpu.num_store_insts                        938                       # Number of store instructions
+system.cpu.num_refs                              2145                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
index e20209bea..d4111deef 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
index 7a871d396..a1f858063 100755
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:30:08
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:42
-M5 executing on SC2B0617
+M5 compiled Dec  7 2010 18:51:32
+M5 revision 331c8c76d885 7806 default qtip tip ext/mismatched_new_delete.patch
+M5 started Dec  7 2010 18:51:46
+M5 executing on u200439-lin.austin.arm.com
 command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
index 59d8fd1e1..3c0d4e2a6 100644
--- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 437377                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215508                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2028175520                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 315416                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 248988                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                             1472008046                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5563                       # Number of instructions simulated
 sim_seconds                                  0.000026                       # Number of seconds simulated
@@ -237,24 +237,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            52692                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      52692                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5563                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4889                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4889                       # number of integer instructions
-system.cpu.num_int_register_reads               15212                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3689                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1207                       # Number of load instructions
-system.cpu.num_mem_refs                          2145                       # number of memory refs
-system.cpu.num_store_insts                        938                       # Number of store instructions
+system.cpu.num_refs                              2145                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              13                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
index 6b7ff5873..d479ef8bf 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=InOrderCPU
@@ -255,7 +246,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
index c56b70ea3..dc388ddae 100755
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Jan 24 2011 18:37:16
+M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip
+M5 started Jan 24 2011 18:37:18
+M5 executing on zooks
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
index ab040cd9f..170c01854 100644
--- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  42279                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206292                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-host_tick_rate                              155948553                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  32637                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156860                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
+host_tick_rate                              120410651                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000022                       # Number of seconds simulated
@@ -253,8 +253,6 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.numCycles                            43069                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.runCycles                             6002                       # Number of cycles cpu stages are processed.
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
index 74ab46a47..a9c72ed3e 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -547,7 +538,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
index c91e0bbc6..6b2281542 100755
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 21:17:36
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 21:17:39
+M5 executing on zizzer
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
index 22735f5ae..a5f35787b 100644
--- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  88897                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206716                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              218871445                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  35741                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204488                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
+host_tick_rate                               88262097                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5169                       # Number of instructions simulated
 sim_seconds                                  0.000013                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        12273                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5826                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      2                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls               87                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  5124                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      1164                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2089                       # Number of memory references committed
@@ -165,8 +162,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                12922                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1555                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36274.074074                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 35024.316109                       # average ReadReq mshr miss latency
@@ -266,8 +261,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          210                       #
 system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          259                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            118                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                     9780                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    4751                       # number of integer regfile writes
 system.cpu.ipc                               0.202151                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.202151                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -359,14 +352,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        12922                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.288346                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   7513                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              27837                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         6791                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             10538                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       8058                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      7373                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  11                       # Number of non-speculative instructions added to the IQ
@@ -451,10 +436,7 @@ system.cpu.memDep0.conflictingLoads                 5                       # Nu
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 2139                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1135                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                     136                       # number of misc regfile reads
 system.cpu.numCycles                            25570                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              238                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           3410                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles              8931                       # Number of cycles rename is idle
@@ -466,14 +448,10 @@ system.cpu.rename.RENAME:RunCycles               2609                       # Nu
 system.cpu.rename.RENAME:SquashCycles             649                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles             81                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              2709                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups            5                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        12083                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          414                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           16                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                196                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           11                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        21491                       # The number of ROB reads
-system.cpu.rob.rob_writes                       19268                       # The number of ROB writes
 system.cpu.timesIdled                             259                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index 23ffe531a..6242699da 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
index e35105442..5dbd10419 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:02
-M5 executing on SC2B0617
+M5 compiled Feb 24 2010 23:13:04
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:11:22
+M5 executing on SC2B0619
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 5f3d27685..a6694501e 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 930385                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197752                       # Number of bytes of host memory used
+host_inst_rate                                1101929                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 183300                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              445693743                       # Simulator tick rate (ticks/s)
+host_tick_rate                              525428314                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -29,24 +29,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5828                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5828                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
-system.cpu.num_int_insts                         5126                       # number of integer instructions
-system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1164                       # Number of load instructions
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_refs                              2090                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 7f769242f..b37edc581 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
-mem_mode=timing
+children=cpu physmem ruby
+mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -95,8 +86,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -117,7 +108,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -128,59 +119,6 @@ simpoint=0
 system=system
 uid=100
 
-[system.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.dir_cntrl0.directory
-directory_latency=12
-memBuffer=system.dir_cntrl0.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=6
-size=134217728
-use_map=false
-version=0
-
-[system.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
-[system.l1_cntrl0]
-type=L1Cache_Controller
-buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
-transitions_per_cycle=32
-version=0
-
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -189,48 +127,35 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
-no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
+tech_nm=45
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=false
+adaptive_routing=true
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -241,7 +166,6 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -249,20 +173,93 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.l1_cntrl0
+ext_node=system.ruby.network.topology.ext_links0.ext_node
 int_node=0
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.dir_cntrl0
+ext_node=system.ruby.network.topology.ext_links1.ext_node
 int_node=1
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 1196b3dac..87d5c1036 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:13
-M5 executing on SC2B0617
+M5 compiled Jan 21 2010 11:12:15
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 11:12:51
+M5 executing on svvint07
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 5e4d0048f..c0deed77b 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  54057                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215848                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                2713497                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  24278                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 347460                       # Number of bytes of host memory used
+host_seconds                                     0.24                       # Real time elapsed on the host
+host_tick_rate                                1220626                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000293                       # Number of seconds simulated
@@ -29,24 +29,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           292960                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     292960                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
-system.cpu.num_int_insts                         5126                       # number of integer instructions
-system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1164                       # Number of load instructions
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_refs                              2090                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index fbed8c837..e2f4de6ac 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -220,7 +211,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
index b10b0a832..bfd8a31fc 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:20:27
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:12
-M5 executing on SC2B0617
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
+M5 compiled Aug 26 2010 12:56:28
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:56:30
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
index 5ad70ef1f..f4ea21892 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 499743                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205480                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2679135009                       # Simulator tick rate (ticks/s)
+host_inst_rate                                   5098                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204896                       # Number of bytes of host memory used
+host_seconds                                     1.14                       # Real time elapsed on the host
+host_tick_rate                               28066026                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000032                       # Number of seconds simulated
@@ -213,24 +213,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            64176                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      64176                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
-system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
-system.cpu.num_int_insts                         5126                       # number of integer instructions
-system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1164                       # Number of load instructions
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_store_insts                        926                       # Number of store instructions
+system.cpu.num_refs                              2090                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
index 8c5c9e02d..3d11c96e4 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -494,7 +485,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
index 495e68f8d..29a71f392 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 17108232. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
index 15215437e..6bd581433 100755
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:21:41
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:45
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 17:18:01
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 17:18:03
+M5 executing on zizzer
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
index 122e0c39a..8b311d8d3 100644
--- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  99962                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204080                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
-host_tick_rate                              201303938                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  12762                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 202140                       # Number of bytes of host memory used
+host_seconds                                     0.45                       # Real time elapsed on the host
+host_tick_rate                               25804848                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5800                       # Number of instructions simulated
 sim_seconds                                  0.000012                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        10473                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                      5800                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                     22                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls              103                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                  5706                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                       962                       # Number of loads committed
 system.cpu.commit.COM:membars                       7                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       2008                       # Number of memory references committed
@@ -165,8 +162,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                11043                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               1490                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency 36422.279793                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434                       # average ReadReq mshr miss latency
@@ -266,8 +261,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          404                       #
 system.cpu.iew.memOrderViolationEvents             42                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          201                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect             76                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    12419                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    6594                       # number of integer regfile writes
 system.cpu.ipc                               0.247156                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.247156                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -359,14 +352,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        11043                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.344697                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      31                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  59                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                   8211                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              27329                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses         7555                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             12158                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                       9163                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                      8089                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  22                       # Number of non-speculative instructions added to the IQ
@@ -452,8 +437,6 @@ system.cpu.memDep0.conflictingStores               29                       # Nu
 system.cpu.memDep0.insertedLoads                 1681                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1450                       # Number of stores inserted to the mem dependence unit.
 system.cpu.numCycles                            23467                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              312                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           5007                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               7                       # Number of times rename has blocked due to IQ full
@@ -466,14 +449,10 @@ system.cpu.rename.RENAME:RunCycles               1825                       # Nu
 system.cpu.rename.RENAME:SquashCycles             570                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            243                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              3701                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           55                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        16177                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          337                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           22                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts                473                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           22                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        19611                       # The number of ROB reads
-system.cpu.rob.rob_writes                       18950                       # The number of ROB writes
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
 
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
index a31e803fb..1ef6f51da 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
index 4337f6cf3..a2a4d88c2 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,5 +1,5 @@
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 16904568. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 13074680. This will break if not /dev/zero.
 For more information see: http://www.m5sim.org/warn/3a2134f6
 hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
index 2ef8d7aa3..23b972156 100755
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:21:41
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:46:45
-M5 executing on SC2B0617
+M5 compiled Feb 24 2010 23:13:07
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 24 2010 23:13:11
+M5 executing on SC2B0619
 command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
index 70fcd9801..8c0754d0c 100644
--- a/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1262734                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195732                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              600414079                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 277162                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 181156                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+host_tick_rate                              136566988                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5801                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -29,24 +29,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5801                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5801                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          896                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
-system.cpu.num_fp_insts                            22                       # number of float instructions
-system.cpu.num_fp_register_reads                   20                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_func_calls                         200                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5801                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  5706                       # Number of integer alu accesses
-system.cpu.num_int_insts                         5706                       # number of integer instructions
-system.cpu.num_int_register_reads                9541                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5005                       # number of times the integer registers were written
-system.cpu.num_load_insts                         962                       # Number of load instructions
-system.cpu.num_mem_refs                          2008                       # number of memory refs
-system.cpu.num_store_insts                       1046                       # Number of store instructions
+system.cpu.num_refs                              2008                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls               9                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 67cd9246c..de14f79c7 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
index 45fe69be2..ec097652e 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:20
-M5 executing on SC2B0617
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:37:59
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 4d7f8e5ae..01cd0d37d 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 945970                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197420                       # Number of bytes of host memory used
+host_inst_rate                                 897027                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 182692                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              454943574                       # Simulator tick rate (ticks/s)
+host_tick_rate                              434663663                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000003                       # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks                                     2701000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                             5403                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                       5403                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4517                       # number of integer instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4859                       # number of times the integer registers were written
-system.cpu.num_load_insts                         724                       # Number of load instructions
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_store_insts                        678                       # Number of store instructions
+system.cpu.num_refs                              1402                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 0c625e543..eb5199f6d 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
-mem_mode=timing
+children=cpu physmem ruby
+mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -41,8 +32,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.cpu_ruby_ports.port[1]
-icache_port=system.ruby.cpu_ruby_ports.port[0]
+dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
+icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
 
 [system.cpu.dtb]
 type=SparcTLB
@@ -63,7 +54,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -74,59 +65,6 @@ simpoint=0
 system=system
 uid=100
 
-[system.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.dir_cntrl0.directory
-directory_latency=12
-memBuffer=system.dir_cntrl0.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=6
-size=134217728
-use_map=false
-version=0
-
-[system.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
-[system.l1_cntrl0]
-type=L1Cache_Controller
-buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
-transitions_per_cycle=32
-version=0
-
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -135,48 +73,35 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
-no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
+tech_nm=45
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=false
+adaptive_routing=true
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -187,7 +112,6 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -195,20 +119,93 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.l1_cntrl0
+ext_node=system.ruby.network.topology.ext_links0.ext_node
 int_node=0
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links0.ext_node]
+type=L1Cache_Controller
+children=sequencer
+buffer_size=0
+cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+deadlock_threshold=500000
+icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
+children=ext_node
 bw_multiplier=64
-ext_node=system.dir_cntrl0
+ext_node=system.ruby.network.topology.ext_links1.ext_node
 int_node=1
 latency=1
 weight=1
 
+[system.ruby.network.topology.ext_links1.ext_node]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.ruby.network.topology.ext_links1.ext_node.directory
+directory_latency=12
+memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.directory]
+type=RubyDirectoryMemory
+size=134217728
+version=0
+
+[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index 47abf6196..2464ac2ec 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -4,11 +4,16 @@
 RubySystem config:
   random_seed: 1234
   randomization: 0
+  tech_nm: 45
   cycle_period: 1
   block_size_bytes: 64
   block_size_bits: 6
   memory_size_bytes: 134217728
   memory_size_bits: 27
+DirectoryMemory Global Config: 
+  number of directory memories: 1
+  total memory size bytes: 134217728
+  total memory size bits: 27
 
 Network Configuration
 ---------------------
@@ -18,9 +23,9 @@ topology:
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
 virtual_net_2: active, ordered
-virtual_net_3: active, ordered
+virtual_net_3: inactive
 virtual_net_4: active, ordered
-virtual_net_5: inactive
+virtual_net_5: active, ordered
 virtual_net_6: inactive
 virtual_net_7: inactive
 virtual_net_8: inactive
@@ -34,29 +39,40 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:47:21
+Real time: Jan/21/2010 11:30:49
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.36
-Virtual_time_in_minutes: 0.006
-Virtual_time_in_hours:   0.0001
-Virtual_time_in_days:    4.16667e-06
+Virtual_time_in_seconds: 0.28
+Virtual_time_in_minutes: 0.00466667
+Virtual_time_in_hours:   7.77778e-05
+Virtual_time_in_days:    3.24074e-06
 
 Ruby_current_time: 253364
 Ruby_start_time: 0
 Ruby_cycles: 253364
 
-mbytes_resident: 36.8398
-mbytes_total: 210.371
-resident_ratio: 0.175156
+mbytes_resident: 34.3555
+mbytes_total: 34.5312
+resident_ratio: 0.995136
+
+Total_misses: 0
+total_misses: 0 [ 0 ]
+user_misses: 0 [ 0 ]
+supervisor_misses: 0 [ 0 ]
+
+ruby_cycles_executed: 253365 [ 253365 ]
+
+transactions_started: 0 [ 0 ]
+transactions_ended: 0 [ 0 ]
+cycles_per_transaction: 0 [ 0 ]
+misses_per_transaction: 0 [ 0 ]
 
-ruby_cycles_executed: [ 253365 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -70,27 +86,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average:     1 |
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 5483 average:     3 | standard deviation: 0 | 0 0 0 5483 ]
-miss_latency_Directory: [binsize: 2 max: 371 count: 1289 average: 178.544 | standard deviation: 22.1923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 0
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
-miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average:   159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-imcomplete_dir_Times: 1288
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 4668 average:     3 | standard deviation: 0 | 0 0 0 4668 ]
-miss_latency_IFETCH_Directory: [binsize: 2 max: 285 count: 715 average: 178.824 | standard deviation: 21.9931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 321 average:     3 | standard deviation: 0 | 0 0 0 321 ]
-miss_latency_LD_Directory: [binsize: 2 max: 285 count: 395 average: 176.514 | standard deviation: 18.6332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 494 average:     3 | standard deviation: 0 | 0 0 0 494 ]
-miss_latency_ST_Directory: [binsize: 2 max: 371 count: 179 average: 181.905 | standard deviation: 28.882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -122,8 +120,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10574
-page_faults: 0
+page_reclaims: 7494
+page_faults: 2200
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -131,22 +129,16 @@ block_outputs: 0
 Network Stats
 -------------
 
-total_msg_count_Control: 3867 30936
-total_msg_count_Data: 3855 277560
-total_msg_count_Response_Data: 3867 278424
-total_msg_count_Writeback_Control: 3855 30840
-total_msgs: 15444 total_bytes: 617760
-
 switch_0_inlinks: 2
 switch_0_outlinks: 2
 links_utilized_percent_switch_0: 0.158621
   links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
   links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
@@ -154,10 +146,10 @@ links_utilized_percent_switch_1: 0.158857
   links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
   links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
@@ -165,64 +157,63 @@ links_utilized_percent_switch_2: 0.253982
   links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
   links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 0 0 0 1289 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 0 1285 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 1289
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 1289
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   30.6439%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   13.8867%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   55.4694%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD:   30.6439%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST:   13.8867%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH:   55.4694%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1289    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode:   1289    100%
+  system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
 
- --- L1Cache ---
+ --- L1Cache 0 ---
  - Event Counts -
-Load [716 ] 716
-Ifetch [5383 ] 5383
-Store [673 ] 673
-Data [1289 ] 1289
-Fwd_GETX [0 ] 0
-Inv [0 ] 0
-Replacement [1285 ] 1285
-Writeback_Ack [1285 ] 1285
-Writeback_Nack [0 ] 0
+Load  716
+Ifetch  5383
+Store  673
+Data  1289
+Fwd_GETX  0
+Inv  0
+Replacement  1285
+Writeback_Ack  1285
+Writeback_Nack  0
 
  - Transitions -
-I  Load [395 ] 395
-I  Ifetch [715 ] 715
-I  Store [179 ] 179
-I  Inv [0 ] 0
-I  Replacement [0 ] 0
-
-II  Writeback_Nack [0 ] 0
+I  Load  395
+I  Ifetch  715
+I  Store  179
+I  Inv  0 <-- 
+I  Replacement  0 <-- 
 
-M  Load [321 ] 321
-M  Ifetch [4668 ] 4668
-M  Store [494 ] 494
-M  Fwd_GETX [0 ] 0
-M  Inv [0 ] 0
-M  Replacement [1285 ] 1285
+II  Writeback_Nack  0 <-- 
 
-MI  Fwd_GETX [0 ] 0
-MI  Inv [0 ] 0
-MI  Writeback_Ack [1285 ] 1285
-MI  Writeback_Nack [0 ] 0
+M  Load  321
+M  Ifetch  4668
+M  Store  494
+M  Fwd_GETX  0 <-- 
+M  Inv  0 <-- 
+M  Replacement  1285
 
-MII  Fwd_GETX [0 ] 0
+MI  Fwd_GETX  0 <-- 
+MI  Inv  0 <-- 
+MI  Writeback_Ack  1285
 
-IS  Data [1110 ] 1110
+IS  Data  1110
 
-IM  Data [179 ] 179
+IM  Data  179
 
-Memory controller: system.dir_cntrl0.memBuffer:
+Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
   memory_total_requests: 2574
   memory_reads: 1289
   memory_writes: 1285
@@ -242,69 +233,70 @@ Memory controller: system.dir_cntrl0.memBuffer:
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 166  40  36  48  109  42  63  241  50  34  16  26  60  64  38  46  30  88  202  144  40  58  22  20  60  120  136  125  84  134  166  66  
 
- --- Directory ---
+ --- Directory 0 ---
  - Event Counts -
-GETX [1289 ] 1289
-GETS [0 ] 0
-PUTX [1285 ] 1285
-PUTX_NotOwner [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [1289 ] 1289
-Memory_Ack [1285 ] 1285
+GETX  1289
+GETS  0
+PUTX  1285
+PUTX_NotOwner  0
+DMA_READ  0
+DMA_WRITE  0
+Memory_Data  1289
+Memory_Ack  1285
 
  - Transitions -
-I  GETX [1289 ] 1289
-I  PUTX_NotOwner [0 ] 0
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  PUTX [1285 ] 1285
-M  PUTX_NotOwner [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-M_DRD  GETX [0 ] 0
-M_DRD  PUTX [0 ] 0
-
-M_DWR  GETX [0 ] 0
-M_DWR  PUTX [0 ] 0
-
-M_DWRI  GETX [0 ] 0
-M_DWRI  Memory_Ack [0 ] 0
-
-M_DRDI  GETX [0 ] 0
-M_DRDI  Memory_Ack [0 ] 0
-
-IM  GETX [0 ] 0
-IM  GETS [0 ] 0
-IM  PUTX [0 ] 0
-IM  PUTX_NotOwner [0 ] 0
-IM  DMA_READ [0 ] 0
-IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [1289 ] 1289
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTX_NotOwner [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [1285 ] 1285
-
-ID  GETX [0 ] 0
-ID  GETS [0 ] 0
-ID  PUTX [0 ] 0
-ID  PUTX_NotOwner [0 ] 0
-ID  DMA_READ [0 ] 0
-ID  DMA_WRITE [0 ] 0
-ID  Memory_Data [0 ] 0
-
-ID_W  GETX [0 ] 0
-ID_W  GETS [0 ] 0
-ID_W  PUTX [0 ] 0
-ID_W  PUTX_NotOwner [0 ] 0
-ID_W  DMA_READ [0 ] 0
-ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack
\ No newline at end of file
+I  GETX  1289
+I  PUTX_NotOwner  0 <-- 
+I  DMA_READ  0 <-- 
+I  DMA_WRITE  0 <-- 
+
+M  GETX  0 <-- 
+M  PUTX  1285
+M  PUTX_NotOwner  0 <-- 
+M  DMA_READ  0 <-- 
+M  DMA_WRITE  0 <-- 
+
+M_DRD  GETX  0 <-- 
+M_DRD  PUTX  0 <-- 
+
+M_DWR  GETX  0 <-- 
+M_DWR  PUTX  0 <-- 
+
+M_DWRI  GETX  0 <-- 
+M_DWRI  Memory_Ack  0 <-- 
+
+M_DRDI  GETX  0 <-- 
+M_DRDI  Memory_Ack  0 <-- 
+
+IM  GETX  0 <-- 
+IM  GETS  0 <-- 
+IM  PUTX  0 <-- 
+IM  PUTX_NotOwner  0 <-- 
+IM  DMA_READ  0 <-- 
+IM  DMA_WRITE  0 <-- 
+IM  Memory_Data  1289
+
+MI  GETX  0 <-- 
+MI  GETS  0 <-- 
+MI  PUTX  0 <-- 
+MI  PUTX_NotOwner  0 <-- 
+MI  DMA_READ  0 <-- 
+MI  DMA_WRITE  0 <-- 
+MI  Memory_Ack  1285
+
+ID  GETX  0 <-- 
+ID  GETS  0 <-- 
+ID  PUTX  0 <-- 
+ID  PUTX_NotOwner  0 <-- 
+ID  DMA_READ  0 <-- 
+ID  DMA_WRITE  0 <-- 
+ID  Memory_Data  0 <-- 
+
+ID_W  GETX  0 <-- 
+ID_W  GETS  0 <-- 
+ID_W  PUTX  0 <-- 
+ID_W  PUTX_NotOwner  0 <-- 
+ID_W  DMA_READ  0 <-- 
+ID_W  DMA_WRITE  0 <-- 
+ID_W  Memory_Ack  0 <-- 
+
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index 0fda4d9b5..e4e5995ba 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:21
-M5 executing on SC2B0617
+M5 compiled Jan 21 2010 11:29:25
+M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
+M5 started Jan 21 2010 11:30:48
+M5 executing on svvint07
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 3beeb6d39..aa77d6897 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  56468                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 215424                       # Number of bytes of host memory used
+host_inst_rate                                  59331                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 347024                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                2673942                       # Simulator tick rate (ticks/s)
+host_tick_rate                                2815062                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000253                       # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks                                      253364                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     253364                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4517                       # number of integer instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
-system.cpu.num_load_insts                         724                       # Number of load instructions
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_store_insts                        678                       # Number of store instructions
+system.cpu.num_refs                              1402                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
index db5c8ef5c..35f8386c3 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
index fdcdacf3d..9b5f99faf 100755
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:21
-M5 executing on SC2B0617
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:05:08
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 28206000 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 03001ae11..49d0076df 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 510712                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205072                       # Number of bytes of host memory used
+host_inst_rate                                 369934                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207380                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                             2629194631                       # Simulator tick rate (ticks/s)
+host_tick_rate                             1923223783                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        5340                       # Number of instructions simulated
 sim_seconds                                  0.000028                       # Number of seconds simulated
@@ -195,24 +195,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      56412                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5340                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
-system.cpu.num_int_insts                         4517                       # number of integer instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
-system.cpu.num_load_insts                         724                       # Number of load instructions
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_store_insts                        678                       # Number of store instructions
+system.cpu.num_refs                              1402                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
index 562787dcb..94d399eab 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simerr
@@ -1,9 +1,7 @@
-Traceback (most recent call last):
-  File "<string>", line 1, in <module>
-  File "/proj/radl_extra/users/bbeckman/noc_m5/src/python/m5/main.py", line 359, in main
-    exec filecode in scope
-  File "tests/run.py", line 70, in <module>
-    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
-  File "tests/configs/o3-timing.py", line 40, in <module>
-    cpu = DerivO3CPU(cpu_id=0)
-NameError: name 'DerivO3CPU' is not defined
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: instruction 'fnstcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+warn: instruction 'fldcw_Mw' unimplemented
+For more information see: http://www.m5sim.org/warn/437d5238
+hack: be nice to actually delete the event here
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
index 781dde786..12f04436f 100755
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout
@@ -5,8 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:49:25
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 15:49:33
-M5 executing on svnxelk05
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
+M5 compiled Jan 31 2011 16:34:44
+M5 revision 1b98eea40540 7883 default qtip tip x86o3regressions.patch
+M5 started Jan 31 2011 16:34:46
+M5 executing on burrito
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Hello world!
+Exiting @ tick 13766000 because target called exit()
diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
index e69de29bb..0a112c922 100644
--- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -0,0 +1,437 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                  48300                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 226820                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
+host_tick_rate                               67673766                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                        9809                       # Number of instructions simulated
+sim_seconds                                  0.000014                       # Number of seconds simulated
+sim_ticks                                    13766000                       # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits                      772                       # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups                  1892                       # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect                458                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted               1920                       # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups                     1920                       # Number of BP lookups
+system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches                   1214                       # Number of branches committed
+system.cpu.commit.COM:bw_lim_events                37                       # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples        15124                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean     0.648572                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev     1.100130                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0         9612     63.55%     63.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1         3088     20.42%     83.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2         1220      8.07%     92.04% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3          836      5.53%     97.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4          232      1.53%     99.10% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5           57      0.38%     99.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6           30      0.20%     99.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7           12      0.08%     99.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8           37      0.24%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total        15124                       # Number of insts commited each cycle
+system.cpu.commit.COM:count                      9809                       # Number of instructions committed
+system.cpu.commit.COM:loads                      1056                       # Number of loads committed
+system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
+system.cpu.commit.COM:refs                       1990                       # Number of memory references committed
+system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts               462                       # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts            3832                       # The number of squashed insts skipped by commit
+system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
+system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
+system.cpu.cpi                               2.806912                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.806912                       # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses               1244                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                   1168                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency        2820000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.061093                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                   76                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits                14                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency      2173000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.049839                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses              62                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits                   621                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency      10372500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.335118                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                 313                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits              235                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency      2790500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.083512                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses             78                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  12.870504                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses                2178                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 33913.881748                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                    1789                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency        13192500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.178604                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   389                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                249                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency      4963500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.064279                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              140                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.020744                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0             84.965644                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses               2178                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 33913.881748                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits                   1789                       # number of overall hits
+system.cpu.dcache.overall_miss_latency       13192500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.178604                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  389                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits               249                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency      4963500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.064279                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             140                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.sampled_refs                    139                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                 84.965644                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1789                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles            464                       # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts           15304                       # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles              6233                       # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles               8371                       # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles             721                       # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles             56                       # Number of cycles decode is unblocking
+system.cpu.fetch.Branches                        1920                       # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines                      1255                       # Number of cache lines fetched
+system.cpu.fetch.Cycles                          9031                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes                   117                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts                           8830                       # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles                    8                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles                     469                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate                  0.069735                       # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles               1255                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches                772                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate                        0.320706                       # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples              15845                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.002083                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.178869                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     7129     44.99%     44.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4489     28.33%     73.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                     1878     11.85%     85.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                     2046     12.91%     98.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                       57      0.36%     98.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      227      1.43%     99.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                        6      0.04%     99.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                        8      0.05%     99.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                        5      0.03%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total                15845                       # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses               1255                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 37417.543860                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                    970                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       10664000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.227092                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  285                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits                27                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency      9040500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.205578                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             258                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                   3.759690                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses                1255                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 37417.543860                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                     970                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        10664000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.227092                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   285                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                 27                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency      9040500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.205578                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              258                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.061525                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            126.002915                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses               1255                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 37417.543860                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits                    970                       # number of overall hits
+system.cpu.icache.overall_miss_latency       10664000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.227092                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  285                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                27                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency      9040500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.205578                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             258                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements                      0                       # number of replacements
+system.cpu.icache.sampled_refs                    258                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                126.002915                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      970                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idleCycles                           11688                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches                     1318                       # Number of branches executed
+system.cpu.iew.EXEC:nop                             0                       # number of nop insts executed
+system.cpu.iew.EXEC:rate                     0.434678                       # Inst execution rate
+system.cpu.iew.EXEC:refs                         2353                       # number of memory reference insts executed
+system.cpu.iew.EXEC:stores                       1060                       # Number of stores executed
+system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
+system.cpu.iew.WB:consumers                     10358                       # num instructions consuming a value
+system.cpu.iew.WB:count                         11818                       # cumulative count of insts written-back
+system.cpu.iew.WB:fanout                     0.702935                       # average fanout of values written-back
+system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers                      7281                       # num instructions producing a value
+system.cpu.iew.WB:rate                       0.429230                       # insts written-back per cycle
+system.cpu.iew.WB:sent                          11866                       # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts                  487                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles                      58                       # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts                  1535                       # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts                 17                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts               418                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts                 1238                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               13635                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts                  1293                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               536                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts                 11968                       # Number of executed instructions
+system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                    721                       # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles                     6                       # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads              21                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation            7                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads            0                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads          479                       # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores          304                       # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect          390                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             97                       # Number of branches that were predicted taken incorrectly
+system.cpu.ipc                               0.356263                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.356263                       # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass            3      0.02%      0.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu           10018     80.12%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult              0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     80.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead           1360     10.88%     91.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite          1123      8.98%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total            12504                       # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt                     4                       # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate             0.000320                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu                 0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult              0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%      0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead                3     75.00%     75.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite               1     25.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:issued_per_cycle::samples        15845                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean     0.789145                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev     0.977935                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0          8160     51.50%     51.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1          4079     25.74%     77.24% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2          2594     16.37%     93.61% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3           834      5.26%     98.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4           157      0.99%     99.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5            19      0.12%     99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6             2      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7             0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8             0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::max_value            6                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total        15845                       # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate                     0.454146                       # Inst issue rate
+system.cpu.iq.iqInstsAdded                      13618                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued                     12504                       # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded                  17                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined            3342                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedNonSpecRemoved              4                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined         5066                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses              78                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency      2690500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses                78                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency      2443500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses           78                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses               320                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency      10872000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.993750                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 318                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency      9859500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.993750                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            318                       # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  0.006309                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses                398                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34248.737374                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency       13562500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.994975                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  396                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency     12303000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.994975                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             396                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.occ_%::0                  0.004816                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0           157.820330                       # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses               398                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34248.737374                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                     2                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency      13562500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.994975                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 396                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency     12303000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.994975                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            396                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.sampled_refs                   317                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse               157.820330                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
+system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads                 1535                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1238                       # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles                            27533                       # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles              105                       # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps           9368                       # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents               6                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles              6603                       # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents             15                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups          38664                       # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts           14745                       # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands        13787                       # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles               8027                       # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles             721                       # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles            108                       # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps              4419                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles          281                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts           20                       # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts                169                       # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts           17                       # count of temporary serializing insts renamed
+system.cpu.timesIdled                             208                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
index 0fc15a925..f4bc2655d 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,13 +10,6 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -66,7 +59,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
index 96e1eca08..0a2d88a32 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:49:25
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:09
-M5 executing on SC2B0617
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic
+M5 compiled Jan 31 2011 14:03:49
+M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
+M5 started Jan 31 2011 14:03:51
+M5 executing on burrito
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
index d93e7eed9..7219cd6a7 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 805088                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 199588                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              453713368                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 137874                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215488                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+host_tick_rate                               79078853                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000006                       # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks                                     5651000                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            11303                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      11303                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
-system.cpu.num_int_insts                         9715                       # number of integer instructions
-system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1056                       # Number of load instructions
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_store_insts                        934                       # Number of store instructions
+system.cpu.num_refs                              1990                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index d0926d8e6..5985e429a 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -10,13 +10,6 @@ type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -63,7 +56,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -154,7 +147,6 @@ tracer=system.ruby.tracer
 [system.ruby.cpu_ruby_ports]
 type=RubySequencer
 children=dcache
-access_phys_mem=true
 dcache=system.ruby.cpu_ruby_ports.dcache
 deadlock_threshold=500000
 icache=system.ruby.cpu_ruby_ports.dcache
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 27560c564..adfa92f7c 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:48:09
+Real time: Feb/04/2011 03:47:05
 
 Profiler Stats
 --------------
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.36
-Virtual_time_in_minutes: 0.006
-Virtual_time_in_hours:   0.0001
-Virtual_time_in_days:    4.16667e-06
+Virtual_time_in_seconds: 0.19
+Virtual_time_in_minutes: 0.00316667
+Virtual_time_in_hours:   5.27778e-05
+Virtual_time_in_days:    2.19907e-06
 
 Ruby_current_time: 276484
 Ruby_start_time: 0
 Ruby_cycles: 276484
 
-mbytes_resident: 36.707
-mbytes_total: 212.684
-resident_ratio: 0.172627
+mbytes_resident: 38.8594
+mbytes_total: 233.992
+resident_ratio: 0.166088
 
 ruby_cycles_executed: [ 276485 ]
 
@@ -71,9 +71,8 @@ All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
 miss_latency: [binsize: 2 max: 371 count: 8900 average: 30.0656 | standard deviation: 63.8436 | 0 7523 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
 miss_latency_IFETCH: [binsize: 2 max: 369 count: 6910 average: 18.6938 | standard deviation: 50.1996 | 0 6287 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD: [binsize: 2 max: 293 count: 1048 average: 86.792 | standard deviation: 89.333 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 293 count: 1056 average: 86.3144 | standard deviation: 89.2896 | 0 556 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST: [binsize: 2 max: 371 count: 934 average: 50.6017 | standard deviation: 78.9939 | 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_RMW_Read: [binsize: 1 max: 169 count: 8 average: 23.75 | standard deviation: 58.6905 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_L1Cache: [binsize: 1 max: 3 count: 7523 average:     3 | standard deviation: 0 | 0 0 0 7523 ]
 miss_latency_Directory: [binsize: 2 max: 371 count: 1377 average: 177.934 | standard deviation: 21.7881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 9 4 1 3 2 328 243 178 299 187 7 4 1 3 0 8 6 4 9 5 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 6 11 19 16 9 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -88,12 +87,10 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 ave
 imcomplete_dir_Times: 1376
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6287 average:     3 | standard deviation: 0 | 0 0 0 6287 ]
 miss_latency_IFETCH_Directory: [binsize: 2 max: 369 count: 623 average: 177.067 | standard deviation: 19.4782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 2 2 0 1 0 158 125 57 116 102 5 3 0 2 0 8 5 3 4 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 3 8 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 549 average:     3 | standard deviation: 0 | 0 0 0 549 ]
-miss_latency_LD_Directory: [binsize: 2 max: 293 count: 499 average: 178.98 | standard deviation: 22.8519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 103 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 556 average:     3 | standard deviation: 0 | 0 0 0 556 ]
+miss_latency_LD_Directory: [binsize: 2 max: 293 count: 500 average: 178.96 | standard deviation: 22.8334 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 1 1 1 1 104 47 87 151 61 1 0 0 1 0 0 1 0 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3 1 14 8 2 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average:     3 | standard deviation: 0 | 0 0 0 680 ]
 miss_latency_ST_Directory: [binsize: 2 max: 371 count: 254 average: 178.039 | standard deviation: 24.8377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 0 1 1 66 71 34 32 24 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 8 2 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
-miss_latency_RMW_Read_Directory: [binsize: 1 max: 169 count: 1 average:   169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -125,11 +122,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10563
+page_reclaims: 11021
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 0
+block_outputs: 64
 
 Network Stats
 -------------
@@ -180,17 +177,17 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
   system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
   system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   36.2382%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   18.5185%
+  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   36.3108%
+  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   18.4459%
   system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   45.2433%
 
   system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   1377    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [1048 ] 1048
+Load [1056 ] 1056
 Ifetch [6910 ] 6910
-Store [942 ] 942
+Store [934 ] 934
 Data [1377 ] 1377
 Fwd_GETX [0 ] 0
 Inv [0 ] 0
@@ -199,17 +196,17 @@ Writeback_Ack [1373 ] 1373
 Writeback_Nack [0 ] 0
 
  - Transitions -
-I  Load [499 ] 499
+I  Load [500 ] 500
 I  Ifetch [623 ] 623
-I  Store [255 ] 255
+I  Store [254 ] 254
 I  Inv [0 ] 0
 I  Replacement [0 ] 0
 
 II  Writeback_Nack [0 ] 0
 
-M  Load [549 ] 549
+M  Load [556 ] 556
 M  Ifetch [6287 ] 6287
-M  Store [687 ] 687
+M  Store [680 ] 680
 M  Fwd_GETX [0 ] 0
 M  Inv [0 ] 0
 M  Replacement [1373 ] 1373
@@ -221,9 +218,9 @@ MI  Writeback_Nack [0 ] 0
 
 MII  Fwd_GETX [0 ] 0
 
-IS  Data [1122 ] 1122
+IS  Data [1123 ] 1123
 
-IM  Data [255 ] 255
+IM  Data [254 ] 254
 
 Memory controller: system.dir_cntrl0.memBuffer:
   memory_total_requests: 2750
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 58b226717..4e5806bd6 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:49:25
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:09
-M5 executing on SC2B0617
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
+M5 compiled Feb  4 2011 03:47:02
+M5 revision afcc4492291f 7892 default qbase qtip rubystatupdate.patch tip
+M5 started Feb  4 2011 03:47:05
+M5 executing on burrito
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 10481a15c..806c6c56a 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  86745                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 217792                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                2441144                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 106685                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 239612                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+host_tick_rate                                3002497                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000276                       # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks                                      276484                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     276484                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
-system.cpu.num_int_insts                         9715                       # number of integer instructions
-system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1056                       # Number of load instructions
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_store_insts                        934                       # Number of store instructions
+system.cpu.num_refs                              1990                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
index 968af204d..9743aff19 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,13 +10,6 @@ type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +159,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
index 4427ab320..d7b40c980 100755
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:49:25
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:48:09
-M5 executing on SC2B0617
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
+M5 compiled Jan 31 2011 14:03:49
+M5 revision aa283c8952a9 7880 default qtip stupdstats.patch tip
+M5 started Jan 31 2011 14:03:51
+M5 executing on burrito
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
index db1eee29b..519e51040 100644
--- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 650703                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 207316                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1875725370                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 101671                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 223168                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                              297579540                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                        9810                       # Number of instructions simulated
 sim_seconds                                  0.000029                       # Number of seconds simulated
@@ -195,24 +195,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            57536                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      57536                       # Number of busy cycles
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             9810                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
-system.cpu.num_int_insts                         9715                       # number of integer instructions
-system.cpu.num_int_register_reads               26194                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               9368                       # number of times the integer registers were written
-system.cpu.num_load_insts                        1056                       # Number of load instructions
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_store_insts                        934                       # Number of store instructions
+system.cpu.num_refs                              1990                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              11                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index e2a6430b6..eef6bf91e 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -493,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -512,7 +503,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index a96cc8e57..1d43d276a 100755
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:00
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 16:24:53
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 16:24:57
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index 5a28c525f..561bc8cb1 100644
--- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  86390                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 206216                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-host_tick_rate                               95458320                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  10660                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 204092                       # Number of bytes of host memory used
+host_seconds                                     1.20                       # Real time elapsed on the host
+host_tick_rate                               11797749                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       12773                       # Number of instructions simulated
 sim_seconds                                  0.000014                       # Number of seconds simulated
@@ -43,15 +43,6 @@ system.cpu.commit.COM:committed_per_cycle::total        22158
 system.cpu.commit.COM:count::0                   6404                       # Number of instructions committed
 system.cpu.commit.COM:count::1                   6403                       # Number of instructions committed
 system.cpu.commit.COM:count::total              12807                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts::0                  10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:fp_insts::1                  10                       # Number of committed floating point instructions.
-system.cpu.commit.COM:fp_insts::total              20                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls::0           127                       # Number of function calls committed.
-system.cpu.commit.COM:function_calls::1           127                       # Number of function calls committed.
-system.cpu.commit.COM:function_calls::total          254                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts::0               6321                       # Number of committed integer instructions.
-system.cpu.commit.COM:int_insts::1               6321                       # Number of committed integer instructions.
-system.cpu.commit.COM:int_insts::total          12642                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads::0                   1185                       # Number of loads committed
 system.cpu.commit.COM:loads::1                   1185                       # Number of loads committed
 system.cpu.commit.COM:loads::total               2370                       # Number of loads committed
@@ -248,8 +239,6 @@ system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Nu
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::total                22205                       # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.icache.ReadReq_accesses               3993                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584                       # average ReadReq miss latency
@@ -435,8 +424,6 @@ system.cpu.iew.lsq.thread.1.squashedStores          367                       #
 system.cpu.iew.memOrderViolationEvents            131                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect         1010                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            260                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    23900                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   13586                       # number of integer regfile writes
 system.cpu.ipc::0                            0.225857                       # IPC: Instructions Per Cycle
 system.cpu.ipc::1                            0.225821                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.451678                       # IPC: Total IPC of All Threads
@@ -603,14 +590,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        22205                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.703773                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                  20041                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              62207                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses        18120                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             32069                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      22957                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     19902                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                  46                       # Number of non-speculative instructions added to the IQ
@@ -758,11 +737,7 @@ system.cpu.memDep1.conflictingLoads                22                       # Nu
 system.cpu.memDep1.conflictingStores                7                       # Number of conflicting stores.
 system.cpu.memDep1.insertedLoads                 2368                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep1.insertedStores                1232                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
 system.cpu.numCycles                            28279                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles             2728                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps           9166                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IQFullEvents               4                       # Number of times rename has blocked due to IQ full
@@ -776,14 +751,10 @@ system.cpu.rename.RENAME:RunCycles               4411                       # Nu
 system.cpu.rename.RENAME:SquashCycles            2039                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles           1326                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              9705                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups           34                       # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups        31597                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles          679                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts           50                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts               3216                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts           38                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                       106394                       # The number of ROB reads
-system.cpu.rob.rob_writes                       48170                       # The number of ROB writes
 system.cpu.timesIdled                             276                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload0.PROG:num_syscalls             17                       # Number of system calls
 system.cpu.workload1.PROG:num_syscalls             17                       # Number of system calls
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
index d70bc91f6..285549a9c 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=DerivO3CPU
@@ -493,7 +484,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
index 41e283efb..7c5c285a5 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:21
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 21:17:52
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 21:18:06
+M5 executing on zizzer
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index e3bbf84bb..5aa081cb3 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 112587                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 205776                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-host_tick_rate                              145080138                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  91156                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 203828                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
+host_tick_rate                              117504787                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       14449                       # Number of instructions simulated
 sim_seconds                                  0.000019                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu.commit.COM:committed_per_cycle::min_value            0
 system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.COM:committed_per_cycle::total        27579                       # Number of insts commited each cycle
 system.cpu.commit.COM:count                     15175                       # Number of instructions committed
-system.cpu.commit.COM:fp_insts                      0                       # Number of committed floating point instructions.
-system.cpu.commit.COM:function_calls                0                       # Number of function calls committed.
-system.cpu.commit.COM:int_insts                 12186                       # Number of committed integer instructions.
 system.cpu.commit.COM:loads                      2226                       # Number of loads committed
 system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
 system.cpu.commit.COM:refs                       3674                       # Number of memory references committed
@@ -254,8 +251,6 @@ system.cpu.iew.lsq.thread.0.squashedStores          477                       #
 system.cpu.iew.memOrderViolationEvents             54                       # Number of memory order violations
 system.cpu.iew.predictedNotTakenIncorrect          560                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.predictedTakenIncorrect            240                       # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads                    28146                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   15679                       # number of integer regfile writes
 system.cpu.ipc                               0.387238                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.387238                       # IPC: Total IPC of All Threads
 system.cpu.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -347,14 +342,6 @@ system.cpu.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:issued_per_cycle::total        28740                       # Number of insts issued each cycle
 system.cpu.iq.ISSUE:rate                     0.483451                       # Inst issue rate
-system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses                  18164                       # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads              65024                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses        17128                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes             23367                       # Number of integer instruction queue writes
 system.cpu.iq.iqInstsAdded                      18671                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqInstsIssued                     18039                       # Number of instructions issued
 system.cpu.iq.iqNonSpecInstsAdded                 566                       # Number of non-speculative instructions added to the IQ
@@ -430,11 +417,7 @@ system.cpu.memDep0.conflictingLoads                13                       # Nu
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
 system.cpu.memDep0.insertedLoads                 3058                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1925                       # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads                    6238                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.numCycles                            37313                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.rename.RENAME:BlockCycles              254                       # Number of cycles rename is blocking
 system.cpu.rename.RENAME:CommittedMaps          13832                       # Number of HB maps that are committed
 system.cpu.rename.RENAME:IdleCycles             13569                       # Number of cycles rename is idle
@@ -446,13 +429,10 @@ system.cpu.rename.RENAME:RunCycles               7042                       # Nu
 system.cpu.rename.RENAME:SquashCycles            1178                       # Number of cycles rename is squashing
 system.cpu.rename.RENAME:UnblockCycles            421                       # Number of cycles rename is unblocking
 system.cpu.rename.RENAME:UndoneMaps              5696                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:int_rename_lookups        40450                       # Number of integer rename lookups
 system.cpu.rename.RENAME:serializeStallCycles         6276                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RENAME:serializingInsts          617                       # count of serializing insts renamed
 system.cpu.rename.RENAME:skidInsts               2691                       # count of insts added to the skid buffer
 system.cpu.rename.RENAME:tempSerializingInsts          583                       # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads                        46980                       # The number of ROB reads
-system.cpu.rob.rob_writes                       41800                       # The number of ROB writes
 system.cpu.timesIdled                             183                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index d09523ca1..91a9c57a5 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
index e27e111a2..a758d34e6 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:21
-M5 executing on SC2B0617
+M5 compiled Feb 25 2010 03:11:27
+M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
+M5 started Feb 25 2010 03:38:01
+M5 executing on SC2B0619
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 8a0b232a8..970d208fc 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1374672                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 197224                       # Number of bytes of host memory used
+host_inst_rate                                1098364                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 182400                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
-host_tick_rate                              675458817                       # Simulator tick rate (ticks/s)
+host_tick_rate                              540894569                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000008                       # Number of seconds simulated
@@ -11,24 +11,8 @@ sim_ticks                                     7618500                       # Nu
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            15238                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      15238                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                            15175                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
-system.cpu.num_int_insts                        12231                       # number of integer instructions
-system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13832                       # number of times the integer registers were written
-system.cpu.num_load_insts                        2232                       # Number of load instructions
-system.cpu.num_mem_refs                          3684                       # number of memory refs
-system.cpu.num_store_insts                       1452                       # Number of store instructions
+system.cpu.num_refs                              3684                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
index e0d239809..04665360b 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -166,7 +157,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
index e887d8fcb..27524a121 100755
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:21
-M5 executing on SC2B0617
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:44
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 5e10ec9cc..6c8846c5d 100644
--- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 702644                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 204952                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-host_tick_rate                             1909286073                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 255958                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 207264                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+host_tick_rate                              701295215                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                       15175                       # Number of instructions simulated
 sim_seconds                                  0.000042                       # Number of seconds simulated
@@ -197,24 +197,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                            83600                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                      83600                       # Number of busy cycles
-system.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                            15175                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
-system.cpu.num_int_insts                        12231                       # number of integer instructions
-system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13831                       # number of times the integer registers were written
-system.cpu.num_load_insts                        2232                       # Number of load instructions
-system.cpu.num_mem_refs                          3684                       # number of memory refs
-system.cpu.num_store_insts                       1452                       # Number of store instructions
+system.cpu.num_refs                              3684                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index a8dd05895..26eb3724f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -1,33 +1,24 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -274,7 +265,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -294,7 +285,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -420,7 +411,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -891,9 +882,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=system.disk0 system.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 0372a3b05..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -2,8 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 05b982df2..41c773ee0 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:18:06
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:44:52
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 23:00:12
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 23:09:56
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index bea2dec1c..8f44fff37 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2482903                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 294432                       # Number of bytes of host memory used
-host_seconds                                    25.44                       # Real time elapsed on the host
-host_tick_rate                            73531568595                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4418519                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 326752                       # Number of bytes of host memory used
+host_seconds                                    14.29                       # Real time elapsed on the host
+host_tick_rate                           130854140423                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
@@ -305,24 +305,8 @@ system.cpu0.kern.syscall::147                       2      0.88%    100.00% # nu
 system.cpu0.kern.syscall::total                   226                       # number of syscalls executed
 system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
 system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles              57233843.686322                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts      6808233                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
-system.cpu0.num_fp_insts                       299810                       # number of float instructions
-system.cpu0.num_fp_register_reads              147724                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             150835                       # number of times the floating registers were written
-system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles              3683437089.313678                       # Number of idle cycles
 system.cpu0.num_insts                        57222076                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
-system.cpu0.num_int_insts                    53249924                       # number of integer instructions
-system.cpu0.num_int_register_reads           73318596                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39827534                       # number of times the integer registers were written
-system.cpu0.num_load_insts                    9184477                       # Number of load instructions
-system.cpu0.num_mem_refs                     15135515                       # number of memory refs
-system.cpu0.num_store_insts                   5951038                       # Number of store instructions
+system.cpu0.num_refs                         15135515                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
@@ -603,24 +587,8 @@ system.cpu1.kern.syscall::132                       2      2.00%    100.00% # nu
 system.cpu1.kern.syscall::total                   100                       # number of syscalls executed
 system.cpu1.not_idle_fraction                0.001587                       # Percentage of non-idle cycles
 system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              5936690.922345                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts       577190                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
-system.cpu1.num_fp_insts                        28590                       # number of float instructions
-system.cpu1.num_fp_register_reads               17889                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              17683                       # number of times the floating registers were written
-system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles              3734312190.077655                       # Number of idle cycles
 system.cpu1.num_insts                         5931958                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
-system.cpu1.num_int_insts                     5550578                       # number of integer instructions
-system.cpu1.num_int_register_reads            7657288                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           4163275                       # number of times the integer registers were written
-system.cpu1.num_load_insts                    1170888                       # Number of load instructions
-system.cpu1.num_mem_refs                      1926244                       # number of memory refs
-system.cpu1.num_store_insts                    755356                       # Number of store instructions
+system.cpu1.num_refs                          1926244                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 948e07caa..c5b353159 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -1,33 +1,24 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -167,7 +158,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -187,7 +178,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -313,7 +304,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -784,9 +775,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=system.disk0 system.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 0372a3b05..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
@@ -2,8 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index b54139f40..85e98e7a4 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,12 +7,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:18:06
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:44:51
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 23:00:12
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 23:09:41
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 09f938159..e2b7c8ed7 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2515835                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 293128                       # Number of bytes of host memory used
-host_seconds                                    23.86                       # Real time elapsed on the host
-host_tick_rate                            76655119142                       # Simulator tick rate (ticks/s)
+host_inst_rate                                4413707                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 325356                       # Number of bytes of host memory used
+host_seconds                                    13.60                       # Real time elapsed on the host
+host_tick_rate                           134480396261                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_seconds                                  1.829332                       # Number of seconds simulated
@@ -297,24 +297,8 @@ system.cpu.kern.syscall::147                        2      0.61%    100.00% # nu
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
 system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               3598608979.180807                       # Number of idle cycles
 system.cpu.num_insts                         60038305                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
-system.cpu.num_int_insts                     55913521                       # number of integer instructions
-system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
-system.cpu.num_load_insts                     9747513                       # Number of load instructions
-system.cpu.num_mem_refs                      16115709                       # number of memory refs
-system.cpu.num_store_insts                    6368196                       # Number of store instructions
+system.cpu.num_refs                          16115709                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index d4e4b7f37..ef977d929 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -1,33 +1,24 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -268,7 +259,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -288,7 +279,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -414,7 +405,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -885,9 +876,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=system.disk0 system.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 0372a3b05..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -2,8 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index f2cae639d..8585e8d27 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:18:06
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:44:52
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 23:00:12
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 23:10:42
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 562628000
 Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 9839f1b5a..0517b4d72 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1140947                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 291380                       # Number of bytes of host memory used
-host_seconds                                    52.02                       # Real time elapsed on the host
-host_tick_rate                            37649358214                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1781653                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 323564                       # Number of bytes of host memory used
+host_seconds                                    33.32                       # Real time elapsed on the host
+host_tick_rate                            58791386546                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    59355643                       # Number of instructions simulated
 sim_seconds                                  1.958647                       # Number of seconds simulated
@@ -360,24 +360,8 @@ system.cpu0.kern.syscall::147                       2      0.90%    100.00% # nu
 system.cpu0.kern.syscall::total                   222                       # number of syscalls executed
 system.cpu0.not_idle_fraction                0.060263                       # Percentage of non-idle cycles
 system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles              235989726.444158                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts      6237040                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
-system.cpu0.num_fp_insts                       293967                       # number of float instructions
-system.cpu0.num_fp_register_reads              143353                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             146452                       # number of times the floating registers were written
-system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles              3680034047.555842                       # Number of idle cycles
 system.cpu0.num_insts                        54072652                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
-system.cpu0.num_int_insts                    50043234                       # number of integer instructions
-system.cpu0.num_int_register_reads           68528072                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          37080372                       # number of times the integer registers were written
-system.cpu0.num_load_insts                    8664914                       # Number of load instructions
-system.cpu0.num_mem_refs                     14724357                       # number of memory refs
-system.cpu0.num_store_insts                   6059443                       # Number of store instructions
+system.cpu0.num_refs                         14724357                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
@@ -707,24 +691,8 @@ system.cpu1.kern.syscall::132                       3      2.88%    100.00% # nu
 system.cpu1.kern.syscall::total                   104                       # number of syscalls executed
 system.cpu1.not_idle_fraction                0.004865                       # Percentage of non-idle cycles
 system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              19057169.001990                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts       510974                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
-system.cpu1.num_fp_insts                        34031                       # number of float instructions
-system.cpu1.num_fp_register_reads               22062                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              21862                       # number of times the floating registers were written
-system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles              3898237020.998010                       # Number of idle cycles
 system.cpu1.num_insts                         5282991                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
-system.cpu1.num_int_insts                     4948310                       # number of integer instructions
-system.cpu1.num_int_register_reads            6886066                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           3732878                       # number of times the integer registers were written
-system.cpu1.num_load_insts                    1056124                       # Number of load instructions
-system.cpu1.num_mem_refs                      1710778                       # number of memory refs
-system.cpu1.num_store_insts                    654654                       # Number of store instructions
+system.cpu1.num_refs                          1710778                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 5942af7ad..14aa8c52d 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -1,33 +1,24 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -164,7 +155,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -184,7 +175,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -310,7 +301,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -781,9 +772,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=system.disk0 system.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 0372a3b05..83c71fc5c 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -2,8 +2,4 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index 7f56804aa..af718c31f 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,12 +7,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:18:06
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:44:52
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 23:00:12
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 23:10:12
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index cff4040d5..37bf681b4 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1177916                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289856                       # Number of bytes of host memory used
-host_seconds                                    47.66                       # Real time elapsed on the host
-host_tick_rate                            40193458044                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1917155                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 322176                       # Number of bytes of host memory used
+host_seconds                                    29.28                       # Real time elapsed on the host
+host_tick_rate                            65417896896                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_seconds                                  1.915549                       # Number of seconds simulated
@@ -341,24 +341,8 @@ system.cpu.kern.syscall::147                        2      0.61%    100.00% # nu
 system.cpu.kern.syscall::total                    326                       # number of syscalls executed
 system.cpu.not_idle_fraction                 0.063469                       # Percentage of non-idle cycles
 system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles               243154546.001873                       # Number of busy cycles
-system.cpu.num_conditional_control_insts      6464616                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                 324192                       # Number of float alu accesses
-system.cpu.num_fp_insts                        324192                       # number of float instructions
-system.cpu.num_fp_register_reads               163510                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166384                       # number of times the floating registers were written
-system.cpu.num_func_calls                     1482242                       # number of times a function call or return occured
-system.cpu.num_idle_cycles               3587943187.998127                       # Number of idle cycles
 system.cpu.num_insts                         56137087                       # Number of instructions executed
-system.cpu.num_int_alu_accesses              52011214                       # Number of integer alu accesses
-system.cpu.num_int_insts                     52011214                       # number of integer instructions
-system.cpu.num_int_register_reads            71259077                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38485860                       # number of times the integer registers were written
-system.cpu.num_load_insts                     9094324                       # Number of load instructions
-system.cpu.num_mem_refs                      15462519                       # number of memory refs
-system.cpu.num_store_insts                    6368195                       # Number of store instructions
+system.cpu.num_refs                          15462519                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 260c1cb37..505488008 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -1,9 +1,7 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxArmSystem
@@ -11,20 +9,13 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -167,7 +158,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/ael-arm.ext2
+file=/chips/pd/randd/dist/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 8914d507c..122561307 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -1,5 +1,39 @@
-fatal: Could not load kernel file /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
- @ cycle 0
-[System:build/ARM_FS/sim/system.cc, line 118]
-Memory Usage: 210184 KBytes
-For more information see: http://www.m5sim.org/fatal/406aceb6
+warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: The clidr register always reports 0 caches.
+For more information see: http://www.m5sim.org/warn/23a3c326
+warn: The csselr register isn't implemented.
+For more information see: http://www.m5sim.org/warn/c0c486b8
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: The ccsidr register isn't implemented and always reads as 0.
+For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: 	instruction 'mcr dccimvac' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr dccmvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr icimvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+For more information see: http://www.m5sim.org/warn/7998f2ea
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index ea23f1508..05fcdedb2 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:34:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 15:35:03
-M5 executing on svnxelk05
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
+M5 compiled Oct 15 2010 11:17:32
+M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip
+M5 started Oct 15 2010 11:17:48
+M5 executing on aus-bc3-b4
+command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 25821310500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index e69de29bb..1bfa8bc8a 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -0,0 +1,399 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                1831927                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 384484                       # Number of bytes of host memory used
+host_seconds                                    27.81                       # Real time elapsed on the host
+host_tick_rate                              928414614                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                    50949504                       # Number of instructions simulated
+sim_seconds                                  0.025821                       # Number of seconds simulated
+sim_ticks                                 25821310500                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0        96794                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        96794                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::0         91895                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        91895                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.050613                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0         4899                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         4899                       # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses::0         7714516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      7714516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0             7482193                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7482193                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0       0.030115                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0            232323                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        232323                       # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses::0        96793                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        96793                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0          96793                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        96793                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0        6604860                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6604860                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0            6433311                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6433311                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0      0.025973                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0           171549                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       171549                       # number of WriteReq misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  34.663994                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses::0         14319376                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     14319376                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             13915504                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13915504                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.028205                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses::0             403872                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         403872                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.999475                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            511.731250                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        14319376                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     14319376                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits::0            13915504                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13915504                       # number of overall hits
+system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.028205                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses::0            403872                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total        403872                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements                 406424                       # number of replacements
+system.cpu.dcache.sampled_refs                 406936                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                511.731250                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14106027                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               21760000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   379025                       # number of writebacks
+system.cpu.dtb.accesses                      15336291                       # DTB accesses
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries                     2242                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits                          15330762                       # DTB hits
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.misses                            5529                       # DTB misses
+system.cpu.dtb.perms_faults                       255                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults                    768                       # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses                  8622893                       # DTB read accesses
+system.cpu.dtb.read_hits                      8618361                       # DTB read hits
+system.cpu.dtb.read_misses                       4532                       # DTB read misses
+system.cpu.dtb.write_accesses                 6713398                       # DTB write accesses
+system.cpu.dtb.write_hits                     6712401                       # DTB write hits
+system.cpu.dtb.write_misses                       997                       # DTB write misses
+system.cpu.icache.ReadReq_accesses::0        41172623                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41172623                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits::0            40741841                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        40741841                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate::0       0.010463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0            430782                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        430782                       # number of ReadReq misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                  94.576690                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses::0         41172623                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41172623                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0             40741841                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         40741841                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.010463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_misses::0             430782                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         430782                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.929162                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            475.731149                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0        41172623                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41172623                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits::0            40741841                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total        40741841                       # number of overall hits
+system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.010463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_misses::0            430782                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        430782                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements                 430269                       # number of replacements
+system.cpu.icache.sampled_refs                 430781                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                475.731149                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 40741841                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle             4544230000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                    33727                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                      41173750                       # DTB accesses
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries                     1478                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits                          41170928                       # DTB hits
+system.cpu.itb.inst_accesses                 41173750                       # ITB inst accesses
+system.cpu.itb.inst_hits                     41170928                       # ITB inst hits
+system.cpu.itb.inst_misses                       2822                       # ITB inst misses
+system.cpu.itb.misses                            2822                       # DTB misses
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                         51642622                       # number of cpu cycles simulated
+system.cpu.num_insts                         50949504                       # Number of instructions executed
+system.cpu.num_refs                          16092645                       # Number of memory references
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                    0                       # number of overall misses
+system.iocache.overall_misses::total                0                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                           0                       # number of writebacks
+system.l2c.ReadExReq_accesses::0               169714                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           169714                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_hits::0                    60310                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                60310                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0            0.644637                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 109404                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             109404                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0                 665898                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                   6073                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             671971                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0                     648226                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                       6049                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 654275                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0              0.026539                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.003952                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.030491                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                    17672                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       24                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                17696                       # number of ReadReq misses
+system.l2c.UpgradeReq_accesses::0                1835                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1835                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0                      17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0           0.990736                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  1818                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1818                       # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0               412752                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           412752                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   412752                       # number of Writeback hits
+system.l2c.Writeback_hits::total               412752                       # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          6.885433                       # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses::0                  835612                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                    6073                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              841685                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
+system.l2c.demand_hits::0                      708536                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                        6049                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  714585                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.152075                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.003952                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.156027                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    127076                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        24                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                127100                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.occ_%::0                          0.072507                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.478199                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  4751.792305                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31339.221407                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                 835612                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                   6073                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             841685                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.l2c.overall_hits::0                     708536                       # number of overall hits
+system.l2c.overall_hits::1                       6049                       # number of overall hits
+system.l2c.overall_hits::total                 714585                       # number of overall hits
+system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.152075                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.003952                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.156027                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   127076                       # number of overall misses
+system.l2c.overall_misses::1                       24                       # number of overall misses
+system.l2c.overall_misses::total               127100                       # number of overall misses
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.replacements                         95922                       # number of replacements
+system.l2c.sampled_refs                        125830                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                     36091.013712                       # Cycle average of tags in use
+system.l2c.total_refs                          866394                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                           90126                       # number of writebacks
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 53b01d583..586cb6b73 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 55ac85829..c7f419728 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -1,9 +1,7 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=LinuxArmSystem
@@ -11,20 +9,13 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
 boot_cpu_frequency=500
 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+kernel=/dist/m5/system/binaries/vmlinux.arm
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.bridge]
 type=Bridge
@@ -164,7 +155,7 @@ type=ExeTracer
 
 [system.diskmem]
 type=PhysicalMemory
-file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/ael-arm.ext2
+file=/dist/m5/system/disks/ael-arm.ext2
 latency=30000
 latency_var=0
 null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index 8914d507c..e76a50eec 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -1,5 +1,45 @@
-fatal: Could not load kernel file /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
- @ cycle 0
-[System:build/ARM_FS/sim/system.cc, line 118]
-Memory Usage: 210184 KBytes
-For more information see: http://www.m5sim.org/fatal/406aceb6
+warn: Sockets disabled, not accepting terminal connections
+For more information see: http://www.m5sim.org/warn/8742226b
+warn: Sockets disabled, not accepting gdb connections
+For more information see: http://www.m5sim.org/warn/d946bea6
+warn: The clidr register always reports 0 caches.
+For more information see: http://www.m5sim.org/warn/23a3c326
+warn: The csselr register isn't implemented.
+For more information see: http://www.m5sim.org/warn/c0c486b8
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: The ccsidr register isn't implemented and always reads as 0.
+For more information see: http://www.m5sim.org/warn/2c4acb9c
+warn: 	instruction 'mcr dccimvac' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr dccmvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr icimvau' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
+For more information see: http://www.m5sim.org/warn/7998f2ea
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Complete acc isn't called on normal stores in O3.
+For more information see: http://www.m5sim.org/warn/138d8573
+warn: Need to flush all TLBs in MP
+For more information see: http://www.m5sim.org/warn/6cccf999
+warn: 	instruction 'mcr bpiall' unimplemented
+For more information see: http://www.m5sim.org/warn/21b09adb
+hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 2dd6d32f6..8382cb48d 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -5,10 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:34:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 15:35:03
-M5 executing on svnxelk05
+M5 compiled Jan 17 2011 18:36:49
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 18:36:52
+M5 executing on zizzer
 command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 114721074000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index e69de29bb..157177a6b 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -0,0 +1,483 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                1461109                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 340352                       # Number of bytes of host memory used
+host_seconds                                    34.61                       # Real time elapsed on the host
+host_tick_rate                             3314430509                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                    50572425                       # Number of instructions simulated
+sim_seconds                                  0.114721                       # Number of seconds simulated
+sim_ticks                                114721074000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0       100214                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       100214                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency          inf                       # average LoadLockedReq mshr uncacheable latency
+system.cpu.dcache.LoadLockedReq_hits::0         95014                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        95014                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency     78765000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0     0.051889                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0         5200                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total         5200                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency     63165000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.051889                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses         5200                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency    310267000                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_accesses::0         7824780                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      7824780                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_hits::0             7588163                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7588163                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     3738156500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0       0.030239                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0            236617                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        236617                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3028228000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.030239                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses          236617                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency  38190415500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0       100213                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       100213                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0         100213                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       100213                       # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0        6671860                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6671860                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_hits::0            6499787                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6499787                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    7026784000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0      0.025791                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0           172073                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       172073                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   6510516500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.025791                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         172073                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency    926046500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                  34.660375                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses::0         14496640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     14496640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 26340.112310                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0             14087950                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         14087950                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     10764940500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0        0.028192                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses::0             408690                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         408690                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   9538744500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0     0.028192                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           408690                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.occ_%::0                   0.994530                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0            509.199113                       # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0        14496640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     14496640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 26340.112310                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits::0            14087950                       # number of overall hits
+system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::total        14087950                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    10764940500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0       0.028192                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses::0            408690                       # number of overall misses
+system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::total        408690                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   9538744500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0     0.028192                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          408690                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency  39116462000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements                 411628                       # number of replacements
+system.cpu.dcache.sampled_refs                 412140                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                509.199113                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14284927                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              658097000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   382676                       # number of writebacks
+system.cpu.dtb.accesses                      15524935                       # DTB accesses
+system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.dtb.flush_entries                     2199                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.dtb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.dtb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.hits                          15519414                       # DTB hits
+system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
+system.cpu.dtb.inst_hits                            0                       # ITB inst hits
+system.cpu.dtb.inst_misses                          0                       # ITB inst misses
+system.cpu.dtb.misses                            5521                       # DTB misses
+system.cpu.dtb.perms_faults                       255                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.prefetch_faults                    756                       # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses                  8740303                       # DTB read accesses
+system.cpu.dtb.read_hits                      8735762                       # DTB read hits
+system.cpu.dtb.read_misses                       4541                       # DTB read misses
+system.cpu.dtb.write_accesses                 6784632                       # DTB write accesses
+system.cpu.dtb.write_hits                     6783652                       # DTB write hits
+system.cpu.dtb.write_misses                       980                       # DTB write misses
+system.cpu.icache.ReadReq_accesses::0        41543801                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41543801                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_hits::0            41110405                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41110405                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency     6414604000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0       0.010432                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0            433396                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        433396                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency   5113853000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0     0.010432                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          433396                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable_latency    349111000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                  94.856667                       # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses::0         41543801                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41543801                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14800.791885                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843                       # average overall mshr miss latency
+system.cpu.icache.demand_hits::0             41110405                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41110405                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency      6414604000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0        0.010432                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
+system.cpu.icache.demand_misses::0             433396                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         433396                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency   5113853000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0     0.010432                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           433396                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.occ_%::0                   0.945788                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0            484.243503                       # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0        41543801                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41543801                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14800.791885                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits::0            41110405                       # number of overall hits
+system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::total        41110405                       # number of overall hits
+system.cpu.icache.overall_miss_latency     6414604000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0       0.010432                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
+system.cpu.icache.overall_misses::0            433396                       # number of overall misses
+system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::total        433396                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency   5113853000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0     0.010432                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          433396                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency    349111000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements                 432883                       # number of replacements
+system.cpu.icache.sampled_refs                 433395                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                484.243503                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 41110405                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle            14253306000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                    33555                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                      41546620                       # DTB accesses
+system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
+system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
+system.cpu.itb.flush_entries                     1478                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
+system.cpu.itb.flush_tlb_asid                      40                       # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
+system.cpu.itb.flush_tlb_mva_asid               33670                       # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.hits                          41543801                       # DTB hits
+system.cpu.itb.inst_accesses                 41546620                       # ITB inst accesses
+system.cpu.itb.inst_hits                     41543801                       # ITB inst hits
+system.cpu.itb.inst_misses                       2819                       # ITB inst misses
+system.cpu.itb.misses                            2819                       # DTB misses
+system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
+system.cpu.itb.read_accesses                        0                       # DTB read accesses
+system.cpu.itb.read_hits                            0                       # DTB read hits
+system.cpu.itb.read_misses                          0                       # DTB read misses
+system.cpu.itb.write_accesses                       0                       # DTB write accesses
+system.cpu.itb.write_hits                           0                       # DTB write hits
+system.cpu.itb.write_misses                         0                       # DTB write misses
+system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
+system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                        229442148                       # number of cpu cycles simulated
+system.cpu.num_insts                         50572425                       # Number of instructions executed
+system.cpu.num_refs                          16289993                       # Number of memory references
+system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
+system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
+system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
+system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
+system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
+system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
+system.iocache.overall_hits::0                      0                       # number of overall hits
+system.iocache.overall_hits::1                      0                       # number of overall hits
+system.iocache.overall_hits::total                  0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
+system.iocache.overall_misses::0                    0                       # number of overall misses
+system.iocache.overall_misses::1                    0                       # number of overall misses
+system.iocache.overall_misses::total                0                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.replacements                         0                       # number of replacements
+system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                            0                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                           0                       # number of writebacks
+system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency          inf                       # average LoadLockedReq mshr uncacheable latency
+system.l2c.LoadLockedReq_mshr_uncacheable_latency    234160000                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.ReadExReq_accesses::0               170323                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           170323                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0        52000                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0                    62071                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                62071                       # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency          5629104000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0            0.635569                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0                 108252                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             108252                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     4330080000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0       0.635569                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses               108252                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0                 673101                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                   5652                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             678753                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0   52096.523258                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   28127657.142857                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 28179753.666115                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_hits::0                     654204                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                       5617                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                 659821                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency             984468000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0              0.028075                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.006192                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.034267                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0                    18897                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                       35                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                18932                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency        757280000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0         0.028127                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         3.349611                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     3.377737                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                  18932                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency  29199338000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses::0                1750                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1750                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0   660.126947                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0                      17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  17                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency            1144000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0           0.990286                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0                  1733                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1733                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency      69320000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0      0.990286                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_misses                1733                       # number of UpgradeReq MSHR misses
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_mshr_uncacheable_latency    739844000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0               416231                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           416231                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0                   416231                       # number of Writeback hits
+system.l2c.Writeback_hits::total               416231                       # number of Writeback hits
+system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.avg_refs                          6.975292                       # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.demand_accesses::0                  843424                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                    5652                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              849076                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0    52014.345374                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1       188959200                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 189011214.345374                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency         40000                       # average overall mshr miss latency
+system.l2c.demand_hits::0                      716275                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                        5617                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  721892                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency             6613572000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0               0.150753                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.006192                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.156946                       # miss rate for demand accesses
+system.l2c.demand_misses::0                    127149                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                        35                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                127184                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency        5087360000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0          0.150795                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1         22.502477                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total     22.653272                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  127184                       # number of demand (read+write) MSHR misses
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.l2c.occ_%::0                          0.086431                       # Average percentage of cache occupancy
+system.l2c.occ_%::1                          0.477933                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::0                  5664.361976                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                 31321.847814                       # Average occupied blocks per context
+system.l2c.overall_accesses::0                 843424                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                   5652                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             849076                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0   52014.345374                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1      188959200                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 189011214.345374                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_hits::0                     716275                       # number of overall hits
+system.l2c.overall_hits::1                       5617                       # number of overall hits
+system.l2c.overall_hits::total                 721892                       # number of overall hits
+system.l2c.overall_miss_latency            6613572000                       # number of overall miss cycles
+system.l2c.overall_miss_rate::0              0.150753                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.006192                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.156946                       # miss rate for overall accesses
+system.l2c.overall_misses::0                   127149                       # number of overall misses
+system.l2c.overall_misses::1                       35                       # number of overall misses
+system.l2c.overall_misses::total               127184                       # number of overall misses
+system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency       5087360000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0         0.150795                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1        22.502477                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total    22.653272                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 127184                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency  29939182000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.replacements                         94170                       # number of replacements
+system.l2c.sampled_refs                        125831                       # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse                     36986.209790                       # Cycle average of tags in use
+system.l2c.total_refs                          877708                       # Total number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.writebacks                           87626                       # number of writebacks
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 7fac8d69a..8b31e35e7 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=AtomicSimpleCPU
@@ -62,7 +53,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
index cc8a06323..d7e9fb267 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:49
-M5 executing on SC2B0617
+M5 compiled Nov  9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov  9 2010 22:11:58
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
index 4af51a06c..4b1bec9b7 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2546556                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 196060                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
-host_tick_rate                             1270042569                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2960881                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 193980                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
+host_tick_rate                             1478428114                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -43,24 +43,8 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           500032                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                     500032                       # Number of busy cycles
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                           500001                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_store_insts                      56350                       # Number of store instructions
+system.cpu.num_refs                            180793                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 219f2790f..380aa38da 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu membus physmem
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -162,7 +153,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
index 9cbd81ab7..35ea05083 100755
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:50
-M5 executing on SC2B0617
+M5 compiled Nov  9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov  9 2010 22:11:58
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
index d511dcb3b..8d21cdbb4 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1346028                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 203784                       # Number of bytes of host memory used
-host_seconds                                     0.37                       # Real time elapsed on the host
-host_tick_rate                             1958145928                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1193890                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 201748                       # Number of bytes of host memory used
+host_seconds                                     0.42                       # Real time elapsed on the host
+host_tick_rate                             1737027103                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000728                       # Number of seconds simulated
@@ -226,24 +226,8 @@ system.cpu.l2cache.warmup_cycle                     0                       # Cy
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                          1455858                       # number of cpu cycles simulated
-system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
-system.cpu.num_busy_cycles                    1455858                       # Number of busy cycles
-system.cpu.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu.num_fp_alu_accesses                     32                       # Number of float alu accesses
-system.cpu.num_fp_insts                            32                       # number of float instructions
-system.cpu.num_fp_register_reads                   32                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
-system.cpu.num_func_calls                       14357                       # number of times a function call or return occured
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                           500001                       # Number of instructions executed
-system.cpu.num_int_alu_accesses                474689                       # Number of integer alu accesses
-system.cpu.num_int_insts                       474689                       # number of integer instructions
-system.cpu.num_int_register_reads              654286                       # number of times the integer registers were read
-system.cpu.num_int_register_writes             371542                       # number of times the integer registers were written
-system.cpu.num_load_insts                      124443                       # Number of load instructions
-system.cpu.num_mem_refs                        180793                       # number of memory refs
-system.cpu.num_store_insts                      56350                       # Number of store instructions
+system.cpu.num_refs                            180793                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index f5bfa4cc2..f95ff0355 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -124,7 +115,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -236,7 +227,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -348,7 +339,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -460,7 +451,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index c3b5cc937..98d9eda34 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -7,6 +7,9 @@ For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
-stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 1af698feb..21b8e7313 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:36
-M5 executing on SC2B0617
+M5 compiled Nov  9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov  9 2010 22:11:58
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 2a7984fc0..81431004c 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2537706                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1129136                       # Number of bytes of host memory used
-host_seconds                                     0.79                       # Real time elapsed on the host
-host_tick_rate                              317111144                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2770469                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1126824                       # Number of bytes of host memory used
+host_seconds                                     0.72                       # Real time elapsed on the host
+host_tick_rate                              346193150                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
@@ -145,24 +145,8 @@ system.cpu0.itb.write_hits                          0                       # DT
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          500001                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.num_refs                           180793                       # Number of memory references
 system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -301,24 +285,8 @@ system.cpu1.itb.write_hits                          0                       # DT
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu1.num_insts                          500001                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu1.num_int_insts                      474689                       # number of integer instructions
-system.cpu1.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_mem_refs                       180793                       # number of memory refs
-system.cpu1.num_store_insts                     56350                       # Number of store instructions
+system.cpu1.num_refs                           180793                       # Number of memory references
 system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -457,24 +425,8 @@ system.cpu2.itb.write_hits                          0                       # DT
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu2.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu2.num_insts                          500001                       # Number of instructions executed
-system.cpu2.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu2.num_int_insts                      474689                       # number of integer instructions
-system.cpu2.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu2.num_load_insts                     124443                       # Number of load instructions
-system.cpu2.num_mem_refs                       180793                       # number of memory refs
-system.cpu2.num_store_insts                     56350                       # Number of store instructions
+system.cpu2.num_refs                           180793                       # Number of memory references
 system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_hits                124111                       # number of ReadReq hits
@@ -613,24 +565,8 @@ system.cpu3.itb.write_hits                          0                       # DT
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          500032                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
-system.cpu3.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu3.num_insts                          500001                       # Number of instructions executed
-system.cpu3.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu3.num_int_insts                      474689                       # number of integer instructions
-system.cpu3.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu3.num_load_insts                     124443                       # Number of load instructions
-system.cpu3.num_mem_refs                       180793                       # number of memory refs
-system.cpu3.num_store_insts                     56350                       # Number of store instructions
+system.cpu3.num_refs                           180793                       # Number of memory references
 system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index ce5f99ffa..a23113a37 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -121,7 +112,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -230,7 +221,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -339,7 +330,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
@@ -448,7 +439,7 @@ type=ExeTracer
 type=EioProcess
 chkpt=
 errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 input=None
 max_stack_size=67108864
 output=cout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 91a8229b7..98d9eda34 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -6,9 +6,9 @@ warn: Prefetch instrutions is Alpha do not do anything
 For more information see: http://www.m5sim.org/warn/3e0eccba
 hack: be nice to actually delete the event here
 
-gzip: 
 gzip: stdout: Broken pipe
-stdout: Broken pipe
+
+gzip: stdout: Broken pipe
 
 gzip: stdout: Broken pipe
 
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index c379f6bd9..09966aa49 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:50
-M5 executing on SC2B0617
+M5 compiled Nov  9 2010 10:38:04
+M5 revision f4362ffd810f+ 7737+ default tip
+M5 started Nov  9 2010 22:11:58
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index e14d3ac02..dbaf84851 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1272425                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 211636                       # Number of bytes of host memory used
-host_seconds                                     1.57                       # Real time elapsed on the host
-host_tick_rate                              463675704                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1961801                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 209312                       # Number of bytes of host memory used
+host_seconds                                     1.02                       # Real time elapsed on the host
+host_tick_rate                              714851017                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1999954                       # Number of instructions simulated
 sim_seconds                                  0.000729                       # Number of seconds simulated
@@ -163,24 +163,8 @@ system.cpu0.itb.write_hits                          0                       # DT
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts        38180                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu0.num_fp_insts                           32                       # number of float instructions
-system.cpu0.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu0.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          500001                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses               474689                       # Number of integer alu accesses
-system.cpu0.num_int_insts                      474689                       # number of integer instructions
-system.cpu0.num_int_register_reads             654286                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            371542                       # number of times the integer registers were written
-system.cpu0.num_load_insts                     124443                       # Number of load instructions
-system.cpu0.num_mem_refs                       180793                       # number of memory refs
-system.cpu0.num_store_insts                     56350                       # Number of store instructions
+system.cpu0.num_refs                           180793                       # Number of memory references
 system.cpu0.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses            124435                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309                       # average ReadReq miss latency
@@ -337,24 +321,8 @@ system.cpu1.itb.write_hits                          0                       # DT
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu1.num_fp_insts                           32                       # number of float instructions
-system.cpu1.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu1.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu1.num_insts                          499993                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses               474681                       # Number of integer alu accesses
-system.cpu1.num_int_insts                      474681                       # number of integer instructions
-system.cpu1.num_int_register_reads             654273                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            371536                       # number of times the integer registers were written
-system.cpu1.num_load_insts                     124443                       # Number of load instructions
-system.cpu1.num_mem_refs                       180792                       # number of memory refs
-system.cpu1.num_store_insts                     56349                       # Number of store instructions
+system.cpu1.num_refs                           180792                       # Number of memory references
 system.cpu1.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu2.dcache.ReadReq_accesses            124433                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086                       # average ReadReq miss latency
@@ -511,24 +479,8 @@ system.cpu2.itb.write_hits                          0                       # DT
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu2.num_conditional_control_insts        38179                       # number of instructions that are conditional controls
-system.cpu2.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu2.num_fp_insts                           32                       # number of float instructions
-system.cpu2.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu2.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu2.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu2.num_insts                          499982                       # Number of instructions executed
-system.cpu2.num_int_alu_accesses               474671                       # Number of integer alu accesses
-system.cpu2.num_int_insts                      474671                       # number of integer instructions
-system.cpu2.num_int_register_reads             654261                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            371526                       # number of times the integer registers were written
-system.cpu2.num_load_insts                     124440                       # Number of load instructions
-system.cpu2.num_mem_refs                       180789                       # number of memory refs
-system.cpu2.num_store_insts                     56349                       # Number of store instructions
+system.cpu2.num_refs                           180789                       # Number of memory references
 system.cpu2.workload.PROG:num_syscalls             18                       # Number of system calls
 system.cpu3.dcache.ReadReq_accesses            124431                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827                       # average ReadReq miss latency
@@ -685,24 +637,8 @@ system.cpu3.itb.write_hits                          0                       # DT
 system.cpu3.itb.write_misses                        0                       # DTB write misses
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.numCycles                         1457840                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.num_busy_cycles                   1457840                       # Number of busy cycles
-system.cpu3.num_conditional_control_insts        38178                       # number of instructions that are conditional controls
-system.cpu3.num_fp_alu_accesses                    32                       # Number of float alu accesses
-system.cpu3.num_fp_insts                           32                       # number of float instructions
-system.cpu3.num_fp_register_reads                  32                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                 16                       # number of times the floating registers were written
-system.cpu3.num_func_calls                      14357                       # number of times a function call or return occured
-system.cpu3.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu3.num_insts                          499978                       # Number of instructions executed
-system.cpu3.num_int_alu_accesses               474667                       # Number of integer alu accesses
-system.cpu3.num_int_insts                      474667                       # number of integer instructions
-system.cpu3.num_int_register_reads             654256                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            371523                       # number of times the integer registers were written
-system.cpu3.num_load_insts                     124438                       # Number of load instructions
-system.cpu3.num_mem_refs                       180787                       # number of memory refs
-system.cpu3.num_store_insts                     56349                       # Number of store instructions
+system.cpu3.num_refs                           180787                       # Number of memory references
 system.cpu3.workload.PROG:num_syscalls             18                       # Number of system calls
 system.l2c.ReadExReq_accesses::0                  139                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                  139                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 47b7c7e8d..17847f641 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=DerivO3CPU
@@ -452,7 +443,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 131d2523e..ac49cfc17 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:32
-M5 executing on SC2B0617
+M5 compiled Jan 17 2011 21:17:52
+M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
+M5 started Jan 17 2011 21:19:18
+M5 executing on zizzer
 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index a4b2391e7..1034fcecd 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 170840                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 216512                       # Number of bytes of host memory used
-host_seconds                                     6.75                       # Real time elapsed on the host
-host_tick_rate                               17403875                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 133732                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 214280                       # Number of bytes of host memory used
+host_seconds                                     8.62                       # Real time elapsed on the host
+host_tick_rate                               13623692                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                     1153323                       # Number of instructions simulated
 sim_seconds                                  0.000117                       # Number of seconds simulated
@@ -37,9 +37,6 @@ system.cpu0.commit.COM:committed_per_cycle::min_value            0
 system.cpu0.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.COM:committed_per_cycle::total       214839                       # Number of insts commited each cycle
 system.cpu0.commit.COM:count                   534547                       # Number of instructions committed
-system.cpu0.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu0.commit.COM:int_insts               359798                       # Number of committed integer instructions.
 system.cpu0.commit.COM:loads                   174318                       # Number of loads committed
 system.cpu0.commit.COM:membars                     84                       # Number of memory barriers committed
 system.cpu0.commit.COM:refs                    261983                       # Number of memory references committed
@@ -165,7 +162,6 @@ system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::total              216884                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
 system.cpu0.icache.ReadReq_accesses              5264                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_avg_miss_latency 39056.216931                       # average ReadReq miss latency
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency 37012.315271                       # average ReadReq mshr miss latency
@@ -265,8 +261,6 @@ system.cpu0.iew.lsq.thread.0.squashedStores         1081                       #
 system.cpu0.iew.memOrderViolationEvents            74                       # Number of memory order violations
 system.cpu0.iew.predictedNotTakenIncorrect          821                       # Number of branches that were predicted not taken incorrectly
 system.cpu0.iew.predictedTakenIncorrect           425                       # Number of branches that were predicted taken incorrectly
-system.cpu0.int_regfile_reads                  812944                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 365773                       # number of integer regfile writes
 system.cpu0.ipc                              1.907193                       # IPC: Instructions Per Cycle
 system.cpu0.ipc_total                        1.907193                       # IPC: Total IPC of All Threads
 system.cpu0.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -358,14 +352,6 @@ system.cpu0.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu0.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:issued_per_cycle::total       216884                       # Number of insts issued each cycle
 system.cpu0.iq.ISSUE:rate                    1.936032                       # Inst issue rate
-system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu0.iq.int_alu_accesses                455183                       # Number of integer alu accesses
-system.cpu0.iq.int_inst_queue_reads           1127113                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_wakeup_accesses       453412                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.int_inst_queue_writes           465644                       # Number of integer instruction queue writes
 system.cpu0.iq.iqInstsAdded                    456518                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu0.iq.iqInstsIssued                   454956                       # Number of instructions issued
 system.cpu0.iq.iqNonSpecInstsAdded                825                       # Number of non-speculative instructions added to the IQ
@@ -377,11 +363,7 @@ system.cpu0.memDep0.conflictingLoads            86252                       # Nu
 system.cpu0.memDep0.conflictingStores           86102                       # Number of conflicting stores.
 system.cpu0.memDep0.insertedLoads              176000                       # Number of loads inserted to the mem dependence unit.
 system.cpu0.memDep0.insertedStores              88746                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.misc_regfile_reads                 265411                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.numCycles                          234994                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.rename.RENAME:BlockCycles            1211                       # Number of cycles rename is blocking
 system.cpu0.rename.RENAME:CommittedMaps        361468                       # Number of HB maps that are committed
 system.cpu0.rename.RENAME:IQFullEvents              6                       # Number of times rename has blocked due to IQ full
@@ -394,13 +376,10 @@ system.cpu0.rename.RENAME:RunCycles            180641                       # Nu
 system.cpu0.rename.RENAME:SquashCycles           2062                       # Number of cycles rename is squashing
 system.cpu0.rename.RENAME:UnblockCycles           697                       # Number of cycles rename is unblocking
 system.cpu0.rename.RENAME:UndoneMaps            10322                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:int_rename_lookups      1089130                       # Number of integer rename lookups
 system.cpu0.rename.RENAME:serializeStallCycles        11540                       # count of cycles rename stalled for serializing inst
 system.cpu0.rename.RENAME:serializingInsts          809                       # count of serializing insts renamed
 system.cpu0.rename.RENAME:skidInsts              4202                       # count of insts added to the skid buffer
 system.cpu0.rename.RENAME:tempSerializingInsts          812                       # count of temporary serializing insts renamed
-system.cpu0.rob.rob_reads                      757548                       # The number of ROB reads
-system.cpu0.rob.rob_writes                    1090250                       # The number of ROB writes
 system.cpu0.timesIdled                            337                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
@@ -432,9 +411,6 @@ system.cpu1.commit.COM:committed_per_cycle::min_value            0
 system.cpu1.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.COM:committed_per_cycle::total       187667                       # Number of insts commited each cycle
 system.cpu1.commit.COM:count                   221435                       # Number of instructions committed
-system.cpu1.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu1.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu1.commit.COM:int_insts               150322                       # Number of committed integer instructions.
 system.cpu1.commit.COM:loads                    60856                       # Number of loads committed
 system.cpu1.commit.COM:membars                   9088                       # Number of memory barriers committed
 system.cpu1.commit.COM:refs                     87006                       # Number of memory references committed
@@ -560,7 +536,6 @@ system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::total              196087                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu1.icache.ReadReq_accesses             27242                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_avg_miss_latency 15144.329897                       # average ReadReq miss latency
 system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12327.702703                       # average ReadReq mshr miss latency
@@ -660,8 +635,6 @@ system.cpu1.iew.lsq.thread.0.squashedStores          732                       #
 system.cpu1.iew.memOrderViolationEvents            35                       # Number of memory order violations
 system.cpu1.iew.predictedNotTakenIncorrect          189                       # Number of branches that were predicted not taken incorrectly
 system.cpu1.iew.predictedTakenIncorrect          1010                       # Number of branches that were predicted taken incorrectly
-system.cpu1.int_regfile_reads                  321648                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 150288                       # number of integer regfile writes
 system.cpu1.ipc                              0.902137                       # IPC: Instructions Per Cycle
 system.cpu1.ipc_total                        0.902137                       # IPC: Total IPC of All Threads
 system.cpu1.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -753,14 +726,6 @@ system.cpu1.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu1.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:issued_per_cycle::total       196087                       # Number of insts issued each cycle
 system.cpu1.iq.ISSUE:rate                    0.970635                       # Inst issue rate
-system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu1.iq.int_alu_accesses                194246                       # Number of integer alu accesses
-system.cpu1.iq.int_inst_queue_reads            584396                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_wakeup_accesses       192754                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.int_inst_queue_writes           203505                       # Number of integer instruction queue writes
 system.cpu1.iq.iqInstsAdded                    186439                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu1.iq.iqInstsIssued                   194061                       # Number of instructions issued
 system.cpu1.iq.iqNonSpecInstsAdded              10484                       # Number of non-speculative instructions added to the IQ
@@ -772,11 +737,7 @@ system.cpu1.memDep0.conflictingLoads            31889                       # Nu
 system.cpu1.memDep0.conflictingStores           22377                       # Number of conflicting stores.
 system.cpu1.memDep0.insertedLoads               62331                       # Number of loads inserted to the mem dependence unit.
 system.cpu1.memDep0.insertedStores              26882                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.misc_regfile_reads                  89554                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu1.numCycles                          199932                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.rename.RENAME:BlockCycles            9891                       # Number of cycles rename is blocking
 system.cpu1.rename.RENAME:CommittedMaps        147748                       # Number of HB maps that are committed
 system.cpu1.rename.RENAME:IQFullEvents             48                       # Number of times rename has blocked due to IQ full
@@ -789,13 +750,10 @@ system.cpu1.rename.RENAME:RunCycles             92302                       # Nu
 system.cpu1.rename.RENAME:SquashCycles           1784                       # Number of cycles rename is squashing
 system.cpu1.rename.RENAME:UnblockCycles           562                       # Number of cycles rename is unblocking
 system.cpu1.rename.RENAME:UndoneMaps             8137                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:int_rename_lookups       422855                       # Number of integer rename lookups
 system.cpu1.rename.RENAME:serializeStallCycles        13360                       # count of cycles rename stalled for serializing inst
 system.cpu1.rename.RENAME:serializingInsts          970                       # count of serializing insts renamed
 system.cpu1.rename.RENAME:skidInsts              2743                       # count of insts added to the skid buffer
 system.cpu1.rename.RENAME:tempSerializingInsts         1022                       # count of temporary serializing insts renamed
-system.cpu1.rob.rob_reads                      416274                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     461144                       # The number of ROB writes
 system.cpu1.timesIdled                            297                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu2.BPredUnit.BTBHits                   58194                       # Number of BTB hits
@@ -826,9 +784,6 @@ system.cpu2.commit.COM:committed_per_cycle::min_value            0
 system.cpu2.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu2.commit.COM:committed_per_cycle::total       185916                       # Number of insts commited each cycle
 system.cpu2.commit.COM:count                   330777                       # Number of instructions committed
-system.cpu2.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu2.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu2.commit.COM:int_insts               226484                       # Number of committed integer instructions.
 system.cpu2.commit.COM:loads                    98945                       # Number of loads committed
 system.cpu2.commit.COM:membars                   4183                       # Number of memory barriers committed
 system.cpu2.commit.COM:refs                    146579                       # Number of memory references committed
@@ -954,7 +909,6 @@ system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::total              194280                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu2.icache.ReadReq_accesses             17027                       # number of ReadReq accesses(hits+misses)
 system.cpu2.icache.ReadReq_avg_miss_latency 21608.921162                       # average ReadReq miss latency
 system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18272.935780                       # average ReadReq mshr miss latency
@@ -1054,8 +1008,6 @@ system.cpu2.iew.lsq.thread.0.squashedStores          766                       #
 system.cpu2.iew.memOrderViolationEvents            35                       # Number of memory order violations
 system.cpu2.iew.predictedNotTakenIncorrect          199                       # Number of branches that were predicted not taken incorrectly
 system.cpu2.iew.predictedTakenIncorrect           991                       # Number of branches that were predicted taken incorrectly
-system.cpu2.int_regfile_reads                  500577                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 231428                       # number of integer regfile writes
 system.cpu2.ipc                              1.392607                       # IPC: Instructions Per Cycle
 system.cpu2.ipc_total                        1.392607                       # IPC: Total IPC of All Threads
 system.cpu2.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -1147,14 +1099,6 @@ system.cpu2.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu2.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu2.iq.ISSUE:issued_per_cycle::total       194280                       # Number of insts issued each cycle
 system.cpu2.iq.ISSUE:rate                    1.437167                       # Inst issue rate
-system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu2.iq.int_alu_accesses                287114                       # Number of integer alu accesses
-system.cpu2.iq.int_inst_queue_reads            768311                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_wakeup_accesses       285574                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.int_inst_queue_writes           296099                       # Number of integer instruction queue writes
 system.cpu2.iq.iqInstsAdded                    284164                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu2.iq.iqInstsIssued                   286916                       # Number of instructions issued
 system.cpu2.iq.iqNonSpecInstsAdded               5428                       # Number of non-speculative instructions added to the IQ
@@ -1166,11 +1110,7 @@ system.cpu2.memDep0.conflictingLoads            48437                       # Nu
 system.cpu2.memDep0.conflictingStores           43927                       # Number of conflicting stores.
 system.cpu2.memDep0.insertedLoads              100435                       # Number of loads inserted to the mem dependence unit.
 system.cpu2.memDep0.insertedStores              48400                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.misc_regfile_reads                 149234                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu2.numCycles                          199640                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.rename.RENAME:BlockCycles            5634                       # Number of cycles rename is blocking
 system.cpu2.rename.RENAME:CommittedMaps        228819                       # Number of HB maps that are committed
 system.cpu2.rename.RENAME:IQFullEvents             67                       # Number of times rename has blocked due to IQ full
@@ -1183,13 +1123,10 @@ system.cpu2.rename.RENAME:RunCycles            120203                       # Nu
 system.cpu2.rename.RENAME:SquashCycles           1740                       # Number of cycles rename is squashing
 system.cpu2.rename.RENAME:UnblockCycles           620                       # Number of cycles rename is unblocking
 system.cpu2.rename.RENAME:UndoneMaps             8187                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.RENAME:int_rename_lookups       661216                       # Number of integer rename lookups
 system.cpu2.rename.RENAME:serializeStallCycles        12791                       # count of cycles rename stalled for serializing inst
 system.cpu2.rename.RENAME:serializingInsts          940                       # count of serializing insts renamed
 system.cpu2.rename.RENAME:skidInsts              2775                       # count of insts added to the skid buffer
 system.cpu2.rename.RENAME:tempSerializingInsts          995                       # count of temporary serializing insts renamed
-system.cpu2.rob.rob_reads                      523697                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     679481                       # The number of ROB writes
 system.cpu2.timesIdled                            296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu3.BPredUnit.BTBHits                   53101                       # Number of BTB hits
@@ -1220,9 +1157,6 @@ system.cpu3.commit.COM:committed_per_cycle::min_value            0
 system.cpu3.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu3.commit.COM:committed_per_cycle::total       187872                       # Number of insts commited each cycle
 system.cpu3.commit.COM:count                   296008                       # Number of instructions committed
-system.cpu3.commit.COM:fp_insts                     0                       # Number of committed floating point instructions.
-system.cpu3.commit.COM:function_calls               0                       # Number of function calls committed.
-system.cpu3.commit.COM:int_insts               202157                       # Number of committed integer instructions.
 system.cpu3.commit.COM:loads                    86777                       # Number of loads committed
 system.cpu3.commit.COM:membars                   5899                       # Number of memory barriers committed
 system.cpu3.commit.COM:refs                    127476                       # Number of memory references committed
@@ -1348,7 +1282,6 @@ system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Nu
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::total              196296                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
 system.cpu3.icache.ReadReq_accesses             20572                       # number of ReadReq accesses(hits+misses)
 system.cpu3.icache.ReadReq_avg_miss_latency 14541.928721                       # average ReadReq miss latency
 system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11822.799097                       # average ReadReq mshr miss latency
@@ -1448,8 +1381,6 @@ system.cpu3.iew.lsq.thread.0.squashedStores          782                       #
 system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
 system.cpu3.iew.predictedNotTakenIncorrect          194                       # Number of branches that were predicted not taken incorrectly
 system.cpu3.iew.predictedTakenIncorrect          1002                       # Number of branches that were predicted taken incorrectly
-system.cpu3.int_regfile_reads                  443221                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 205359                       # number of integer regfile writes
 system.cpu3.ipc                              1.237689                       # IPC: Instructions Per Cycle
 system.cpu3.ipc_total                        1.237689                       # IPC: Total IPC of All Threads
 system.cpu3.iq.ISSUE:FU_type_0::No_OpClass            0      0.00%      0.00% # Type of FU issued
@@ -1541,14 +1472,6 @@ system.cpu3.iq.ISSUE:issued_per_cycle::min_value            0
 system.cpu3.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu3.iq.ISSUE:issued_per_cycle::total       196296                       # Number of insts issued each cycle
 system.cpu3.iq.ISSUE:rate                    1.290801                       # Inst issue rate
-system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
-system.cpu3.iq.int_alu_accesses                257546                       # Number of integer alu accesses
-system.cpu3.iq.int_inst_queue_reads            711191                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_wakeup_accesses       256019                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.int_inst_queue_writes           266954                       # Number of integer instruction queue writes
 system.cpu3.iq.iqInstsAdded                    253019                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu3.iq.iqInstsIssued                   257347                       # Number of instructions issued
 system.cpu3.iq.iqNonSpecInstsAdded               7241                       # Number of non-speculative instructions added to the IQ
@@ -1560,11 +1483,7 @@ system.cpu3.memDep0.conflictingLoads            43278                       # Nu
 system.cpu3.memDep0.conflictingStores           36990                       # Number of conflicting stores.
 system.cpu3.memDep0.insertedLoads               88323                       # Number of loads inserted to the mem dependence unit.
 system.cpu3.memDep0.insertedStores              41481                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.misc_regfile_reads                 130106                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu3.numCycles                          199370                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.rename.RENAME:BlockCycles            7226                       # Number of cycles rename is blocking
 system.cpu3.rename.RENAME:CommittedMaps        202775                       # Number of HB maps that are committed
 system.cpu3.rename.RENAME:IQFullEvents             58                       # Number of times rename has blocked due to IQ full
@@ -1577,13 +1496,10 @@ system.cpu3.rename.RENAME:RunCycles            111693                       # Nu
 system.cpu3.rename.RENAME:SquashCycles           1792                       # Number of cycles rename is squashing
 system.cpu3.rename.RENAME:UnblockCycles           593                       # Number of cycles rename is unblocking
 system.cpu3.rename.RENAME:UndoneMaps             8286                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.RENAME:int_rename_lookups       585183                       # Number of integer rename lookups
 system.cpu3.rename.RENAME:serializeStallCycles        13124                       # count of cycles rename stalled for serializing inst
 system.cpu3.rename.RENAME:serializingInsts          957                       # count of serializing insts renamed
 system.cpu3.rename.RENAME:skidInsts              2808                       # count of insts added to the skid buffer
 system.cpu3.rename.RENAME:tempSerializingInsts         1009                       # count of temporary serializing insts renamed
-system.cpu3.rob.rob_reads                      491204                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     610604                       # The number of ROB writes
 system.cpu3.timesIdled                            290                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 5787a6d74..e833b46ac 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=atomic
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=AtomicSimpleCPU
@@ -128,7 +119,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index 576190411..9ac3c5e14 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:32
-M5 executing on SC2B0617
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:04:32
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 0b9d84f24..0544aca9b 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1942923                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1130976                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
-host_tick_rate                              251405159                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1027581                       # Simulator instruction rate (inst/s)
+host_mem_usage                                1133204                       # Number of bytes of host memory used
+host_seconds                                     0.66                       # Real time elapsed on the host
+host_tick_rate                              133016942                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      677340                       # Number of instructions simulated
 sim_seconds                                  0.000088                       # Number of seconds simulated
@@ -117,24 +117,8 @@ system.cpu0.icache.writebacks                       0                       # nu
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles                    175428                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          175339                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses               120388                       # Number of integer alu accesses
-system.cpu0.num_int_insts                      120388                       # number of integer instructions
-system.cpu0.num_int_register_reads             349308                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            121996                       # number of times the integer registers were written
-system.cpu0.num_load_insts                      54592                       # Number of load instructions
-system.cpu0.num_mem_refs                        82398                       # number of memory refs
-system.cpu0.num_store_insts                     27806                       # Number of store instructions
+system.cpu0.num_refs                            82398                       # Number of memory references
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             40644                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_hits                 40468                       # number of ReadReq hits
@@ -245,24 +229,8 @@ system.cpu1.icache.writebacks                       0                       # nu
 system.cpu1.idle_fraction                    0.045506                       # Percentage of idle cycles
 system.cpu1.not_idle_fraction                0.954494                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          173308                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              165421.425557                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles               7886.574443                       # Number of idle cycles
 system.cpu1.num_insts                          167398                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses               109926                       # Number of integer alu accesses
-system.cpu1.num_int_insts                      109926                       # number of integer instructions
-system.cpu1.num_int_register_reads             270038                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes            100721                       # number of times the integer registers were written
-system.cpu1.num_load_insts                      40652                       # Number of load instructions
-system.cpu1.num_mem_refs                        53394                       # number of memory refs
-system.cpu1.num_store_insts                     12742                       # Number of store instructions
+system.cpu1.num_refs                            53394                       # Number of memory references
 system.cpu2.dcache.ReadReq_accesses             42354                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_hits                 42192                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_miss_rate         0.003825                       # miss rate for ReadReq accesses
@@ -372,24 +340,8 @@ system.cpu2.icache.writebacks                       0                       # nu
 system.cpu2.idle_fraction                    0.045871                       # Percentage of idle cycles
 system.cpu2.not_idle_fraction                0.954129                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          173308                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.num_busy_cycles              165358.198620                       # Number of busy cycles
-system.cpu2.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu2.num_idle_cycles               7949.801380                       # Number of idle cycles
 system.cpu2.num_insts                          167334                       # Number of instructions executed
-system.cpu2.num_int_alu_accesses               113333                       # Number of integer alu accesses
-system.cpu2.num_int_insts                      113333                       # number of integer instructions
-system.cpu2.num_int_register_reads             290613                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            109308                       # number of times the integer registers were written
-system.cpu2.num_load_insts                      42362                       # Number of load instructions
-system.cpu2.num_mem_refs                        58537                       # number of memory refs
-system.cpu2.num_store_insts                     16175                       # Number of store instructions
+system.cpu2.num_refs                            58537                       # Number of memory references
 system.cpu3.dcache.ReadReq_accesses             41458                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_hits                 41299                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_miss_rate         0.003835                       # miss rate for ReadReq accesses
@@ -499,24 +451,8 @@ system.cpu3.icache.writebacks                       0                       # nu
 system.cpu3.idle_fraction                    0.046241                       # Percentage of idle cycles
 system.cpu3.not_idle_fraction                0.953759                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          173307                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.num_busy_cycles              165293.030003                       # Number of busy cycles
-system.cpu3.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu3.num_idle_cycles               8013.969997                       # Number of idle cycles
 system.cpu3.num_insts                          167269                       # Number of instructions executed
-system.cpu3.num_int_alu_accesses               111554                       # Number of integer alu accesses
-system.cpu3.num_int_insts                      111554                       # number of integer instructions
-system.cpu3.num_int_register_reads             280060                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            104916                       # number of times the integer registers were written
-system.cpu3.num_load_insts                      41466                       # Number of load instructions
-system.cpu3.num_mem_refs                        55900                       # number of memory refs
-system.cpu3.num_store_insts                     14434                       # Number of store instructions
+system.cpu3.num_refs                            55900                       # Number of memory references
 system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 2a4e57f6c..276044213 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=TimingSimpleCPU
@@ -125,7 +116,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index a6189c8f0..cae225db3 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:47:32
-M5 executing on SC2B0617
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:45
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 7703b45f1..a2bed5a68 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1041704                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 213476                       # Number of bytes of host memory used
-host_seconds                                     0.62                       # Real time elapsed on the host
-host_tick_rate                              419868162                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 583465                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 215700                       # Number of bytes of host memory used
+host_seconds                                     1.12                       # Real time elapsed on the host
+host_tick_rate                              235218525                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      650423                       # Number of instructions simulated
 sim_seconds                                  0.000262                       # Number of seconds simulated
@@ -141,24 +141,8 @@ system.cpu0.icache.writebacks                       0                       # nu
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.numCycles                          524590                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.num_busy_cycles                    524590                       # Number of busy cycles
-system.cpu0.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
 system.cpu0.num_insts                          158353                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses               109064                       # Number of integer alu accesses
-system.cpu0.num_int_insts                      109064                       # number of integer instructions
-system.cpu0.num_int_register_reads             315336                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            110671                       # number of times the integer registers were written
-system.cpu0.num_load_insts                      48930                       # Number of load instructions
-system.cpu0.num_mem_refs                        73905                       # number of memory refs
-system.cpu0.num_store_insts                     24975                       # Number of store instructions
+system.cpu0.num_refs                            73905                       # Number of memory references
 system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
 system.cpu1.dcache.ReadReq_accesses             38632                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667                       # average ReadReq miss latency
@@ -295,24 +279,8 @@ system.cpu1.icache.writebacks                       0                       # nu
 system.cpu1.idle_fraction                    0.130715                       # Percentage of idle cycles
 system.cpu1.not_idle_fraction                0.869285                       # Percentage of non-idle cycles
 system.cpu1.numCycles                          513666                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.num_busy_cycles              446521.933500                       # Number of busy cycles
-system.cpu1.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_idle_cycles              67144.066500                       # Number of idle cycles
 system.cpu1.num_insts                          168364                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses               105930                       # Number of integer alu accesses
-system.cpu1.num_int_insts                      105930                       # number of integer instructions
-system.cpu1.num_int_register_reads             244134                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes             89763                       # number of times the integer registers were written
-system.cpu1.num_load_insts                      38640                       # Number of load instructions
-system.cpu1.num_mem_refs                        46919                       # number of memory refs
-system.cpu1.num_store_insts                      8279                       # Number of store instructions
+system.cpu1.num_refs                            46919                       # Number of memory references
 system.cpu2.dcache.ReadReq_accesses             40867                       # number of ReadReq accesses(hits+misses)
 system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484                       # average ReadReq miss latency
 system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484                       # average ReadReq mshr miss latency
@@ -448,24 +416,8 @@ system.cpu2.icache.writebacks                       0                       # nu
 system.cpu2.idle_fraction                    0.131215                       # Percentage of idle cycles
 system.cpu2.not_idle_fraction                0.868785                       # Percentage of non-idle cycles
 system.cpu2.numCycles                          513662                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.num_busy_cycles              446261.914218                       # Number of busy cycles
-system.cpu2.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu2.num_fp_insts                            0                       # number of float instructions
-system.cpu2.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu2.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu2.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu2.num_idle_cycles              67400.085782                       # Number of idle cycles
 system.cpu2.num_insts                          161536                       # Number of instructions executed
-system.cpu2.num_int_alu_accesses               110351                       # Number of integer alu accesses
-system.cpu2.num_int_insts                      110351                       # number of integer instructions
-system.cpu2.num_int_register_reads             284309                       # number of times the integer registers were read
-system.cpu2.num_int_register_writes            107647                       # number of times the integer registers were written
-system.cpu2.num_load_insts                      40875                       # Number of load instructions
-system.cpu2.num_mem_refs                        56961                       # number of memory refs
-system.cpu2.num_store_insts                     16086                       # Number of store instructions
+system.cpu2.num_refs                            56961                       # Number of memory references
 system.cpu3.dcache.ReadReq_accesses             40736                       # number of ReadReq accesses(hits+misses)
 system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615                       # average ReadReq miss latency
 system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615                       # average ReadReq mshr miss latency
@@ -601,24 +553,8 @@ system.cpu3.icache.writebacks                       0                       # nu
 system.cpu3.idle_fraction                    0.131691                       # Percentage of idle cycles
 system.cpu3.not_idle_fraction                0.868309                       # Percentage of non-idle cycles
 system.cpu3.numCycles                          513670                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.num_busy_cycles              446024.068564                       # Number of busy cycles
-system.cpu3.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu3.num_fp_insts                            0                       # number of float instructions
-system.cpu3.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu3.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu3.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu3.num_idle_cycles              67645.931436                       # Number of idle cycles
 system.cpu3.num_insts                          162170                       # Number of instructions executed
-system.cpu3.num_int_alu_accesses               110096                       # Number of integer alu accesses
-system.cpu3.num_int_insts                      110096                       # number of integer instructions
-system.cpu3.num_int_register_reads             281520                       # number of times the integer registers were read
-system.cpu3.num_int_register_writes            106379                       # number of times the integer registers were written
-system.cpu3.num_load_insts                      40744                       # Number of load instructions
-system.cpu3.num_mem_refs                        56264                       # number of memory refs
-system.cpu3.num_store_insts                     15520                       # Number of store instructions
+system.cpu3.num_refs                            56264                       # Number of memory references
 system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
index 83237c30c..75b04f0f3 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -501,7 +492,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
@@ -514,7 +504,6 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.L1IcacheMemory
@@ -527,7 +516,6 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.L1IcacheMemory
@@ -540,7 +528,6 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.L1IcacheMemory
@@ -553,7 +540,6 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.L1IcacheMemory
@@ -566,7 +552,6 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.L1IcacheMemory
@@ -579,7 +564,6 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.L1IcacheMemory
@@ -592,7 +576,6 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.L1IcacheMemory
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index ad8a03637..307193acf 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Dec/01/2010 10:30:07
+Real time: Jan/13/2011 22:37:51
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 46
-Elapsed_time_in_minutes: 0.766667
-Elapsed_time_in_hours: 0.0127778
-Elapsed_time_in_days: 0.000532407
+Elapsed_time_in_seconds: 83
+Elapsed_time_in_minutes: 1.38333
+Elapsed_time_in_hours: 0.0230556
+Elapsed_time_in_days: 0.000960648
 
-Virtual_time_in_seconds: 45.19
-Virtual_time_in_minutes: 0.753167
-Virtual_time_in_hours:   0.0125528
-Virtual_time_in_days:    0.000523032
+Virtual_time_in_seconds: 82.77
+Virtual_time_in_minutes: 1.3795
+Virtual_time_in_hours:   0.0229917
+Virtual_time_in_days:    0.000957986
 
 Ruby_current_time: 3750455
 Ruby_start_time: 0
 Ruby_cycles: 3750455
 
-mbytes_resident: 34.6367
-mbytes_total: 335.688
-resident_ratio: 0.103205
+mbytes_resident: 19.9609
+mbytes_total: 283.734
+resident_ratio: 0.0703783
 
 ruby_cycles_executed: [ 3750456 3750456 3750456 3750456 3750456 3750456 3750456 3750456 ]
 
@@ -116,12 +116,12 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603
 Resource Usage
 --------------
 page_size: 4096
-user_time: 44
+user_time: 82
 system_time: 0
-page_reclaims: 10049
+page_reclaims: 5799
 page_faults: 0
 swaps: 0
-block_inputs: 16
+block_inputs: 0
 block_outputs: 0
 
 Network Stats
@@ -424,6 +424,13 @@ E_I  Ifetch [0 0 0 0 0 0 0 0 ] 0
 E_I  Store [0 0 0 0 0 0 0 0 ] 0
 E_I  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 
+SINK_WB_ACK  Load [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  Store [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  Inv [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  WB_Ack [0 0 0 0 0 0 0 0 ] 0
+
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
   system.l1_cntrl1.L1IcacheMemory_total_misses: 0
   system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
index 8e15caa61..e36729355 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
@@ -1,15 +1,74 @@
-system.cpu1: completed 10000 read accesses @4267815
-system.cpu0: completed 10000 read accesses @4386665
-system.cpu7: completed 10000 read accesses @4430875
-system.cpu5: completed 10000 read accesses @4607545
-system.cpu2: completed 10000 read accesses @4619185
-system.cpu6: completed 10000 read accesses @4647575
-system.cpu4: completed 10000 read accesses @4703325
-system.cpu3: completed 10000 read accesses @4708885
-panic: Possible Deadlock detected. Aborting!
-version: 3 request.paddr: 0x10c0c3 m_readRequestTable: 8 current time: 5500000 issue_time: 4999950 difference: 500050
- @ cycle 5500000
-[wakeup:build/ALPHA_SE_MESI_CMP_directory/mem/ruby/system/Sequencer.cc, line 107]
-Memory Usage: 346324 KBytes
-For more information see: http://www.m5sim.org/panic/ee664ab2
-Program aborted at cycle 5500000
+system.cpu0: completed 10000 read accesses @371396
+system.cpu2: completed 10000 read accesses @374647
+system.cpu7: completed 10000 read accesses @377314
+system.cpu1: completed 10000 read accesses @379478
+system.cpu3: completed 10000 read accesses @380787
+system.cpu5: completed 10000 read accesses @386046
+system.cpu4: completed 10000 read accesses @386470
+system.cpu6: completed 10000 read accesses @394077
+system.cpu0: completed 20000 read accesses @748308
+system.cpu2: completed 20000 read accesses @750148
+system.cpu1: completed 20000 read accesses @752701
+system.cpu3: completed 20000 read accesses @761044
+system.cpu5: completed 20000 read accesses @762156
+system.cpu4: completed 20000 read accesses @766351
+system.cpu6: completed 20000 read accesses @775961
+system.cpu7: completed 20000 read accesses @776472
+system.cpu2: completed 30000 read accesses @1125160
+system.cpu1: completed 30000 read accesses @1125369
+system.cpu0: completed 30000 read accesses @1130636
+system.cpu3: completed 30000 read accesses @1139985
+system.cpu5: completed 30000 read accesses @1141453
+system.cpu4: completed 30000 read accesses @1142264
+system.cpu6: completed 30000 read accesses @1154957
+system.cpu7: completed 30000 read accesses @1163543
+system.cpu2: completed 40000 read accesses @1501376
+system.cpu1: completed 40000 read accesses @1506717
+system.cpu0: completed 40000 read accesses @1507617
+system.cpu3: completed 40000 read accesses @1521033
+system.cpu4: completed 40000 read accesses @1523666
+system.cpu5: completed 40000 read accesses @1527373
+system.cpu6: completed 40000 read accesses @1547890
+system.cpu7: completed 40000 read accesses @1551332
+system.cpu2: completed 50000 read accesses @1879261
+system.cpu0: completed 50000 read accesses @1879360
+system.cpu1: completed 50000 read accesses @1885794
+system.cpu3: completed 50000 read accesses @1900931
+system.cpu4: completed 50000 read accesses @1902181
+system.cpu5: completed 50000 read accesses @1910820
+system.cpu6: completed 50000 read accesses @1931247
+system.cpu7: completed 50000 read accesses @1940656
+system.cpu0: completed 60000 read accesses @2246405
+system.cpu1: completed 60000 read accesses @2255112
+system.cpu2: completed 60000 read accesses @2258276
+system.cpu3: completed 60000 read accesses @2284120
+system.cpu4: completed 60000 read accesses @2284604
+system.cpu5: completed 60000 read accesses @2293116
+system.cpu6: completed 60000 read accesses @2311203
+system.cpu7: completed 60000 read accesses @2336896
+system.cpu0: completed 70000 read accesses @2626542
+system.cpu1: completed 70000 read accesses @2633209
+system.cpu2: completed 70000 read accesses @2638509
+system.cpu4: completed 70000 read accesses @2659805
+system.cpu3: completed 70000 read accesses @2663605
+system.cpu5: completed 70000 read accesses @2671213
+system.cpu6: completed 70000 read accesses @2693680
+system.cpu7: completed 70000 read accesses @2725734
+system.cpu0: completed 80000 read accesses @2999116
+system.cpu1: completed 80000 read accesses @3008858
+system.cpu2: completed 80000 read accesses @3014566
+system.cpu3: completed 80000 read accesses @3028069
+system.cpu4: completed 80000 read accesses @3040014
+system.cpu5: completed 80000 read accesses @3055346
+system.cpu6: completed 80000 read accesses @3080851
+system.cpu7: completed 80000 read accesses @3115153
+system.cpu0: completed 90000 read accesses @3374370
+system.cpu1: completed 90000 read accesses @3384044
+system.cpu2: completed 90000 read accesses @3385035
+system.cpu3: completed 90000 read accesses @3412877
+system.cpu4: completed 90000 read accesses @3422171
+system.cpu5: completed 90000 read accesses @3435207
+system.cpu6: completed 90000 read accesses @3466955
+system.cpu7: completed 90000 read accesses @3499833
+system.cpu0: completed 100000 read accesses @3750455
+hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index 7de418081..edd524f60 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:58
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 15:13:09
-M5 executing on svnxelk05
+M5 compiled Jan 13 2011 22:36:25
+M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
+M5 started Jan 13 2011 22:36:28
+M5 executing on scamorza.cs.wisc.edu
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 3750455 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index e69de29bb..ce3cfcb57 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -0,0 +1,34 @@
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage                                 290548                       # Number of bytes of host memory used
+host_seconds                                    82.41                       # Real time elapsed on the host
+host_tick_rate                                  45509                       # Simulator tick rate (ticks/s)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+sim_seconds                                  0.003750                       # Number of seconds simulated
+sim_ticks                                     3750455                       # Number of ticks simulated
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          54108                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           99918                       # number of read accesses completed
+system.cpu1.num_writes                          53757                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           99521                       # number of read accesses completed
+system.cpu2.num_writes                          53948                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           98786                       # number of read accesses completed
+system.cpu3.num_writes                          53362                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                           98631                       # number of read accesses completed
+system.cpu4.num_writes                          52746                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                           98242                       # number of read accesses completed
+system.cpu5.num_writes                          52924                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           97407                       # number of read accesses completed
+system.cpu6.num_writes                          52658                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           96638                       # number of read accesses completed
+system.cpu7.num_writes                          51757                       # number of write accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index 2400b08fd..2086e11ae 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -469,9 +460,10 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
+children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -483,7 +475,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
@@ -496,7 +487,6 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.L1IcacheMemory
@@ -509,7 +499,6 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.L1IcacheMemory
@@ -522,7 +511,6 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.L1IcacheMemory
@@ -535,7 +523,6 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.L1IcacheMemory
@@ -548,7 +535,6 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.L1IcacheMemory
@@ -561,7 +547,6 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.L1IcacheMemory
@@ -574,7 +559,6 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.L1IcacheMemory
@@ -585,6 +569,14 @@ version=7
 physMemPort=system.physmem.port[7]
 port=system.cpu7.test
 
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index e38c477d8..f165c60b3 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:52:05
+Real time: Aug/20/2010 12:11:08
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 491
-Elapsed_time_in_minutes: 8.18333
-Elapsed_time_in_hours: 0.136389
-Elapsed_time_in_days: 0.00568287
+Elapsed_time_in_seconds: 30
+Elapsed_time_in_minutes: 0.5
+Elapsed_time_in_hours: 0.00833333
+Elapsed_time_in_days: 0.000347222
 
-Virtual_time_in_seconds: 491.75
-Virtual_time_in_minutes: 8.19583
-Virtual_time_in_hours:   0.136597
-Virtual_time_in_days:    0.00569155
+Virtual_time_in_seconds: 29.75
+Virtual_time_in_minutes: 0.495833
+Virtual_time_in_hours:   0.00826389
+Virtual_time_in_days:    0.000344329
 
-Ruby_current_time: 38939096
+Ruby_current_time: 3377485
 Ruby_start_time: 0
-Ruby_cycles: 38939096
+Ruby_cycles: 3377485
 
-mbytes_resident: 36.1992
-mbytes_total: 338.422
-resident_ratio: 0.106976
+mbytes_resident: 32.793
+mbytes_total: 333.84
+resident_ratio: 0.0982413
 
-ruby_cycles_executed: [ 38939097 38939097 38939097 38939097 38939097 38939097 38939097 38939097 ]
+ruby_cycles_executed: [ 3377486 3377486 3377486 3377486 3377486 3377486 3377486 3377486 ]
 
 Busy Controller Counts:
 L2Cache-0:0  
@@ -67,14 +67,14 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1227844 average: 15.9992 | standard deviation: 0.0898844 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1227724 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1222069 average: 1.94291 | standard deviation: 0.23202 | 0 69771 1152298 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 4096 max: 586358 count: 1227716 average: 4059.12 | standard deviation: 6630.54 | 915382 91625 85198 72179 41849 15993 4230 871 157 19 15 10 11 13 13 11 7 8 6 6 5 6 1 6 7 6 3 2 6 6 2 6 3 2 4 4 1 3 3 0 1 0 3 4 0 2 2 2 0 0 3 2 1 0 1 1 2 0 0 1 0 0 0 1 0 0 1 2 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 4096 max: 458107 count: 798039 average: 4060.36 | standard deviation: 7800.42 | 595041 59542 55380 46865 27273 10341 2768 557 110 12 14 9 7 8 7 7 4 8 4 4 2 5 1 1 7 6 2 1 4 5 1 4 2 1 2 3 1 2 2 0 0 0 2 3 0 2 1 1 0 0 2 1 0 0 1 1 2 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 4096 max: 586358 count: 429677 average: 4056.81 | standard deviation: 5606.8 | 320341 32083 29818 25314 14576 5652 1462 314 47 7 1 1 4 5 6 4 3 0 2 2 3 1 0 5 0 0 1 1 2 1 1 2 1 1 2 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_NULL: [binsize: 4096 max: 586358 count: 1227716 average: 4059.12 | standard deviation: 6630.54 | 915382 91625 85198 72179 41849 15993 4230 871 157 19 15 10 11 13 13 11 7 8 6 6 5 6 1 6 7 6 3 2 6 6 2 6 3 2 4 4 1 3 3 0 1 0 3 4 0 2 2 2 0 0 3 2 1 0 1 1 2 0 0 1 0 0 0 1 0 0 1 2 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,8 +85,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 4096 max: 458107 count: 798039 average: 4060.36 | standard deviation: 7800.42 | 595041 59542 55380 46865 27273 10341 2768 557 110 12 14 9 7 8 7 7 4 8 4 4 2 5 1 1 7 6 2 1 4 5 1 4 2 1 2 3 1 2 2 0 0 0 2 3 0 2 1 1 0 0 2 1 0 0 1 1 2 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 4096 max: 586358 count: 429677 average: 4056.81 | standard deviation: 5606.8 | 320341 32083 29818 25314 14576 5652 1462 314 47 7 1 1 4 5 6 4 3 0 2 2 3 1 0 5 0 0 1 1 2 1 1 2 1 1 2 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_NULL: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -116,302 +116,227 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 491
+user_time: 29
 system_time: 0
-page_reclaims: 10526
+page_reclaims: 9510
 page_faults: 0
 swaps: 0
-block_inputs: 0
+block_inputs: 16
 block_outputs: 0
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 7302717 58421736
-total_msg_count_Response_Data: 7240224 521296128
-total_msg_count_ResponseL2hit_Data: 12633 909576
-total_msg_count_ResponseLocal_Data: 49758 3582576
-total_msg_count_Response_Control: 17919 143352
-total_msg_count_Writeback_Data: 4922002 354384144
-total_msg_count_Writeback_Control: 16868172 134945376
-total_msg_count_Forwarded_Control: 49758 398064
-total_msg_count_Invalidate_Control: 153 1224
-total_msg_count_Unblock_Control: 7327287 58618296
-total_msgs: 43790623 total_bytes: 1132700472
+total_msg_count_Request_Control: 311844 2494752
+total_msg_count_Response_Data: 12 864
+total_msg_count_ResponseLocal_Data: 311478 22426416
+total_msg_count_Response_Control: 113679 909432
+total_msg_count_Forwarded_Control: 311796 2494368
+total_msg_count_Invalidate_Control: 1988 15904
+total_msg_count_Unblock_Control: 311802 2494416
+total_msgs: 1362599 total_bytes: 30836152
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.142732
-  links_utilized_percent_switch_0_link_0: 0.0492106 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.236253 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Response_Data: 150484 10834848 [ 0 0 150484 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 517 37224 [ 0 0 517 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 2084 150048 [ 0 0 2084 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 733 5864 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Forwarded_Control: 2038 16304 [ 2038 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 153088 1224704 [ 153088 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 2038 146736 [ 0 0 2038 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 8 64 [ 0 0 8 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 151322 10895184 [ 0 0 151322 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Unblock_Control: 154131 1233048 [ 0 0 154131 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.130402
+  links_utilized_percent_switch_0_link_0: 0.0495676 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.211237 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 12920 103360 [ 12920 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12975 934200 [ 0 0 12975 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 77 616 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 12918 103344 [ 0 0 12918 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.143413
-  links_utilized_percent_switch_1_link_0: 0.0494321 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.237394 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Response_Data: 151179 10884888 [ 0 0 151179 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 522 37584 [ 0 0 522 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 2067 148824 [ 0 0 2067 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 724 5792 [ 0 0 724 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Forwarded_Control: 2120 16960 [ 2120 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 153771 1230168 [ 153771 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 2120 152640 [ 0 0 2120 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 6 48 [ 0 0 6 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 151999 10943928 [ 0 0 151999 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Unblock_Control: 154820 1238560 [ 0 0 154820 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.130527
+  links_utilized_percent_switch_1_link_0: 0.0497582 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.211296 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 12985 103880 [ 12985 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 12962 933264 [ 0 0 12962 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 12983 103864 [ 0 0 12983 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.143021
-  links_utilized_percent_switch_2_link_0: 0.0493064 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.236736 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Response_Data: 150709 10851048 [ 0 0 150709 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 552 39744 [ 0 0 552 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 2118 152496 [ 0 0 2118 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 783 6264 [ 0 0 783 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Forwarded_Control: 2035 16280 [ 2035 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Invalidate_Control: 9 72 [ 9 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 153382 1227056 [ 153382 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 2035 146520 [ 0 0 2035 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 9 72 [ 0 0 9 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 151649 10918728 [ 0 0 151649 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Unblock_Control: 154390 1235120 [ 0 0 154390 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.130904
+  links_utilized_percent_switch_2_link_0: 0.0499306 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.211878 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 13024 104192 [ 13024 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12997 935784 [ 0 0 12997 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 13023 104184 [ 0 0 13023 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.14278
-  links_utilized_percent_switch_3_link_0: 0.0492124 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.236348 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Response_Data: 150596 10842912 [ 0 0 150596 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 483 34776 [ 0 0 483 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 2010 144720 [ 0 0 2010 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 718 5744 [ 0 0 718 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Forwarded_Control: 2087 16696 [ 2087 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 153091 1224728 [ 153091 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 2087 150264 [ 0 0 2087 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 6 48 [ 0 0 6 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 151360 10897920 [ 0 0 151360 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Unblock_Control: 154100 1232800 [ 0 0 154100 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_3: 0.131152
+  links_utilized_percent_switch_3_link_0: 0.0500739 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.21223 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 13063 104504 [ 13063 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 111 888 [ 0 0 111 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 13061 104488 [ 0 0 13061 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0.142856
-  links_utilized_percent_switch_4_link_0: 0.0492357 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 0.236477 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_4_link_0_Response_Data: 150629 10845288 [ 0 0 150629 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 518 37296 [ 0 0 518 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 2015 145080 [ 0 0 2015 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Control: 709 5672 [ 0 0 709 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Forwarded_Control: 2056 16448 [ 2056 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 153164 1225312 [ 153164 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 2056 148032 [ 0 0 2056 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 5 40 [ 0 0 5 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 151475 10906200 [ 0 0 151475 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Unblock_Control: 154166 1233328 [ 0 0 154166 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_4: 0.130608
+  links_utilized_percent_switch_4_link_0: 0.0498674 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0.21135 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 12995 103960 [ 12995 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 12993 103944 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0.143084
-  links_utilized_percent_switch_5_link_0: 0.0493135 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.236854 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_5_link_0_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 528 38016 [ 0 0 528 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 2002 144144 [ 0 0 2002 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 715 5720 [ 0 0 715 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Forwarded_Control: 2090 16720 [ 2090 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 153405 1227240 [ 153405 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 2090 150480 [ 0 0 2090 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 8 64 [ 0 0 8 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 151692 10921824 [ 0 0 151692 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Unblock_Control: 154393 1235144 [ 0 0 154393 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_5: 0.129687
+  links_utilized_percent_switch_5_link_0: 0.0495006 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.209874 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 12908 103264 [ 12908 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12873 926856 [ 0 0 12873 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 12906 103248 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0.143721
-  links_utilized_percent_switch_6_link_0: 0.0495395 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 0.237903 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_6_link_0_Response_Data: 151359 10897848 [ 0 0 151359 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 565 40680 [ 0 0 565 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 2164 155808 [ 0 0 2164 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 807 6456 [ 0 0 807 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Forwarded_Control: 2143 17144 [ 2143 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Invalidate_Control: 7 56 [ 7 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 154090 1232720 [ 154090 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 2143 154296 [ 0 0 2143 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 7 56 [ 0 0 7 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 152300 10965600 [ 0 0 152300 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Unblock_Control: 155187 1241496 [ 0 0 155187 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_6: 0.130865
+  links_utilized_percent_switch_6_link_0: 0.0499036 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 0.211826 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12998 935856 [ 0 0 12998 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 13007 104056 [ 0 0 13007 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0.143169
-  links_utilized_percent_switch_7_link_0: 0.0493539 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 0.236983 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_7_link_0_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 526 37872 [ 0 0 526 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 2126 153072 [ 0 0 2126 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 784 6272 [ 0 0 784 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Forwarded_Control: 2017 16136 [ 2017 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 153527 1228216 [ 153527 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 2017 145224 [ 0 0 2017 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 151829 10931688 [ 0 0 151829 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Unblock_Control: 154539 1236312 [ 0 0 154539 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_7: 0.131276
+  links_utilized_percent_switch_7_link_0: 0.0500158 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 0.212537 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 13043 104344 [ 13043 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 13043 939096 [ 0 0 13043 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 97 776 [ 0 0 97 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 13041 104328 [ 0 0 13041 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 1.73629
-  links_utilized_percent_switch_8_link_0: 0.856152 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 2.61643 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 1227518 9820144 [ 1227518 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 1213626 87381072 [ 0 0 1213626 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Control: 2424023 19392184 [ 1222304 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Unblock_Control: 1235726 9885808 [ 0 0 1235726 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 4211 303192 [ 0 0 4211 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Control: 5922 47376 [ 0 0 5922 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Data: 427042 30747024 [ 0 0 427042 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 3198701 25589608 [ 1222304 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Forwarded_Control: 16586 132688 [ 16586 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Invalidate_Control: 51 408 [ 51 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 0.143198
+  links_utilized_percent_switch_8_link_0: 0.0769419 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 0.209455 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Control: 37110 296880 [ 0 0 37110 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Forwarded_Control: 103932 831456 [ 103932 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Invalidate_Control: 422 3376 [ 422 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 2
 switch_9_outlinks: 2
-links_utilized_percent_switch_9: 0.906567
-  links_utilized_percent_switch_9_link_0: 0.264297 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 1.54884 bw: 160000 base_latency: 1
+links_utilized_percent_switch_9: 1.40637e-05
+  links_utilized_percent_switch_9_link_0: 1.48039e-06 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 2.6647e-05 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_9_link_0_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Data: 427041 30746952 [ 0 0 427041 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 1976397 15811176 [ 0 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 1201719 9613752 [ 0 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_10_inlinks: 10
 switch_10_outlinks: 10
-links_utilized_percent_switch_10: 0.606021
-  links_utilized_percent_switch_10_link_0: 0.196842 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_1: 0.197728 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_2: 0.197225 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_3: 0.19685 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_4: 0.196943 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_5: 0.197254 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_6: 0.198158 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_7: 0.197416 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_8: 3.42461 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_9: 1.05719 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_10_link_0_Response_Data: 150484 10834848 [ 0 0 150484 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 517 37224 [ 0 0 517 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 2084 150048 [ 0 0 2084 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Response_Control: 733 5864 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Forwarded_Control: 2038 16304 [ 2038 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Data: 151179 10884888 [ 0 0 151179 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 522 37584 [ 0 0 522 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 2067 148824 [ 0 0 2067 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Control: 724 5792 [ 0 0 724 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Forwarded_Control: 2120 16960 [ 2120 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Response_Data: 150709 10851048 [ 0 0 150709 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 552 39744 [ 0 0 552 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 2118 152496 [ 0 0 2118 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Response_Control: 783 6264 [ 0 0 783 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Forwarded_Control: 2035 16280 [ 2035 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Invalidate_Control: 9 72 [ 9 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Data: 150596 10842912 [ 0 0 150596 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 483 34776 [ 0 0 483 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 2010 144720 [ 0 0 2010 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Control: 718 5744 [ 0 0 718 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Forwarded_Control: 2087 16696 [ 2087 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Response_Data: 150629 10845288 [ 0 0 150629 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 518 37296 [ 0 0 518 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 2015 145080 [ 0 0 2015 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Response_Control: 709 5672 [ 0 0 709 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Forwarded_Control: 2056 16448 [ 2056 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 528 38016 [ 0 0 528 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 2002 144144 [ 0 0 2002 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Response_Control: 715 5720 [ 0 0 715 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Forwarded_Control: 2090 16720 [ 2090 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Data: 151359 10897848 [ 0 0 151359 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 565 40680 [ 0 0 565 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 2164 155808 [ 0 0 2164 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Control: 807 6456 [ 0 0 807 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Forwarded_Control: 2143 17144 [ 2143 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Invalidate_Control: 7 56 [ 7 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 526 37872 [ 0 0 526 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 2126 153072 [ 0 0 2126 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Control: 784 6272 [ 0 0 784 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Forwarded_Control: 2017 16136 [ 2017 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Request_Control: 1227518 9820144 [ 1227518 0 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Writeback_Data: 1213626 87381072 [ 0 0 1213626 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Writeback_Control: 2424023 19392184 [ 1222304 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Unblock_Control: 1235726 9885808 [ 0 0 1235726 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Data: 427041 30746952 [ 0 0 427041 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Control: 1976397 15811176 [ 0 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_10: 0.190224
+  links_utilized_percent_switch_10_link_0: 0.19827 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 0.199033 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 0.199723 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 0.200295 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 0.199469 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 0.198002 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 0.199615 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 0.200063 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 0.307767 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 5.92157e-06 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -431,155 +356,155 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory
 
  --- L1Cache ---
  - Event Counts -
-Load [99346 99989 100000 99701 99652 99889 99730 99744 ] 798051
+Load [99188 98347 99157 99646 99118 99153 100001 99634 ] 794244
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [53842 53434 54117 53855 53466 53908 53685 53375 ] 429682
-L1_Replacement [51679234 51650729 51653770 51670696 51699067 51665651 51674373 51657971 ] 413351491
-Own_GETX [0 0 0 0 0 0 0 0 ] 0
-Fwd_GETX [2699 2710 2705 2541 2634 2694 2642 2703 ] 21328
-Fwd_GETS [4842 4709 5137 4829 4716 5047 4647 4835 ] 38762
+Store [53590 53268 53749 53528 53019 53486 53183 54001 ] 427824
+L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+Own_GETX [12 14 11 13 11 21 9 13 ] 104
+Fwd_GETX [22780 22543 22706 22494 22314 22746 22504 22308 ] 180395
+Fwd_GETS [40560 40358 40695 41058 40851 40579 40962 41289 ] 326352
 Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
-Inv [5 8 7 2 8 6 9 6 ] 51
-Ack [709 715 807 784 733 724 783 718 ] 5973
-Data [1692 1677 1758 1730 1717 1744 1731 1702 ] 13751
-Exclusive_Data [151470 151727 152330 151796 151368 152024 151648 151387 ] 1213750
-Writeback_Ack [729 713 785 732 775 770 747 723 ] 5974
-Writeback_Ack_Data [151750 151968 152615 152110 151593 152281 151913 151648 ] 1215878
-Writeback_Nack [49 50 71 58 60 59 58 47 ] 452
-All_acks [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593
-Use_Timeout [151470 151727 152329 151795 151368 152024 151648 151387 ] 1213748
+Inv [102 98 91 97 77 104 103 111 ] 783
+Ack [4834 4737 4774 4737 4705 4701 4676 4729 ] 37893
+Data [117 113 98 108 88 113 112 122 ] 871
+Exclusive_Data [12864 12779 12898 12920 12819 12849 12902 12926 ] 102957
+Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0
+Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110
+Use_Timeout [12876 12793 12908 12933 12830 12870 12910 12939 ] 103059
 
  - Transitions -
-I  Load [99333 99979 99984 99680 99633 99873 99711 99727 ] 797920
+I  Load [8262 8273 8337 8401 8312 8394 8441 8416 ] 66836
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [53831 53425 54106 53847 53455 53898 53671 53363 ] 429596
-I  L1_Replacement [678 714 682 680 711 712 713 712 ] 5602
+I  Store [4573 4492 4542 4491 4468 4437 4447 4499 ] 35949
+I  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 I  Inv [0 0 0 0 0 0 0 0 ] 0
 
-S  Load [0 0 0 0 0 0 1 0 ] 1
+S  Load [136 189 149 161 147 187 176 221 ] 1366
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
-S  Store [0 1 0 0 0 0 0 1 ] 2
-S  L1_Replacement [1690 1673 1755 1729 1714 1742 1727 1698 ] 13728
-S  Fwd_GETS [4 5 7 7 2 6 3 5 ] 39
+S  Store [109 97 80 91 76 95 93 104 ] 745
+S  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+S  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
-S  Inv [2 3 3 1 3 2 4 3 ] 21
+S  Inv [8 16 18 17 12 18 19 18 ] 126
 
-O  Load [0 0 0 0 0 0 0 0 ] 0
+O  Load [93 105 85 75 124 102 80 82 ] 746
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
-O  Store [0 0 0 0 0 0 0 0 ] 0
-O  L1_Replacement [584 611 588 525 551 566 556 589 ] 4570
-O  Fwd_GETX [2 3 0 1 0 1 0 1 ] 8
-O  Fwd_GETS [2 3 3 1 3 4 6 4 ] 26
+O  Store [51 46 49 60 64 59 43 44 ] 416
+O  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+O  Fwd_GETX [2 4 2 1 1 1 3 1 ] 15
+O  Fwd_GETS [3 5 4 2 6 8 4 3 ] 35
 O  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 
-M  Load [7 2 11 9 11 11 13 10 ] 74
+M  Load [116 128 118 133 159 134 127 113 ] 1028
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [6 4 8 4 5 7 8 6 ] 48
-M  L1_Replacement [96750 97343 97329 97135 97016 97229 97061 97091 ] 776954
-M  Fwd_GETX [295 337 299 283 341 322 351 335 ] 2563
-M  Fwd_GETS [586 614 588 526 551 567 556 590 ] 4578
+M  Store [57 72 73 65 45 58 84 64 ] 518
+M  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+M  Fwd_GETX [28 33 30 32 33 36 34 34 ] 260
+M  Fwd_GETS [53 50 51 61 65 60 46 45 ] 431
 M  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 
-M_W  Load [0 1 0 0 0 0 0 0 ] 1
+M_W  Load [14625 14739 14872 15279 15066 15137 15392 14864 ] 119974
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M_W  Store [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_Replacement [1731154 1738479 1732095 1738299 1737770 1736109 1737116 1740218 ] 13891240
+M_W  Store [8005 8003 8084 8133 8079 8125 8164 8149 ] 64742
+M_W  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 M_W  Own_GETX [0 0 0 0 0 0 0 0 ] 0
-M_W  Fwd_GETX [1239 1175 1217 1063 1241 1209 1241 1280 ] 9665
-M_W  Fwd_GETS [2253 2137 2289 2249 2093 2363 2012 2169 ] 17565
+M_W  Fwd_GETX [1364 1363 1417 1394 1416 1389 1476 1364 ] 11183
+M_W  Fwd_GETS [2392 2478 2488 2651 2563 2494 2590 2473 ] 20129
 M_W  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 M_W  Inv [0 0 0 0 0 0 0 0 ] 0
-M_W  Use_Timeout [97639 98301 98225 97949 97914 98126 97977 98024 ] 784155
+M_W  Use_Timeout [138 155 154 158 143 154 164 143 ] 1209
 
-MM  Load [6 7 5 12 8 5 5 7 ] 55
+MM  Load [11570 11359 11558 11408 11540 11529 11698 11455 ] 92117
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM  Store [5 4 3 3 6 3 4 5 ] 33
-MM  L1_Replacement [53458 53059 53732 53454 53092 53518 53321 52996 ] 426630
-MM  Fwd_GETX [153 142 131 147 140 143 121 122 ] 1099
-MM  Fwd_GETS [226 229 249 248 227 244 237 251 ] 1911
+MM  Store [6129 6213 6160 6217 6122 6256 6194 6383 ] 49674
+MM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+MM  Fwd_GETX [4600 4549 4589 4547 4500 4586 4546 4502 ] 36419
+MM  Fwd_GETS [8195 8161 8238 8293 8232 8188 8284 8358 ] 65949
 MM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 
-MM_W  Load [0 0 0 0 0 0 0 0 ] 0
+MM_W  Load [64386 63554 64038 64189 63770 63670 64087 64483 ] 512177
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM_W  Store [0 0 0 1 0 0 2 0 ] 3
-MM_W  L1_Replacement [950252 943134 957418 948048 944969 950631 948207 941544 ] 7584203
+MM_W  Store [34666 34345 34761 34471 34165 34456 34158 34758 ] 275780
+MM_W  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 MM_W  Own_GETX [0 0 0 0 0 0 0 0 ] 0
-MM_W  Fwd_GETX [735 777 743 766 641 737 665 677 ] 5741
-MM_W  Fwd_GETS [1258 1240 1450 1275 1337 1312 1336 1325 ] 10533
+MM_W  Fwd_GETX [16747 16562 16630 16473 16311 16696 16411 16376 ] 132206
+MM_W  Fwd_GETS [29873 29625 29868 29991 29900 29784 29992 30370 ] 239403
 MM_W  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 MM_W  Inv [0 0 0 0 0 0 0 0 ] 0
-MM_W  Use_Timeout [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593
+MM_W  Use_Timeout [12738 12638 12754 12775 12687 12716 12746 12796 ] 101850
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
-IM  L1_Replacement [17050741 16944001 17146281 17026088 16990015 16910076 17042850 17066004 ] 136176056
+IM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 IM  Inv [0 0 0 0 0 0 0 0 ] 0
-IM  Ack [705 712 801 777 729 720 777 709 ] 5930
+IM  Ack [4717 4630 4681 4635 4610 4584 4595 4636 ] 37088
 IM  Data [0 0 0 0 0 0 0 0 ] 0
-IM  Exclusive_Data [53831 53425 54104 53846 53454 53898 53671 53362 ] 429591
+IM  Exclusive_Data [4706 4606 4653 4618 4586 4561 4565 4623 ] 36918
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SM  Store [0 0 0 0 0 0 0 0 ] 0
-SM  L1_Replacement [0 66 0 0 0 0 0 0 ] 66
+SM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 SM  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
 SM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
-SM  Inv [0 0 0 0 0 0 0 0 ] 0
-SM  Ack [0 0 0 0 0 0 0 0 ] 0
+SM  Inv [94 82 73 80 65 86 84 93 ] 657
+SM  Ack [33 31 14 16 20 21 15 20 ] 170
 SM  Data [0 0 0 0 0 0 0 0 ] 0
-SM  Exclusive_Data [0 1 0 0 0 0 0 1 ] 2
+SM  Exclusive_Data [15 15 7 11 11 9 9 11 ] 88
 
 OM  Load [0 0 0 0 0 0 0 0 ] 0
 OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 OM  Store [0 0 0 0 0 0 0 0 ] 0
-OM  L1_Replacement [210 239 245 295 296 192 259 272 ] 2008
-OM  Own_GETX [0 0 0 0 0 0 0 0 ] 0
-OM  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
-OM  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+OM  Own_GETX [12 14 11 13 11 21 9 13 ] 104
+OM  Fwd_GETX [39 32 38 47 53 38 34 31 ] 312
+OM  Fwd_GETS [44 39 46 60 85 45 46 40 ] 405
 OM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
-OM  Ack [4 3 6 7 4 4 6 9 ] 43
-OM  All_acks [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593
+OM  Ack [84 76 79 86 75 96 66 73 ] 635
+OM  All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
-IS  L1_Replacement [31793717 31871410 31663645 31804443 31872933 31914876 31792563 31756847 ] 254470434
+IS  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 IS  Inv [0 0 0 0 0 0 0 0 ] 0
-IS  Data [1692 1677 1758 1730 1717 1744 1731 1702 ] 13751
-IS  Exclusive_Data [97639 98301 98226 97950 97914 98126 97977 98024 ] 784157
+IS  Data [117 113 98 108 88 113 112 122 ] 871
+IS  Exclusive_Data [8143 8158 8238 8291 8222 8279 8328 8292 ] 65951
 
 SI  Load [0 0 0 0 0 0 0 0 ] 0
 SI  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SI  Store [0 0 0 0 0 0 0 0 ] 0
 SI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
-SI  Fwd_GETS [5 3 2 1 2 3 1 4 ] 21
+SI  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
 SI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
-SI  Inv [3 5 4 1 5 4 5 3 ] 30
-SI  Writeback_Ack [729 713 785 732 775 770 747 723 ] 5974
-SI  Writeback_Ack_Data [958 955 966 996 934 968 975 972 ] 7724
+SI  Inv [0 0 0 0 0 0 0 0 ] 0
+SI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+SI  Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0
 SI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 OI  Load [0 0 0 0 0 0 0 0 ] 0
 OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
 OI  Store [0 0 0 0 0 0 0 0 ] 0
 OI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
-OI  Fwd_GETX [0 0 2 2 0 0 0 1 ] 5
-OI  Fwd_GETS [3 0 2 0 5 4 0 2 ] 16
+OI  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
+OI  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 OI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
-OI  Writeback_Ack_Data [1089 1089 1133 1045 1047 1110 1052 1073 ] 8638
-OI  Writeback_Nack [46 45 67 57 55 55 53 44 ] 422
+OI  Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0
+OI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 MI  Load [0 0 0 0 0 0 0 0 ] 0
 MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MI  Store [0 0 0 0 0 0 0 0 ] 0
 MI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
-MI  Fwd_GETX [275 276 313 279 271 282 264 287 ] 2247
-MI  Fwd_GETS [505 478 547 522 496 544 496 485 ] 4073
+MI  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
+MI  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
 MI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack_Data [149428 149648 150201 149788 149341 149921 149622 149315 ] 1197264
+MI  Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0
 MI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 II  Load [0 0 0 0 0 0 0 0 ] 0
@@ -588,8 +513,8 @@ II  Store [0 0 0 0 0 0 0 0 ] 0
 II  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 II  Inv [0 0 0 0 0 0 0 0 ] 0
 II  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
-II  Writeback_Ack_Data [275 276 315 281 271 282 264 288 ] 2252
-II  Writeback_Nack [3 5 4 1 5 4 5 3 ] 30
+II  Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0
+II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
   system.l1_cntrl1.L1IcacheMemory_total_misses: 0
@@ -713,12 +638,12 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
 
  --- L2Cache ---
  - Event Counts -
-L1_GETS [1156724 ] 1156724
-L1_GETX [632843 ] 632843
-L1_PUTO [6387 ] 6387
-L1_PUTX [1217214 ] 1217214
-L1_PUTS_only [19414 ] 19414
-L1_PUTS [180 ] 180
+L1_GETS [2715881 ] 2715881
+L1_GETX [1524697 ] 1524697
+L1_PUTO [0 ] 0
+L1_PUTX [0 ] 0
+L1_PUTS_only [0 ] 0
+L1_PUTS [0 ] 0
 Fwd_GETX [0 ] 0
 Fwd_GETS [0 ] 0
 Fwd_DMA [0 ] 0
@@ -726,20 +651,20 @@ Own_GETX [0 ] 0
 Inv [0 ] 0
 IntAck [0 ] 0
 ExtAck [0 ] 0
-All_Acks [422217 ] 422217
-Data [427178 ] 427178
-Data_Exclusive [779526 ] 779526
-L1_WBCLEANDATA [785130 ] 785130
-L1_WBDIRTYDATA [428496 ] 428496
-Writeback_Ack [1201719 ] 1201719
+All_Acks [0 ] 0
+Data [0 ] 0
+Data_Exclusive [2 ] 2
+L1_WBCLEANDATA [0 ] 0
+L1_WBDIRTYDATA [0 ] 0
+Writeback_Ack [0 ] 0
 Writeback_Nack [0 ] 0
-Unblock [21977 ] 21977
-Exclusive_Unblock [1213749 ] 1213749
-L2_Replacement [1209622 ] 1209622
+Unblock [871 ] 871
+Exclusive_Unblock [103061 ] 103061
+L2_Replacement [0 ] 0
 
  - Transitions -
-NP  L1_GETS [784499 ] 784499
-NP  L1_GETX [422171 ] 422171
+NP  L1_GETS [2 ] 2
+NP  L1_GETX [0 ] 0
 NP  L1_PUTO [0 ] 0
 NP  L1_PUTX [0 ] 0
 NP  L1_PUTS [0 ] 0
@@ -753,21 +678,21 @@ I  L1_PUTS [0 ] 0
 I  Inv [0 ] 0
 I  L2_Replacement [0 ] 0
 
-ILS  L1_GETS [60 ] 60
-ILS  L1_GETX [37 ] 37
+ILS  L1_GETS [0 ] 0
+ILS  L1_GETX [0 ] 0
 ILS  L1_PUTO [0 ] 0
 ILS  L1_PUTX [0 ] 0
-ILS  L1_PUTS_only [7655 ] 7655
-ILS  L1_PUTS [69 ] 69
+ILS  L1_PUTS_only [0 ] 0
+ILS  L1_PUTS [0 ] 0
 ILS  Inv [0 ] 0
 ILS  L2_Replacement [0 ] 0
 
-ILX  L1_GETS [10562 ] 10562
-ILX  L1_GETX [5909 ] 5909
+ILX  L1_GETS [66382 ] 66382
+ILX  L1_GETX [36679 ] 36679
 ILX  L1_PUTO [0 ] 0
-ILX  L1_PUTX [1199516 ] 1199516
+ILX  L1_PUTX [0 ] 0
 ILX  L1_PUTS_only [0 ] 0
-ILX  L1_PUTS [30 ] 30
+ILX  L1_PUTS [0 ] 0
 ILX  Fwd_GETX [0 ] 0
 ILX  Fwd_GETS [0 ] 0
 ILX  Fwd_DMA [0 ] 0
@@ -787,10 +712,10 @@ ILO  Inv [0 ] 0
 ILO  Data [0 ] 0
 ILO  L2_Replacement [0 ] 0
 
-ILOX  L1_GETS [15 ] 15
-ILOX  L1_GETX [4 ] 4
-ILOX  L1_PUTO [2554 ] 2554
-ILOX  L1_PUTX [422 ] 422
+ILOX  L1_GETS [0 ] 0
+ILOX  L1_GETX [0 ] 0
+ILOX  L1_PUTO [0 ] 0
+ILOX  L1_PUTX [0 ] 0
 ILOX  L1_PUTS [0 ] 0
 ILOX  Fwd_GETX [0 ] 0
 ILOX  Fwd_GETS [0 ] 0
@@ -809,23 +734,23 @@ ILOS  Fwd_DMA [0 ] 0
 ILOS  Data [0 ] 0
 ILOS  L2_Replacement [0 ] 0
 
-ILOSX  L1_GETS [27 ] 27
-ILOSX  L1_GETX [9 ] 9
-ILOSX  L1_PUTO [2438 ] 2438
-ILOSX  L1_PUTX [3646 ] 3646
-ILOSX  L1_PUTS_only [2573 ] 2573
-ILOSX  L1_PUTS [11 ] 11
+ILOSX  L1_GETS [440 ] 440
+ILOSX  L1_GETX [431 ] 431
+ILOSX  L1_PUTO [0 ] 0
+ILOSX  L1_PUTX [0 ] 0
+ILOSX  L1_PUTS_only [0 ] 0
+ILOSX  L1_PUTS [0 ] 0
 ILOSX  Fwd_GETX [0 ] 0
 ILOSX  Fwd_GETS [0 ] 0
 ILOSX  Fwd_DMA [0 ] 0
 ILOSX  Data [0 ] 0
 
-S  L1_GETS [24 ] 24
-S  L1_GETX [14 ] 14
+S  L1_GETS [0 ] 0
+S  L1_GETX [0 ] 0
 S  L1_PUTX [0 ] 0
 S  L1_PUTS [0 ] 0
 S  Inv [0 ] 0
-S  L2_Replacement [7658 ] 7658
+S  L2_Replacement [0 ] 0
 
 O  L1_GETS [0 ] 0
 O  L1_GETX [0 ] 0
@@ -845,34 +770,34 @@ OLS  Fwd_GETS [0 ] 0
 OLS  Fwd_DMA [0 ] 0
 OLS  L2_Replacement [0 ] 0
 
-OLSX  L1_GETS [13 ] 13
-OLSX  L1_GETX [7 ] 7
+OLSX  L1_GETS [0 ] 0
+OLSX  L1_GETX [0 ] 0
 OLSX  L1_PUTO [0 ] 0
 OLSX  L1_PUTX [0 ] 0
-OLSX  L1_PUTS_only [3329 ] 3329
-OLSX  L1_PUTS [20 ] 20
+OLSX  L1_PUTS_only [0 ] 0
+OLSX  L1_PUTS [0 ] 0
 OLSX  Fwd_GETX [0 ] 0
 OLSX  Fwd_GETS [0 ] 0
 OLSX  Fwd_DMA [0 ] 0
-OLSX  L2_Replacement [2748 ] 2748
+OLSX  L2_Replacement [0 ] 0
 
 SLS  L1_GETS [0 ] 0
 SLS  L1_GETX [0 ] 0
 SLS  L1_PUTX [0 ] 0
-SLS  L1_PUTS_only [41 ] 41
+SLS  L1_PUTS_only [0 ] 0
 SLS  L1_PUTS [0 ] 0
 SLS  Inv [0 ] 0
-SLS  L2_Replacement [52 ] 52
+SLS  L2_Replacement [0 ] 0
 
-M  L1_GETS [2720 ] 2720
-M  L1_GETX [1447 ] 1447
+M  L1_GETS [0 ] 0
+M  L1_GETX [0 ] 0
 M  L1_PUTO [0 ] 0
 M  L1_PUTX [0 ] 0
 M  L1_PUTS [0 ] 0
 M  Fwd_GETX [0 ] 0
 M  Fwd_GETS [0 ] 0
 M  Fwd_DMA [0 ] 0
-M  L2_Replacement [1198972 ] 1198972
+M  L2_Replacement [0 ] 0
 
 IFGX  L1_GETS [0 ] 0
 IFGX  L1_GETX [0 ] 0
@@ -971,19 +896,19 @@ ILOW  L1_WBDIRTYDATA [0 ] 0
 ILOW  Unblock [0 ] 0
 ILOW  L2_Replacement [0 ] 0
 
-ILOXW  L1_GETS [2 ] 2
+ILOXW  L1_GETS [0 ] 0
 ILOXW  L1_GETX [0 ] 0
-ILOXW  L1_PUTO [185 ] 185
-ILOXW  L1_PUTX [839 ] 839
+ILOXW  L1_PUTO [0 ] 0
+ILOXW  L1_PUTX [0 ] 0
 ILOXW  L1_PUTS_only [0 ] 0
 ILOXW  L1_PUTS [0 ] 0
 ILOXW  Fwd_GETX [0 ] 0
 ILOXW  Fwd_GETS [0 ] 0
 ILOXW  Fwd_DMA [0 ] 0
 ILOXW  Inv [0 ] 0
-ILOXW  L1_WBCLEANDATA [2332 ] 2332
-ILOXW  L1_WBDIRTYDATA [222 ] 222
-ILOXW  Unblock [2573 ] 2573
+ILOXW  L1_WBCLEANDATA [0 ] 0
+ILOXW  L1_WBDIRTYDATA [0 ] 0
+ILOXW  Unblock [0 ] 0
 ILOXW  L2_Replacement [0 ] 0
 
 ILOSW  L1_GETS [0 ] 0
@@ -1001,19 +926,19 @@ ILOSW  L1_WBDIRTYDATA [0 ] 0
 ILOSW  Unblock [0 ] 0
 ILOSW  L2_Replacement [0 ] 0
 
-ILOSXW  L1_GETS [16 ] 16
-ILOSXW  L1_GETX [8 ] 8
+ILOSXW  L1_GETS [0 ] 0
+ILOSXW  L1_GETX [0 ] 0
 ILOSXW  L1_PUTO [0 ] 0
-ILOSXW  L1_PUTX [6 ] 6
-ILOSXW  L1_PUTS_only [3219 ] 3219
-ILOSXW  L1_PUTS [18 ] 18
+ILOSXW  L1_PUTX [0 ] 0
+ILOSXW  L1_PUTS_only [0 ] 0
+ILOSXW  L1_PUTS [0 ] 0
 ILOSXW  Fwd_GETX [0 ] 0
 ILOSXW  Fwd_GETS [0 ] 0
 ILOSXW  Fwd_DMA [0 ] 0
 ILOSXW  Inv [0 ] 0
-ILOSXW  L1_WBCLEANDATA [4446 ] 4446
-ILOSXW  L1_WBDIRTYDATA [1638 ] 1638
-ILOSXW  Unblock [11 ] 11
+ILOSXW  L1_WBCLEANDATA [0 ] 0
+ILOSXW  L1_WBDIRTYDATA [0 ] 0
+ILOSXW  Unblock [0 ] 0
 ILOSXW  L2_Replacement [0 ] 0
 
 SLSW  L1_GETS [0 ] 0
@@ -1047,16 +972,16 @@ ILSW  L1_GETX [0 ] 0
 ILSW  L1_PUTO [0 ] 0
 ILSW  L1_PUTX [0 ] 0
 ILSW  L1_PUTS_only [0 ] 0
-ILSW  L1_PUTS [17 ] 17
+ILSW  L1_PUTS [0 ] 0
 ILSW  Fwd_GETX [0 ] 0
 ILSW  Fwd_GETS [0 ] 0
 ILSW  Fwd_DMA [0 ] 0
 ILSW  Inv [0 ] 0
-ILSW  L1_WBCLEANDATA [69 ] 69
+ILSW  L1_WBCLEANDATA [0 ] 0
 ILSW  Unblock [0 ] 0
 ILSW  L2_Replacement [0 ] 0
 
-IW  L1_GETS [9 ] 9
+IW  L1_GETS [0 ] 0
 IW  L1_GETX [0 ] 0
 IW  L1_PUTO [0 ] 0
 IW  L1_PUTX [0 ] 0
@@ -1066,7 +991,7 @@ IW  Fwd_GETX [0 ] 0
 IW  Fwd_GETS [0 ] 0
 IW  Fwd_DMA [0 ] 0
 IW  Inv [0 ] 0
-IW  L1_WBCLEANDATA [7655 ] 7655
+IW  L1_WBCLEANDATA [0 ] 0
 IW  L2_Replacement [0 ] 0
 
 OW  L1_GETS [0 ] 0
@@ -1092,11 +1017,11 @@ SW  Fwd_GETX [0 ] 0
 SW  Fwd_GETS [0 ] 0
 SW  Fwd_DMA [0 ] 0
 SW  Inv [0 ] 0
-SW  Unblock [41 ] 41
-SW  L2_Replacement [4 ] 4
+SW  Unblock [0 ] 0
+SW  L2_Replacement [0 ] 0
 
-OXW  L1_GETS [7 ] 7
-OXW  L1_GETX [4 ] 4
+OXW  L1_GETS [0 ] 0
+OXW  L1_GETX [0 ] 0
 OXW  L1_PUTO [0 ] 0
 OXW  L1_PUTX [0 ] 0
 OXW  L1_PUTS_only [0 ] 0
@@ -1105,8 +1030,8 @@ OXW  Fwd_GETX [0 ] 0
 OXW  Fwd_GETS [0 ] 0
 OXW  Fwd_DMA [0 ] 0
 OXW  Inv [0 ] 0
-OXW  Unblock [3329 ] 3329
-OXW  L2_Replacement [97 ] 97
+OXW  Unblock [0 ] 0
+OXW  L2_Replacement [0 ] 0
 
 OLSXW  L1_GETS [0 ] 0
 OLSXW  L1_GETX [0 ] 0
@@ -1118,36 +1043,36 @@ OLSXW  Fwd_GETX [0 ] 0
 OLSXW  Fwd_GETS [0 ] 0
 OLSXW  Fwd_DMA [0 ] 0
 OLSXW  Inv [0 ] 0
-OLSXW  Unblock [20 ] 20
+OLSXW  Unblock [0 ] 0
 OLSXW  L2_Replacement [0 ] 0
 
-ILXW  L1_GETS [145 ] 145
-ILXW  L1_GETX [71 ] 71
+ILXW  L1_GETS [0 ] 0
+ILXW  L1_GETX [0 ] 0
 ILXW  L1_PUTO [0 ] 0
 ILXW  L1_PUTX [0 ] 0
 ILXW  L1_PUTS_only [0 ] 0
-ILXW  L1_PUTS [4 ] 4
+ILXW  L1_PUTS [0 ] 0
 ILXW  Fwd_GETX [0 ] 0
 ILXW  Fwd_GETS [0 ] 0
 ILXW  Fwd_DMA [0 ] 0
 ILXW  Inv [0 ] 0
 ILXW  Data [0 ] 0
-ILXW  L1_WBCLEANDATA [770628 ] 770628
-ILXW  L1_WBDIRTYDATA [426636 ] 426636
-ILXW  Unblock [2252 ] 2252
+ILXW  L1_WBCLEANDATA [0 ] 0
+ILXW  L1_WBDIRTYDATA [0 ] 0
+ILXW  Unblock [0 ] 0
 ILXW  L2_Replacement [0 ] 0
 
 IFLS  L1_GETS [0 ] 0
 IFLS  L1_GETX [0 ] 0
 IFLS  L1_PUTO [0 ] 0
 IFLS  L1_PUTX [0 ] 0
-IFLS  L1_PUTS_only [64 ] 64
+IFLS  L1_PUTS_only [0 ] 0
 IFLS  L1_PUTS [0 ] 0
 IFLS  Fwd_GETX [0 ] 0
 IFLS  Fwd_GETS [0 ] 0
 IFLS  Fwd_DMA [0 ] 0
 IFLS  Inv [0 ] 0
-IFLS  Unblock [60 ] 60
+IFLS  Unblock [0 ] 0
 IFLS  L2_Replacement [0 ] 0
 
 IFLO  L1_GETS [0 ] 0
@@ -1165,78 +1090,78 @@ IFLO  L2_Replacement [0 ] 0
 
 IFLOX  L1_GETS [0 ] 0
 IFLOX  L1_GETX [0 ] 0
-IFLOX  L1_PUTO [1 ] 1
-IFLOX  L1_PUTX [3 ] 3
-IFLOX  L1_PUTS_only [3 ] 3
+IFLOX  L1_PUTO [0 ] 0
+IFLOX  L1_PUTX [0 ] 0
+IFLOX  L1_PUTS_only [0 ] 0
 IFLOX  L1_PUTS [0 ] 0
 IFLOX  Fwd_GETX [0 ] 0
 IFLOX  Fwd_GETS [0 ] 0
 IFLOX  Fwd_DMA [0 ] 0
 IFLOX  Inv [0 ] 0
-IFLOX  Unblock [15 ] 15
-IFLOX  Exclusive_Unblock [7 ] 7
+IFLOX  Unblock [0 ] 0
+IFLOX  Exclusive_Unblock [0 ] 0
 IFLOX  L2_Replacement [0 ] 0
 
-IFLOXX  L1_GETS [360 ] 360
-IFLOXX  L1_GETX [116 ] 116
-IFLOXX  L1_PUTO [1204 ] 1204
-IFLOXX  L1_PUTX [12725 ] 12725
+IFLOXX  L1_GETS [2641993 ] 2641993
+IFLOXX  L1_GETX [1479034 ] 1479034
+IFLOXX  L1_PUTO [0 ] 0
+IFLOXX  L1_PUTX [0 ] 0
 IFLOXX  L1_PUTS_only [0 ] 0
-IFLOXX  L1_PUTS [6 ] 6
+IFLOXX  L1_PUTS [0 ] 0
 IFLOXX  Fwd_GETX [0 ] 0
 IFLOXX  Fwd_GETS [0 ] 0
 IFLOXX  Fwd_DMA [0 ] 0
 IFLOXX  Inv [0 ] 0
-IFLOXX  Unblock [8651 ] 8651
-IFLOXX  Exclusive_Unblock [7824 ] 7824
+IFLOXX  Unblock [431 ] 431
+IFLOXX  Exclusive_Unblock [102628 ] 102628
 IFLOXX  L2_Replacement [0 ] 0
 
-IFLOSX  L1_GETS [0 ] 0
-IFLOSX  L1_GETX [0 ] 0
-IFLOSX  L1_PUTO [5 ] 5
-IFLOSX  L1_PUTX [42 ] 42
-IFLOSX  L1_PUTS_only [26 ] 26
+IFLOSX  L1_GETS [3247 ] 3247
+IFLOSX  L1_GETX [4201 ] 4201
+IFLOSX  L1_PUTO [0 ] 0
+IFLOSX  L1_PUTX [0 ] 0
+IFLOSX  L1_PUTS_only [0 ] 0
 IFLOSX  L1_PUTS [0 ] 0
 IFLOSX  Fwd_GETX [0 ] 0
 IFLOSX  Fwd_GETS [0 ] 0
 IFLOSX  Fwd_DMA [0 ] 0
 IFLOSX  Inv [0 ] 0
-IFLOSX  Unblock [27 ] 27
+IFLOSX  Unblock [440 ] 440
 IFLOSX  Exclusive_Unblock [0 ] 0
 IFLOSX  L2_Replacement [0 ] 0
 
-IFLXO  L1_GETS [0 ] 0
-IFLXO  L1_GETX [0 ] 0
+IFLXO  L1_GETS [3428 ] 3428
+IFLXO  L1_GETX [4287 ] 4287
 IFLXO  L1_PUTO [0 ] 0
-IFLXO  L1_PUTX [15 ] 15
-IFLXO  L1_PUTS_only [6 ] 6
+IFLXO  L1_PUTX [0 ] 0
+IFLXO  L1_PUTS_only [0 ] 0
 IFLXO  L1_PUTS [0 ] 0
 IFLXO  Fwd_GETX [0 ] 0
 IFLXO  Fwd_GETS [0 ] 0
 IFLXO  Fwd_DMA [0 ] 0
 IFLXO  Inv [0 ] 0
-IFLXO  Exclusive_Unblock [9 ] 9
+IFLXO  Exclusive_Unblock [431 ] 431
 IFLXO  L2_Replacement [0 ] 0
 
-IGS  L1_GETS [232650 ] 232650
-IGS  L1_GETX [132978 ] 132978
+IGS  L1_GETS [389 ] 389
+IGS  L1_GETX [65 ] 65
 IGS  L1_PUTO [0 ] 0
 IGS  L1_PUTX [0 ] 0
 IGS  L1_PUTS_only [0 ] 0
-IGS  L1_PUTS [1 ] 1
+IGS  L1_PUTS [0 ] 0
 IGS  Fwd_GETX [0 ] 0
 IGS  Fwd_GETS [0 ] 0
 IGS  Fwd_DMA [0 ] 0
 IGS  Own_GETX [0 ] 0
 IGS  Inv [0 ] 0
-IGS  Data [4961 ] 4961
-IGS  Data_Exclusive [779526 ] 779526
-IGS  Unblock [4961 ] 4961
-IGS  Exclusive_Unblock [779525 ] 779525
+IGS  Data [0 ] 0
+IGS  Data_Exclusive [2 ] 2
+IGS  Unblock [0 ] 0
+IGS  Exclusive_Unblock [2 ] 2
 IGS  L2_Replacement [0 ] 0
 
-IGM  L1_GETS [121622 ] 121622
-IGM  L1_GETX [67947 ] 67947
+IGM  L1_GETS [0 ] 0
+IGM  L1_GETX [0 ] 0
 IGM  L1_PUTO [0 ] 0
 IGM  L1_PUTX [0 ] 0
 IGM  L1_PUTS_only [0 ] 0
@@ -1247,37 +1172,37 @@ IGM  Fwd_DMA [0 ] 0
 IGM  Own_GETX [0 ] 0
 IGM  Inv [0 ] 0
 IGM  ExtAck [0 ] 0
-IGM  Data [422180 ] 422180
+IGM  Data [0 ] 0
 IGM  Data_Exclusive [0 ] 0
 IGM  L2_Replacement [0 ] 0
 
 IGMLS  L1_GETS [0 ] 0
-IGMLS  L1_GETX [11 ] 11
+IGMLS  L1_GETX [0 ] 0
 IGMLS  L1_PUTO [0 ] 0
 IGMLS  L1_PUTX [0 ] 0
-IGMLS  L1_PUTS_only [2219 ] 2219
+IGMLS  L1_PUTS_only [0 ] 0
 IGMLS  L1_PUTS [0 ] 0
 IGMLS  Inv [0 ] 0
 IGMLS  IntAck [0 ] 0
 IGMLS  ExtAck [0 ] 0
 IGMLS  All_Acks [0 ] 0
-IGMLS  Data [37 ] 37
+IGMLS  Data [0 ] 0
 IGMLS  Data_Exclusive [0 ] 0
 IGMLS  L2_Replacement [0 ] 0
 
-IGMO  L1_GETS [3469 ] 3469
-IGMO  L1_GETX [1846 ] 1846
+IGMO  L1_GETS [0 ] 0
+IGMO  L1_GETX [0 ] 0
 IGMO  L1_PUTO [0 ] 0
 IGMO  L1_PUTX [0 ] 0
-IGMO  L1_PUTS_only [57 ] 57
+IGMO  L1_PUTS_only [0 ] 0
 IGMO  L1_PUTS [0 ] 0
 IGMO  Fwd_GETX [0 ] 0
 IGMO  Fwd_GETS [0 ] 0
 IGMO  Fwd_DMA [0 ] 0
 IGMO  Own_GETX [0 ] 0
 IGMO  ExtAck [0 ] 0
-IGMO  All_Acks [422217 ] 422217
-IGMO  Exclusive_Unblock [422217 ] 422217
+IGMO  All_Acks [0 ] 0
+IGMO  Exclusive_Unblock [0 ] 0
 IGMO  L2_Replacement [0 ] 0
 
 IGMIO  L1_GETS [0 ] 0
@@ -1357,7 +1282,7 @@ MM  Fwd_GETX [0 ] 0
 MM  Fwd_GETS [0 ] 0
 MM  Fwd_DMA [0 ] 0
 MM  Inv [0 ] 0
-MM  Exclusive_Unblock [1447 ] 1447
+MM  Exclusive_Unblock [0 ] 0
 MM  L2_Replacement [0 ] 0
 
 SS  L1_GETS [0 ] 0
@@ -1370,8 +1295,8 @@ SS  Fwd_GETX [0 ] 0
 SS  Fwd_GETS [0 ] 0
 SS  Fwd_DMA [0 ] 0
 SS  Inv [0 ] 0
-SS  Unblock [24 ] 24
-SS  L2_Replacement [1 ] 1
+SS  Unblock [0 ] 0
+SS  L2_Replacement [0 ] 0
 
 OO  L1_GETS [0 ] 0
 OO  L1_GETX [0 ] 0
@@ -1384,8 +1309,8 @@ OO  Fwd_GETS [0 ] 0
 OO  Fwd_DMA [0 ] 0
 OO  Inv [0 ] 0
 OO  Unblock [0 ] 0
-OO  Exclusive_Unblock [2720 ] 2720
-OO  L2_Replacement [90 ] 90
+OO  Exclusive_Unblock [0 ] 0
+OO  L2_Replacement [0 ] 0
 
 OLSS  L1_GETS [0 ] 0
 OLSS  L1_GETX [0 ] 0
@@ -1410,7 +1335,7 @@ OLSXS  Fwd_GETX [0 ] 0
 OLSXS  Fwd_GETS [0 ] 0
 OLSXS  Fwd_DMA [0 ] 0
 OLSXS  Inv [0 ] 0
-OLSXS  Unblock [13 ] 13
+OLSXS  Unblock [0 ] 0
 OLSXS  L2_Replacement [0 ] 0
 
 SLSS  L1_GETS [0 ] 0
@@ -1439,8 +1364,8 @@ OI  Writeback_Ack [0 ] 0
 OI  Writeback_Nack [0 ] 0
 OI  L2_Replacement [0 ] 0
 
-MI  L1_GETS [524 ] 524
-MI  L1_GETX [264 ] 264
+MI  L1_GETS [0 ] 0
+MI  L1_GETX [0 ] 0
 MI  L1_PUTO [0 ] 0
 MI  L1_PUTX [0 ] 0
 MI  L1_PUTS_only [0 ] 0
@@ -1448,7 +1373,7 @@ MI  L1_PUTS [0 ] 0
 MI  Fwd_GETX [0 ] 0
 MI  Fwd_GETS [0 ] 0
 MI  Fwd_DMA [0 ] 0
-MI  Writeback_Ack [1198971 ] 1198971
+MI  Writeback_Ack [0 ] 0
 MI  L2_Replacement [0 ] 0
 
 MII  L1_GETS [0 ] 0
@@ -1465,12 +1390,12 @@ OLSI  L1_GETS [0 ] 0
 OLSI  L1_GETX [0 ] 0
 OLSI  L1_PUTO [0 ] 0
 OLSI  L1_PUTX [0 ] 0
-OLSI  L1_PUTS_only [222 ] 222
-OLSI  L1_PUTS [4 ] 4
+OLSI  L1_PUTS_only [0 ] 0
+OLSI  L1_PUTS [0 ] 0
 OLSI  Fwd_GETX [0 ] 0
 OLSI  Fwd_GETS [0 ] 0
 OLSI  Fwd_DMA [0 ] 0
-OLSI  Writeback_Ack [2748 ] 2748
+OLSI  Writeback_Ack [0 ] 0
 OLSI  L2_Replacement [0 ] 0
 
 ILSI  L1_GETS [0 ] 0
@@ -1485,59 +1410,59 @@ ILSI  Writeback_Ack [0 ] 0
 ILSI  L2_Replacement [0 ] 0
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1633762
-  memory_reads: 1206708
-  memory_writes: 427032
-  memory_refreshes: 81124
-  memory_total_request_delays: 100270801
-  memory_delays_per_request: 61.3742
-  memory_delays_in_input_queue: 671540
-  memory_delays_behind_head_of_bank_queue: 41440167
-  memory_delays_stalled_at_head_of_bank_queue: 58159094
-  memory_stalls_for_bank_busy: 8934136
+  memory_total_requests: 2
+  memory_reads: 2
+  memory_writes: 0
+  memory_refreshes: 22
+  memory_total_request_delays: 31
+  memory_delays_per_request: 15.5
+  memory_delays_in_input_queue: 1
+  memory_delays_behind_head_of_bank_queue: 10
+  memory_delays_stalled_at_head_of_bank_queue: 20
+  memory_stalls_for_bank_busy: 20
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 14073572
-  memory_stalls_for_arbitration: 11978655
-  memory_stalls_for_bus: 16268659
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 0
+  memory_stalls_for_bus: 0
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 4121967
-  memory_stalls_for_read_read_turnaround: 2782105
-  accesses_per_bank: 51374  51312  51085  51181  51268  51561  51508  50825  51409  51217  51548  51127  51070  51087  50968  50678  51156  50861  51389  50919  50839  50944  50908  50859  51006  50629  50693  50438  51078  50705  51300  50820  
+  memory_stalls_for_read_write_turnaround: 0
+  memory_stalls_for_read_read_turnaround: 0
+  accesses_per_bank: 2  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  
 
  --- Directory ---
  - Event Counts -
-GETX [422222 ] 422222
-GETS [784499 ] 784499
-PUTX [1198972 ] 1198972
+GETX [0 ] 0
+GETS [2 ] 2
+PUTX [0 ] 0
 PUTO [0 ] 0
-PUTO_SHARERS [2748 ] 2748
+PUTO_SHARERS [0 ] 0
 Unblock [0 ] 0
-Last_Unblock [4961 ] 4961
-Exclusive_Unblock [1201742 ] 1201742
-Clean_Writeback [774677 ] 774677
-Dirty_Writeback [427041 ] 427041
-Memory_Data [1206704 ] 1206704
-Memory_Ack [427031 ] 427031
+Last_Unblock [0 ] 0
+Exclusive_Unblock [2 ] 2
+Clean_Writeback [0 ] 0
+Dirty_Writeback [0 ] 0
+Memory_Data [2 ] 2
+Memory_Ack [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
 Data [0 ] 0
 
  - Transitions -
-I  GETX [419482 ] 419482
-I  GETS [779538 ] 779538
+I  GETX [0 ] 0
+I  GETS [2 ] 2
 I  PUTX [0 ] 0
 I  PUTO [0 ] 0
 I  Memory_Data [0 ] 0
-I  Memory_Ack [420246 ] 420246
+I  Memory_Ack [0 ] 0
 I  DMA_READ [0 ] 0
 I  DMA_WRITE [0 ] 0
 
-S  GETX [2740 ] 2740
-S  GETS [4961 ] 4961
+S  GETX [0 ] 0
+S  GETS [0 ] 0
 S  PUTX [0 ] 0
 S  PUTO [0 ] 0
 S  Memory_Data [0 ] 0
-S  Memory_Ack [640 ] 640
+S  Memory_Ack [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
 
@@ -1553,9 +1478,9 @@ O  DMA_WRITE [0 ] 0
 
 M  GETX [0 ] 0
 M  GETS [0 ] 0
-M  PUTX [1198972 ] 1198972
+M  PUTX [0 ] 0
 M  PUTO [0 ] 0
-M  PUTO_SHARERS [2748 ] 2748
+M  PUTO_SHARERS [0 ] 0
 M  Memory_Data [0 ] 0
 M  Memory_Ack [0 ] 0
 M  DMA_READ [0 ] 0
@@ -1567,9 +1492,9 @@ IS  PUTX [0 ] 0
 IS  PUTO [0 ] 0
 IS  PUTO_SHARERS [0 ] 0
 IS  Unblock [0 ] 0
-IS  Exclusive_Unblock [779525 ] 779525
-IS  Memory_Data [779526 ] 779526
-IS  Memory_Ack [4016 ] 4016
+IS  Exclusive_Unblock [2 ] 2
+IS  Memory_Data [2 ] 2
+IS  Memory_Ack [0 ] 0
 IS  DMA_READ [0 ] 0
 IS  DMA_WRITE [0 ] 0
 
@@ -1579,9 +1504,9 @@ SS  PUTX [0 ] 0
 SS  PUTO [0 ] 0
 SS  PUTO_SHARERS [0 ] 0
 SS  Unblock [0 ] 0
-SS  Last_Unblock [4961 ] 4961
-SS  Memory_Data [4961 ] 4961
-SS  Memory_Ack [3 ] 3
+SS  Last_Unblock [0 ] 0
+SS  Memory_Data [0 ] 0
+SS  Memory_Ack [0 ] 0
 SS  DMA_READ [0 ] 0
 SS  DMA_WRITE [0 ] 0
 
@@ -1614,9 +1539,9 @@ MM  GETS [0 ] 0
 MM  PUTX [0 ] 0
 MM  PUTO [0 ] 0
 MM  PUTO_SHARERS [0 ] 0
-MM  Exclusive_Unblock [422217 ] 422217
-MM  Memory_Data [422217 ] 422217
-MM  Memory_Ack [2126 ] 2126
+MM  Exclusive_Unblock [0 ] 0
+MM  Memory_Data [0 ] 0
+MM  Memory_Ack [0 ] 0
 MM  DMA_READ [0 ] 0
 MM  DMA_WRITE [0 ] 0
 
@@ -1627,8 +1552,8 @@ MI  PUTX [0 ] 0
 MI  PUTO [0 ] 0
 MI  PUTO_SHARERS [0 ] 0
 MI  Unblock [0 ] 0
-MI  Clean_Writeback [772580 ] 772580
-MI  Dirty_Writeback [426390 ] 426390
+MI  Clean_Writeback [0 ] 0
+MI  Dirty_Writeback [0 ] 0
 MI  Memory_Data [0 ] 0
 MI  Memory_Ack [0 ] 0
 MI  DMA_READ [0 ] 0
@@ -1640,8 +1565,8 @@ MIS  PUTX [0 ] 0
 MIS  PUTO [0 ] 0
 MIS  PUTO_SHARERS [0 ] 0
 MIS  Unblock [0 ] 0
-MIS  Clean_Writeback [2097 ] 2097
-MIS  Dirty_Writeback [651 ] 651
+MIS  Clean_Writeback [0 ] 0
+MIS  Dirty_Writeback [0 ] 0
 MIS  Memory_Data [0 ] 0
 MIS  Memory_Ack [0 ] 0
 MIS  DMA_READ [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index 5944f2026..ac46137f1 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -1,74 +1,74 @@
-system.cpu7: completed 10000 read accesses @3869056
-system.cpu6: completed 10000 read accesses @3886426
-system.cpu4: completed 10000 read accesses @3898396
-system.cpu5: completed 10000 read accesses @3918286
-system.cpu0: completed 10000 read accesses @3919696
-system.cpu1: completed 10000 read accesses @3927286
-system.cpu2: completed 10000 read accesses @3929616
-system.cpu3: completed 10000 read accesses @3936396
-system.cpu5: completed 20000 read accesses @7713766
-system.cpu7: completed 20000 read accesses @7774726
-system.cpu4: completed 20000 read accesses @7795816
-system.cpu6: completed 20000 read accesses @7798926
-system.cpu1: completed 20000 read accesses @7805792
-system.cpu0: completed 20000 read accesses @7819976
-system.cpu2: completed 20000 read accesses @7850656
-system.cpu3: completed 20000 read accesses @7872096
-system.cpu5: completed 30000 read accesses @11623576
-system.cpu6: completed 30000 read accesses @11668436
-system.cpu0: completed 30000 read accesses @11699446
-system.cpu7: completed 30000 read accesses @11704516
-system.cpu4: completed 30000 read accesses @11718806
-system.cpu1: completed 30000 read accesses @11741606
-system.cpu3: completed 30000 read accesses @11767816
-system.cpu2: completed 30000 read accesses @11813276
-system.cpu5: completed 40000 read accesses @15522846
-system.cpu0: completed 40000 read accesses @15592626
-system.cpu6: completed 40000 read accesses @15619436
-system.cpu1: completed 40000 read accesses @15624516
-system.cpu4: completed 40000 read accesses @15630786
-system.cpu7: completed 40000 read accesses @15640616
-system.cpu3: completed 40000 read accesses @15655796
-system.cpu2: completed 40000 read accesses @15680896
-system.cpu5: completed 50000 read accesses @19438476
-system.cpu0: completed 50000 read accesses @19458866
-system.cpu1: completed 50000 read accesses @19542456
-system.cpu6: completed 50000 read accesses @19543746
-system.cpu4: completed 50000 read accesses @19568206
-system.cpu7: completed 50000 read accesses @19569526
-system.cpu3: completed 50000 read accesses @19594416
-system.cpu2: completed 50000 read accesses @19626796
-system.cpu5: completed 60000 read accesses @23331176
-system.cpu0: completed 60000 read accesses @23345146
-system.cpu6: completed 60000 read accesses @23379766
-system.cpu1: completed 60000 read accesses @23400806
-system.cpu4: completed 60000 read accesses @23475225
-system.cpu3: completed 60000 read accesses @23504027
-system.cpu7: completed 60000 read accesses @23511286
-system.cpu2: completed 60000 read accesses @23548006
-system.cpu5: completed 70000 read accesses @27140516
-system.cpu0: completed 70000 read accesses @27275896
-system.cpu1: completed 70000 read accesses @27288996
-system.cpu6: completed 70000 read accesses @27292846
-system.cpu7: completed 70000 read accesses @27386426
-system.cpu3: completed 70000 read accesses @27389056
-system.cpu4: completed 70000 read accesses @27433216
-system.cpu2: completed 70000 read accesses @27451236
-system.cpu5: completed 80000 read accesses @31034206
-system.cpu6: completed 80000 read accesses @31104766
-system.cpu1: completed 80000 read accesses @31179446
-system.cpu0: completed 80000 read accesses @31203676
-system.cpu3: completed 80000 read accesses @31246486
-system.cpu7: completed 80000 read accesses @31258446
-system.cpu2: completed 80000 read accesses @31320306
-system.cpu4: completed 80000 read accesses @31334426
-system.cpu5: completed 90000 read accesses @34995346
-system.cpu6: completed 90000 read accesses @35062566
-system.cpu3: completed 90000 read accesses @35112636
-system.cpu1: completed 90000 read accesses @35134786
-system.cpu7: completed 90000 read accesses @35159686
-system.cpu2: completed 90000 read accesses @35168476
-system.cpu0: completed 90000 read accesses @35169596
-system.cpu4: completed 90000 read accesses @35260086
-system.cpu6: completed 100000 read accesses @38939096
+system.cpu3: completed 10000 read accesses @323743
+system.cpu2: completed 10000 read accesses @336402
+system.cpu1: completed 10000 read accesses @338132
+system.cpu0: completed 10000 read accesses @340751
+system.cpu5: completed 10000 read accesses @341263
+system.cpu4: completed 10000 read accesses @346558
+system.cpu7: completed 10000 read accesses @346738
+system.cpu6: completed 10000 read accesses @348135
+system.cpu3: completed 20000 read accesses @670303
+system.cpu0: completed 20000 read accesses @670934
+system.cpu2: completed 20000 read accesses @675651
+system.cpu1: completed 20000 read accesses @679374
+system.cpu6: completed 20000 read accesses @683883
+system.cpu7: completed 20000 read accesses @684999
+system.cpu4: completed 20000 read accesses @688475
+system.cpu5: completed 20000 read accesses @691089
+system.cpu3: completed 30000 read accesses @1012754
+system.cpu2: completed 30000 read accesses @1013014
+system.cpu5: completed 30000 read accesses @1015303
+system.cpu0: completed 30000 read accesses @1018359
+system.cpu1: completed 30000 read accesses @1021563
+system.cpu4: completed 30000 read accesses @1024489
+system.cpu6: completed 30000 read accesses @1024945
+system.cpu7: completed 30000 read accesses @1026805
+system.cpu3: completed 40000 read accesses @1337640
+system.cpu4: completed 40000 read accesses @1353749
+system.cpu5: completed 40000 read accesses @1355921
+system.cpu2: completed 40000 read accesses @1358297
+system.cpu0: completed 40000 read accesses @1365879
+system.cpu7: completed 40000 read accesses @1368402
+system.cpu6: completed 40000 read accesses @1369510
+system.cpu1: completed 40000 read accesses @1372174
+system.cpu3: completed 50000 read accesses @1687319
+system.cpu4: completed 50000 read accesses @1694511
+system.cpu7: completed 50000 read accesses @1696243
+system.cpu2: completed 50000 read accesses @1699794
+system.cpu5: completed 50000 read accesses @1700188
+system.cpu6: completed 50000 read accesses @1703368
+system.cpu0: completed 50000 read accesses @1704599
+system.cpu1: completed 50000 read accesses @1716501
+system.cpu4: completed 60000 read accesses @2030412
+system.cpu3: completed 60000 read accesses @2034929
+system.cpu2: completed 60000 read accesses @2036378
+system.cpu7: completed 60000 read accesses @2036726
+system.cpu0: completed 60000 read accesses @2038738
+system.cpu5: completed 60000 read accesses @2046852
+system.cpu1: completed 60000 read accesses @2050784
+system.cpu6: completed 60000 read accesses @2058109
+system.cpu3: completed 70000 read accesses @2359493
+system.cpu4: completed 70000 read accesses @2365063
+system.cpu2: completed 70000 read accesses @2371739
+system.cpu0: completed 70000 read accesses @2373666
+system.cpu7: completed 70000 read accesses @2373767
+system.cpu5: completed 70000 read accesses @2395804
+system.cpu1: completed 70000 read accesses @2404686
+system.cpu6: completed 70000 read accesses @2406335
+system.cpu2: completed 80000 read accesses @2701352
+system.cpu7: completed 80000 read accesses @2705729
+system.cpu3: completed 80000 read accesses @2707362
+system.cpu4: completed 80000 read accesses @2711169
+system.cpu0: completed 80000 read accesses @2718197
+system.cpu1: completed 80000 read accesses @2736476
+system.cpu6: completed 80000 read accesses @2746379
+system.cpu5: completed 80000 read accesses @2751740
+system.cpu2: completed 90000 read accesses @3041770
+system.cpu3: completed 90000 read accesses @3048359
+system.cpu7: completed 90000 read accesses @3049406
+system.cpu0: completed 90000 read accesses @3052026
+system.cpu4: completed 90000 read accesses @3061142
+system.cpu1: completed 90000 read accesses @3064341
+system.cpu6: completed 90000 read accesses @3079121
+system.cpu5: completed 90000 read accesses @3089679
+system.cpu2: completed 100000 read accesses @3377485
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 9d1af9231..be3549bde 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:43:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:54
-M5 executing on SC2B0617
+M5 compiled Aug 20 2010 12:10:28
+M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
+M5 started Aug 20 2010 12:10:38
+M5 executing on SC2B0629
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 38939096 because maximum number of loads reached
+Exiting @ tick 3377485 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index 91d2150b0..b18cfb37f 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 346548                       # Number of bytes of host memory used
-host_seconds                                   491.59                       # Real time elapsed on the host
-host_tick_rate                                  79210                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 341856                       # Number of bytes of host memory used
+host_seconds                                    29.56                       # Real time elapsed on the host
+host_tick_rate                                 114257                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.038939                       # Number of seconds simulated
-sim_ticks                                    38939096                       # Number of ticks simulated
+sim_seconds                                  0.003377                       # Number of seconds simulated
+sim_ticks                                     3377485                       # Number of ticks simulated
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99650                       # number of read accesses completed
-system.cpu0.num_writes                          53465                       # number of write accesses completed
+system.cpu0.num_reads                           99116                       # number of read accesses completed
+system.cpu0.num_writes                          53019                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99886                       # number of read accesses completed
-system.cpu1.num_writes                          53908                       # number of write accesses completed
+system.cpu1.num_reads                           99151                       # number of read accesses completed
+system.cpu1.num_writes                          53486                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99727                       # number of read accesses completed
-system.cpu2.num_writes                          53685                       # number of write accesses completed
+system.cpu2.num_reads                          100000                       # number of read accesses completed
+system.cpu2.num_writes                          53183                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99743                       # number of read accesses completed
-system.cpu3.num_writes                          53374                       # number of write accesses completed
+system.cpu3.num_reads                           99632                       # number of read accesses completed
+system.cpu3.num_writes                          54001                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99344                       # number of read accesses completed
-system.cpu4.num_writes                          53842                       # number of write accesses completed
+system.cpu4.num_reads                           99186                       # number of read accesses completed
+system.cpu4.num_writes                          53590                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99988                       # number of read accesses completed
-system.cpu5.num_writes                          53434                       # number of write accesses completed
+system.cpu5.num_reads                           98345                       # number of read accesses completed
+system.cpu5.num_writes                          53268                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                          100000                       # number of read accesses completed
-system.cpu6.num_writes                          54115                       # number of write accesses completed
+system.cpu6.num_reads                           99155                       # number of read accesses completed
+system.cpu6.num_writes                          53749                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99701                       # number of read accesses completed
-system.cpu7.num_writes                          53854                       # number of write accesses completed
+system.cpu7.num_reads                           99644                       # number of read accesses completed
+system.cpu7.num_writes                          53528                       # number of write accesses completed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index e235c7a0d..cffe74459 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -522,9 +513,10 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
+children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -536,7 +528,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
@@ -549,7 +540,6 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.L1IcacheMemory
@@ -562,7 +552,6 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.L1IcacheMemory
@@ -575,7 +564,6 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.L1IcacheMemory
@@ -588,7 +576,6 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.L1IcacheMemory
@@ -601,7 +588,6 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.L1IcacheMemory
@@ -614,7 +600,6 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.L1IcacheMemory
@@ -627,7 +612,6 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.L1IcacheMemory
@@ -638,6 +622,14 @@ version=7
 physMemPort=system.physmem.port[7]
 port=system.cpu7.test
 
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index bfdf3cf97..7b2bdba27 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:32:59
+Real time: Aug/20/2010 12:14:59
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 309
-Elapsed_time_in_minutes: 5.15
-Elapsed_time_in_hours: 0.0858333
-Elapsed_time_in_days: 0.00357639
+Elapsed_time_in_seconds: 26
+Elapsed_time_in_minutes: 0.433333
+Elapsed_time_in_hours: 0.00722222
+Elapsed_time_in_days: 0.000300926
 
-Virtual_time_in_seconds: 308.79
-Virtual_time_in_minutes: 5.1465
-Virtual_time_in_hours:   0.085775
-Virtual_time_in_days:    0.00357396
+Virtual_time_in_seconds: 25.78
+Virtual_time_in_minutes: 0.429667
+Virtual_time_in_hours:   0.00716111
+Virtual_time_in_days:    0.00029838
 
-Ruby_current_time: 39098820
+Ruby_current_time: 2583072
 Ruby_start_time: 0
-Ruby_cycles: 39098820
+Ruby_cycles: 2583072
 
-mbytes_resident: 35.832
-mbytes_total: 338
-resident_ratio: 0.106035
+mbytes_resident: 32.8789
+mbytes_total: 333.961
+resident_ratio: 0.0984747
 
-ruby_cycles_executed: [ 39098821 39098821 39098821 39098821 39098821 39098821 39098821 39098821 ]
+ruby_cycles_executed: [ 2583073 2583073 2583073 2583073 2583073 2583073 2583073 2583073 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -67,35 +67,31 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1222292 average: 15.9992 | standard deviation: 0.0900883 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1222172 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1202451 average: 1.98763 | standard deviation: 0.110552 | 0 14880 1187571 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 19010 count: 1222164 average: 4094.58 | standard deviation: 4593.48 | 880 14265 26585 29256 28185 35200 38945 38659 33785 30463 32498 30366 25971 24412 21952 21617 19095 18024 17874 15039 15394 14747 15001 13923 12605 13752 13676 13169 13327 12339 13422 12918 12919 13474 12199 13007 13169 13505 13304 11996 13422 13587 13234 13635 13004 14282 13902 14329 14720 13221 14049 14170 14758 14115 12697 14009 13907 13300 13036 12016 12717 11721 11409 11153 9488 9656 9446 9016 8223 7027 7249 6997 6100 5734 4930 5022 4406 3930 3733 3114 2971 2616 2611 2119 1803 1802 1613 1355 1170 1067 944 845 751 691 552 470 444 408 329 301 262 258 185 172 148 120 124 92 81 69 53 55 44 44 30 28 27 14 17 12 18 15 11 2 4 4 2 4 3 3 1 2 5 2 3 0 2 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 19010 count: 794491 average: 4097.54 | standard deviation: 6162.87 | 574 9241 17391 18989 18344 22795 25252 25174 21924 19783 21202 19508 16884 15814 14312 14027 12415 11711 11609 9835 10025 9594 9689 8982 8157 8925 8922 8521 8688 7983 8759 8333 8336 8819 7995 8480 8556 8845 8615 7796 8730 8855 8537 8853 8467 9277 9000 9350 9661 8645 9005 9134 9600 9253 8268 9089 9151 8760 8479 7801 8302 7675 7466 7212 6197 6318 6086 5880 5353 4602 4740 4503 3963 3713 3209 3232 2853 2538 2406 2050 1897 1727 1714 1378 1169 1186 1040 885 771 692 593 561 512 447 356 315 291 270 228 178 173 164 112 110 107 78 80 64 60 45 32 33 25 32 19 17 17 10 10 9 15 10 9 1 0 4 2 3 3 3 1 2 4 2 2 0 1 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 17500 count: 427673 average: 4089.1 | standard deviation: 2956.01 | 306 5024 9194 10267 9841 12405 13693 13485 11861 10680 11296 10858 9087 8598 7640 7590 6680 6313 6265 5204 5369 5153 5312 4941 4448 4827 4754 4648 4639 4356 4663 4585 4583 4655 4204 4527 4613 4660 4689 4200 4692 4732 4697 4782 4537 5005 4902 4979 5059 4576 5044 5036 5158 4862 4429 4920 4756 4540 4557 4215 4415 4046 3943 3941 3291 3338 3360 3136 2870 2425 2509 2494 2137 2021 1721 1790 1553 1392 1327 1064 1074 889 897 741 634 616 573 470 399 375 351 284 239 244 196 155 153 138 101 123 89 94 73 62 41 42 44 28 21 24 21 22 19 12 11 11 10 4 7 3 3 5 2 1 4 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 2 count: 182 average:     2 | standard deviation: 0 | 0 0 182 ]
-miss_latency_L2Cache: [binsize: 128 max: 14636 count: 3318 average: 4304.23 | standard deviation: 3025.46 | 103 34 41 46 41 81 42 74 81 73 78 75 61 77 70 75 60 60 65 39 55 43 40 38 39 32 32 48 28 32 32 36 39 45 44 33 36 26 37 48 36 41 30 24 38 43 29 40 38 35 40 31 38 37 31 37 33 39 44 32 40 44 29 34 28 25 23 25 29 16 21 30 15 15 27 16 21 11 14 9 12 7 9 5 9 3 8 4 3 5 3 2 4 1 2 2 2 3 0 0 2 0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 19010 count: 1212227 average: 4096.98 | standard deviation: 4615.1 | 1 14081 26393 29048 27995 34881 38752 38403 33550 30252 32309 30196 25812 24248 21814 21475 18947 17878 17734 14925 15278 14631 14881 13820 12515 13647 13587 13028 13222 12241 13320 12827 12817 13368 12081 12904 13058 13415 13183 11879 13322 13475 13134 13541 12888 14167 13803 14219 14601 13102 13935 14061 14647 13997 12600 13894 13816 13186 12931 11939 12620 11639 11321 11073 9422 9602 9381 8954 8158 6979 7199 6945 6056 5700 4877 4986 4372 3908 3705 3092 2944 2601 2590 2102 1788 1793 1593 1347 1162 1060 938 838 747 688 548 466 442 405 327 298 258 258 185 170 147 119 122 90 81 69 53 55 44 44 29 28 27 14 16 12 18 15 11 2 4 4 2 4 3 3 1 2 5 2 3 0 2 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 128 max: 15204 count: 6437 average: 3651.95 | standard deviation: 2983.45 | 594 150 151 162 149 238 151 182 154 138 111 95 98 87 68 67 88 86 75 75 61 73 80 65 51 73 57 93 77 66 70 55 63 61 74 70 75 64 84 69 64 71 70 70 78 72 70 70 81 84 74 78 73 81 66 78 58 75 61 45 57 38 59 46 38 29 42 37 36 32 29 22 29 19 26 20 13 11 14 13 15 8 12 12 6 6 12 4 5 2 3 5 0 2 2 2 0 0 2 3 2 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 6437
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_first_response_to_completion: [binsize: 4 max: 579 count: 8 average: 340.25 | standard deviation: 178.281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-imcomplete_dir_Times: 1212219
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 120 average:     2 | standard deviation: 0 | 0 0 120 ]
-miss_latency_LD_L2Cache: [binsize: 128 max: 13736 count: 2082 average: 4302.16 | standard deviation: 3042.21 | 68 21 23 26 19 57 29 48 59 48 48 54 33 52 45 47 40 32 38 26 31 29 29 20 20 14 22 33 16 20 17 21 22 25 28 22 25 17 22 27 22 28 18 17 21 25 20 25 26 24 21 19 24 25 25 22 21 25 31 17 18 28 17 25 16 15 13 18 18 10 16 16 13 10 16 14 13 6 8 4 9 5 7 5 2 1 3 4 3 3 2 1 3 1 2 2 1 2 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_Directory: [binsize: 128 max: 19010 count: 788140 average: 4099.76 | standard deviation: 6200.71 | 0 9117 17280 18869 18227 22592 25126 25009 21768 19647 21089 19389 16788 15698 14217 13930 12324 11625 11524 9759 9953 9516 9610 8921 8109 8862 8864 8436 8621 7916 8703 8275 8280 8751 7918 8410 8481 8787 8526 7730 8661 8781 8481 8793 8398 9211 8939 9284 9582 8567 8942 9064 9531 9173 8203 9011 9100 8685 8403 7754 8242 7617 7411 7165 6158 6282 6047 5837 5310 4567 4708 4472 3926 3691 3172 3205 2830 2524 2387 2037 1875 1716 1702 1365 1164 1181 1029 878 763 687 589 557 509 445 352 312 290 268 226 176 171 164 112 110 106 77 79 63 60 45 32 33 25 32 19 17 17 10 10 9 15 10 9 1 0 4 2 3 3 3 1 2 4 2 2 0 1 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 13609 count: 4149 average: 3690.67 | standard deviation: 3008.16 | 386 103 88 94 98 146 97 117 97 88 65 65 63 64 50 50 51 54 47 50 41 49 50 41 28 49 36 52 51 47 39 37 34 43 49 48 50 41 67 39 47 46 38 43 48 41 41 41 53 54 42 51 45 55 40 56 30 50 45 30 42 30 38 22 23 21 26 25 25 25 16 15 24 12 21 13 10 8 11 9 13 6 5 8 3 4 8 3 5 2 2 3 0 1 2 1 0 0 2 2 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 62 average:     2 | standard deviation: 0 | 0 0 62 ]
-miss_latency_ST_L2Cache: [binsize: 128 max: 14636 count: 1236 average: 4307.73 | standard deviation: 2998.25 | 35 13 18 20 22 24 13 26 22 25 30 21 28 25 25 28 20 28 27 13 24 14 11 18 19 18 10 15 12 12 15 15 17 20 16 11 11 9 15 21 14 13 12 7 17 18 9 15 12 11 19 12 14 12 6 15 12 14 13 15 22 16 12 9 12 10 10 7 11 6 5 14 2 5 11 2 8 5 6 5 3 2 2 0 7 2 5 0 0 2 1 1 1 0 0 0 1 1 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 128 max: 17500 count: 424087 average: 4091.79 | standard deviation: 2955.53 | 1 4964 9113 10179 9768 12289 13626 13394 11782 10605 11220 10807 9024 8550 7597 7545 6623 6253 6210 5166 5325 5115 5271 4899 4406 4785 4723 4592 4601 4325 4617 4552 4537 4617 4163 4494 4577 4628 4657 4149 4661 4694 4653 4748 4490 4956 4864 4935 5019 4535 4993 4997 5116 4824 4397 4883 4716 4501 4528 4185 4378 4022 3910 3908 3264 3320 3334 3117 2848 2412 2491 2473 2130 2009 1705 1781 1542 1384 1318 1055 1069 885 888 737 624 612 564 469 399 373 349 281 238 243 196 154 152 137 101 122 87 94 73 60 41 42 43 27 21 24 21 22 19 12 10 11 10 4 6 3 3 5 2 1 4 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15204 count: 2288 average: 3581.73 | standard deviation: 2937.45 | 208 47 63 68 51 92 54 65 57 50 46 30 35 23 18 17 37 32 28 25 20 24 30 24 23 24 21 41 26 19 31 18 29 18 25 22 25 23 17 30 17 25 32 27 30 31 29 29 28 30 32 27 28 26 26 22 28 25 16 15 15 8 21 24 15 8 16 12 11 7 13 7 5 7 5 7 3 3 3 4 2 2 7 4 3 2 4 1 0 0 1 2 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 8 max: 1010 count: 1202436 average: 32.3679 | standard deviation: 136.165 | 1145435 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 8 max: 1010 count: 782221 average: 32.3974 | standard deviation: 136.229 | 745119 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 8 max: 825 count: 420215 average: 32.313 | standard deviation: 136.046 | 400316 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 1145435 average:     2 | standard deviation: 0 | 0 0 1145435 ]
+miss_latency_Directory: [binsize: 2 max: 369 count: 2 average:   314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache_wCC: [binsize: 8 max: 1010 count: 56999 average: 642.622 | standard deviation: 13.675 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 8 max: 887 count: 6 average: 764.333 | standard deviation: 101.837 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_wCC_Times: 56993
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_first_response_to_completion: [binsize: 2 max: 369 count: 2 average:   314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 745119 average:     2 | standard deviation: 0 | 0 0 745119 ]
+miss_latency_LD_Directory: [binsize: 2 max: 369 count: 2 average:   314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 8 max: 1010 count: 37100 average: 642.885 | standard deviation: 5.20071 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 400316 average:     2 | standard deviation: 0 | 0 0 400316 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 8 max: 825 count: 19899 average: 642.132 | standard deviation: 22.02 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -125,322 +121,244 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 308
+user_time: 25
 system_time: 0
-page_reclaims: 10424
+page_reclaims: 9519
 page_faults: 0
 swaps: 0
-block_inputs: 8
+block_inputs: 16
 block_outputs: 0
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 7329210 58633680
-total_msg_count_Response_Data: 3644058 262372176
-total_msg_count_ResponseL2hit_Data: 2832 203904
-total_msg_count_ResponseLocal_Data: 13539 974808
-total_msg_count_Response_Control: 11253 90024
-total_msg_count_Writeback_Data: 4939377 355635144
-total_msg_count_Writeback_Control: 2366358 18930864
-total_msg_count_Broadcast_Control: 18330105 146640840
-total_msg_count_Persistent_Control: 16213440 129707520
-total_msgs: 52850172 total_bytes: 973188960
+total_msg_count_Request_Control: 342090 2736720
+total_msg_count_Response_Data: 170931 12307032
+total_msg_count_ResponseLocal_Data: 48 3456
+total_msg_count_Response_Control: 170943 1367544
+total_msg_count_Broadcast_Control: 855225 6841800
+total_msg_count_Persistent_Control: 2279000 18232000
+total_msgs: 3818237 total_bytes: 41488552
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.166841
-  links_utilized_percent_switch_0_link_0: 0.104259 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.229422 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Response_Data: 152823 11003256 [ 0 0 0 0 152823 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 130 9360 [ 0 0 0 0 130 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 597 42984 [ 0 0 0 0 597 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Broadcast_Control: 1068453 8547624 [ 0 1068453 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 153554 1228432 [ 0 153554 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 261 18792 [ 0 0 0 0 261 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 583 41976 [ 0 0 0 0 583 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 490 3920 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 153061 11020392 [ 0 0 0 0 153061 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Broadcast_Control: 153554 1228432 [ 0 153554 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Persistent_Control: 101285 810280 [ 0 0 0 101285 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.151672
+  links_utilized_percent_switch_0_link_0: 0.110312 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.193032 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.166478
-  links_utilized_percent_switch_1_link_0: 0.104145 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.228811 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Response_Data: 152394 10972368 [ 0 0 0 0 152394 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 533 38376 [ 0 0 0 0 533 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Data: 64 4608 [ 0 0 0 0 64 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Broadcast_Control: 1068894 8551152 [ 0 1068894 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 153113 1224904 [ 0 153113 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 251 18072 [ 0 0 0 0 251 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 535 38520 [ 0 0 0 0 535 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 457 3656 [ 0 0 0 0 457 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 152654 10991088 [ 0 0 0 0 152654 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Broadcast_Control: 153113 1224904 [ 0 153113 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Persistent_Control: 101607 812856 [ 0 0 0 101607 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.151704
+  links_utilized_percent_switch_1_link_0: 0.11032 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.193088 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Persistent_Control: 14242 113936 [ 0 0 0 14242 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.16592
-  links_utilized_percent_switch_2_link_0: 0.103987 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.227854 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Response_Data: 151660 10919520 [ 0 0 0 0 151660 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 104 7488 [ 0 0 0 0 104 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 582 41904 [ 0 0 0 0 582 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Data: 145 10440 [ 0 0 0 0 145 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Broadcast_Control: 1069512 8556096 [ 0 1069512 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 152495 1219960 [ 0 152495 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 242 17424 [ 0 0 0 0 242 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 562 40464 [ 0 0 0 0 562 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 469 3752 [ 0 0 0 0 469 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 152024 10945728 [ 0 0 0 0 152024 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Broadcast_Control: 152495 1219960 [ 0 152495 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Persistent_Control: 100853 806824 [ 0 0 0 100853 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.151685
+  links_utilized_percent_switch_2_link_0: 0.110312 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.193057 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 7120 512640 [ 0 0 0 0 7120 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.165833
-  links_utilized_percent_switch_3_link_0: 0.103949 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.227717 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Response_Data: 151505 10908360 [ 0 0 0 0 151505 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 99 7128 [ 0 0 0 0 99 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 554 39888 [ 0 0 0 0 554 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Broadcast_Control: 1069661 8557288 [ 0 1069661 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 152346 1218768 [ 0 152346 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 249 17928 [ 0 0 0 0 249 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 591 42552 [ 0 0 0 0 591 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 505 4040 [ 0 0 0 0 505 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 151837 10932264 [ 0 0 0 0 151837 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Broadcast_Control: 152346 1218768 [ 0 152346 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Persistent_Control: 101401 811208 [ 0 0 0 101401 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_3: 0.151691
+  links_utilized_percent_switch_3_link_0: 0.110313 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.193069 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Broadcast_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0.165882
-  links_utilized_percent_switch_4_link_0: 0.103963 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 0.227802 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_4_link_0_Response_Data: 151444 10903968 [ 0 0 0 0 151444 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 564 40608 [ 0 0 0 0 564 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Data: 257 18504 [ 0 0 0 0 257 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Broadcast_Control: 1069606 8556848 [ 0 1069606 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 152401 1219208 [ 0 152401 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 254 18288 [ 0 0 0 0 254 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 561 40392 [ 0 0 0 0 561 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 468 3744 [ 0 0 0 0 468 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 151929 10938888 [ 0 0 0 0 151929 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Broadcast_Control: 152401 1219208 [ 0 152401 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Persistent_Control: 101391 811128 [ 0 0 0 101391 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_4: 0.1517
+  links_utilized_percent_switch_4_link_0: 0.110316 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0.193084 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Broadcast_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0.166348
-  links_utilized_percent_switch_5_link_0: 0.104099 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.228597 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_5_link_0_Response_Data: 151938 10939536 [ 0 0 0 0 151938 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 115 8280 [ 0 0 0 0 115 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 568 40896 [ 0 0 0 0 568 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Broadcast_Control: 1069072 8552576 [ 0 1069072 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 152935 1223480 [ 0 152935 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 245 17640 [ 0 0 0 0 245 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 560 40320 [ 0 0 0 0 560 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 466 3728 [ 0 0 0 0 466 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 152466 10977552 [ 0 0 0 0 152466 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Broadcast_Control: 152935 1223480 [ 0 152935 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Persistent_Control: 101798 814384 [ 0 0 0 101798 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_5: 0.151686
+  links_utilized_percent_switch_5_link_0: 0.110312 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.193059 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 7119 512568 [ 0 0 0 0 7119 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0.166154
-  links_utilized_percent_switch_6_link_0: 0.104058 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 0.22825 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_6_link_0_Response_Data: 151673 10920456 [ 0 0 0 0 151673 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 559 40248 [ 0 0 0 0 559 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Data: 418 30096 [ 0 0 0 0 418 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Broadcast_Control: 1069234 8553872 [ 0 1069234 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 152773 1222184 [ 0 152773 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 215 15480 [ 0 0 0 0 215 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 570 41040 [ 0 0 0 0 570 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 469 3752 [ 0 0 0 0 469 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 152302 10965744 [ 0 0 0 0 152302 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Broadcast_Control: 152773 1222184 [ 0 152773 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Persistent_Control: 101062 808496 [ 0 0 0 101062 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_6: 0.151673
+  links_utilized_percent_switch_6_link_0: 0.110309 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 0.193038 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 7125 57000 [ 0 0 0 0 7125 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0.165861
-  links_utilized_percent_switch_7_link_0: 0.10396 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 0.227762 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_7_link_0_Response_Data: 151248 10889856 [ 0 0 0 0 151248 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 125 9000 [ 0 0 0 0 125 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 556 40032 [ 0 0 0 0 556 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Data: 459 33048 [ 0 0 0 0 459 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Broadcast_Control: 1069617 8556936 [ 0 1069617 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 152390 1219120 [ 0 152390 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 212 15264 [ 0 0 0 0 212 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 551 39672 [ 0 0 0 0 551 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 420 3360 [ 0 0 0 0 420 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 151967 10941624 [ 0 0 0 0 151967 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Broadcast_Control: 152390 1219120 [ 0 152390 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Persistent_Control: 101275 810200 [ 0 0 0 101275 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_7: 0.151662
+  links_utilized_percent_switch_7_link_0: 0.110309 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 0.193014 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 7121 512712 [ 0 0 0 0 7121 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 0.5836
-  links_utilized_percent_switch_8_link_0: 0.415632 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 0.751568 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 1222007 9776056 [ 0 1222007 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Response_Control: 3735 29880 [ 0 0 0 0 3735 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 1218239 87713208 [ 0 0 0 0 1218239 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 566 40752 [ 0 0 0 0 566 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 944 67968 [ 0 0 0 0 944 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Data: 428184 30829248 [ 0 0 0 0 428184 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 788775 6310200 [ 0 0 0 0 788775 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 0.110331
+  links_utilized_percent_switch_8_link_0: 0.110299 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 0.110363 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 2
 switch_9_outlinks: 2
-links_utilized_percent_switch_9: 0.804022
-  links_utilized_percent_switch_9_link_0: 0.212855 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 1.39519 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Data: 426377 30699144 [ 0 0 0 0 426377 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 788780 6310240 [ 0 0 0 0 788780 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 1212191 87277752 [ 0 0 0 0 1212191 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Data: 35 2520 [ 0 0 0 0 35 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 0.0413841
+  links_utilized_percent_switch_9_link_0: 0.0827334 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 3.48422e-05 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
 
 switch_10_inlinks: 10
 switch_10_outlinks: 10
-links_utilized_percent_switch_10: 0.573996
-  links_utilized_percent_switch_10_link_0: 0.404083 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_1: 0.403587 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_2: 0.40305 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_3: 0.402828 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_4: 0.402885 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_5: 0.40338 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_6: 0.403308 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_7: 0.40289 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_8: 1.66253 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_10_link_9: 0.851422 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_10_link_0_Response_Data: 152823 11003256 [ 0 0 0 0 152823 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 130 9360 [ 0 0 0 0 130 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 597 42984 [ 0 0 0 0 597 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Writeback_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Broadcast_Control: 1068453 8547624 [ 0 1068453 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_0_Persistent_Control: 709387 5675096 [ 0 0 0 709387 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Data: 152394 10972368 [ 0 0 0 0 152394 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 533 38376 [ 0 0 0 0 533 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Writeback_Data: 64 4608 [ 0 0 0 0 64 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Broadcast_Control: 1068894 8551152 [ 0 1068894 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_1_Persistent_Control: 709065 5672520 [ 0 0 0 709065 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Response_Data: 151660 10919520 [ 0 0 0 0 151660 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 104 7488 [ 0 0 0 0 104 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 582 41904 [ 0 0 0 0 582 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Writeback_Data: 145 10440 [ 0 0 0 0 145 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Broadcast_Control: 1069512 8556096 [ 0 1069512 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_2_Persistent_Control: 709819 5678552 [ 0 0 0 709819 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Data: 151505 10908360 [ 0 0 0 0 151505 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 99 7128 [ 0 0 0 0 99 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 554 39888 [ 0 0 0 0 554 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Writeback_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Broadcast_Control: 1069661 8557288 [ 0 1069661 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_3_Persistent_Control: 709271 5674168 [ 0 0 0 709271 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Response_Data: 151444 10903968 [ 0 0 0 0 151444 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 564 40608 [ 0 0 0 0 564 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Writeback_Data: 257 18504 [ 0 0 0 0 257 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Broadcast_Control: 1069606 8556848 [ 0 1069606 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_4_Persistent_Control: 709281 5674248 [ 0 0 0 709281 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Response_Data: 151938 10939536 [ 0 0 0 0 151938 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 115 8280 [ 0 0 0 0 115 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 568 40896 [ 0 0 0 0 568 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Writeback_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Broadcast_Control: 1069072 8552576 [ 0 1069072 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_5_Persistent_Control: 708874 5670992 [ 0 0 0 708874 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Data: 151673 10920456 [ 0 0 0 0 151673 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 559 40248 [ 0 0 0 0 559 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Writeback_Data: 418 30096 [ 0 0 0 0 418 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Broadcast_Control: 1069234 8553872 [ 0 1069234 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_6_Persistent_Control: 709610 5676880 [ 0 0 0 709610 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Data: 151248 10889856 [ 0 0 0 0 151248 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 125 9000 [ 0 0 0 0 125 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 556 40032 [ 0 0 0 0 556 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Writeback_Data: 459 33048 [ 0 0 0 0 459 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Broadcast_Control: 1069617 8556936 [ 0 1069617 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_7_Persistent_Control: 709397 5675176 [ 0 0 0 709397 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Request_Control: 1222007 9776056 [ 0 1222007 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Response_Control: 3735 29880 [ 0 0 0 0 3735 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Writeback_Data: 1218239 87713208 [ 0 0 0 0 1218239 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_8_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Response_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Data: 426377 30699144 [ 0 0 0 0 426377 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Writeback_Control: 788780 6310240 [ 0 0 0 0 788780 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_10_link_9_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_10: 0.408158
+  links_utilized_percent_switch_10_link_0: 0.413678 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 0.413713 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 0.413678 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 0.41368 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 0.413693 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 0.413678 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 0.413664 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 0.413664 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 0.441198 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 0.330933 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Persistent_Control: 99708 797664 [ 0 0 0 99708 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -451,203 +369,203 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 153555
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 153555
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 7125
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 7125
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.1174%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.8826%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   64.9965%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   35.0035%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   153555    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   7125    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [99079 99634 99062 99037 100002 99633 99065 99000 ] 794512
+Load [97598 97330 96960 97500 100000 98829 96777 97237 ] 782231
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [53348 53317 53734 53376 53574 53502 53455 53372 ] 427678
+Store [52430 52106 52281 52110 53664 53487 51846 52295 ] 420219
 Atomic [0 0 0 0 0 0 0 0 ] 0
-L1_Replacement [2549788 2558433 2553840 2548163 2566926 2559538 2551293 2548476 ] 20436457
-Data_Shared [325 321 306 321 323 299 309 317 ] 2521
-Data_Owner [97 90 104 115 101 92 97 120 ] 816
-Data_All_Tokens [151975 152521 152360 151952 153130 152719 152085 151906 ] 1218648
-Ack [1 1 3 1 3 3 2 1 ] 15
-Ack_All_Tokens [1 1 0 0 1 2 1 0 ] 6
+L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+Data_Shared [0 0 0 0 0 0 0 0 ] 0
+Data_Owner [6 6 3 2 1 3 5 4 ] 30
+Data_All_Tokens [7119 7118 7120 7121 7123 7123 7119 7120 ] 56963
+Ack [0 1 1 1 0 0 1 2 ] 6
+Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11
 Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETX [374278 374305 373891 374249 374052 374120 374165 374252 ] 2993312
+Transient_Local_GETX [17379 17433 17386 17429 17409 17431 17418 17436 ] 139321
 Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETS [695328 694766 695342 695367 694400 694774 695344 695409 ] 5560730
+Transient_Local_GETS [32507 32455 32504 32461 32481 32457 32470 32449 ] 259784
 Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-Transient_Local_GETS_Last_Token [0 1 1 1 1 0 3 0 ] 7
-Persistent_GETX [124790 124771 124739 124760 124868 124800 124686 124679 ] 998093
-Persistent_GETS [231798 231640 232019 231915 231752 231656 232127 231872 ] 1854779
-Persistent_GETS_Last_Token [1 0 0 0 0 0 1 2 ] 4
-Own_Lock_or_Unlock [454083 454261 453914 453997 454052 454216 453858 454119 ] 3632500
-Request_Timeout [987948 1003569 995376 995086 995661 991836 987483 990404 ] 7947363
-Use_TimeoutStarverX [13 14 10 10 3 1 10 6 ] 67
-Use_TimeoutStarverS [29 30 20 25 5 9 20 17 ] 155
-Use_TimeoutNoStarvers [151934 152478 152330 151916 153120 152711 152056 151882 ] 1218427
+Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+Persistent_GETX [19681 19967 19851 19972 19399 19393 19734 19360 ] 157357
+Persistent_GETS [36732 37056 37006 37152 36090 36049 36638 36016 ] 292739
+Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+Own_Lock_or_Unlock [57537 56927 57093 56826 58461 58508 57578 58574 ] 461504
+Request_Timeout [7147 7226 7147 7140 7122 7468 7539 7333 ] 58122
+Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123
+Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177
+Use_TimeoutNoStarvers [7105 7073 7098 7046 7123 7109 6997 7123 ] 56674
 Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
-NP  Load [98846 99418 98841 98814 99785 99416 98856 98777 ] 792753
+NP  Load [2 2 1 2 2 2 2 1 ] 14
 NP  Ifetch [0 0 0 0 0 0 0 0 ] 0
-NP  Store [53244 53182 53579 53256 53436 53391 53317 53247 ] 426652
+NP  Store [0 0 1 0 0 0 0 1 ] 2
 NP  Atomic [0 0 0 0 0 0 0 0 ] 0
 NP  Data_Shared [0 0 0 0 0 0 0 0 ] 0
-NP  Data_Owner [0 1 0 0 0 0 0 0 ] 1
-NP  Data_All_Tokens [0 0 0 1 0 0 0 0 ] 1
-NP  Ack [0 1 2 0 1 2 0 0 ] 6
+NP  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+NP  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+NP  Ack [0 0 0 0 0 0 0 0 ] 0
 NP  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-NP  Transient_Local_GETX [372830 372866 372426 372762 372623 372681 372738 372818 ] 2981744
+NP  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 NP  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-NP  Transient_Local_GETS [692740 692196 692800 692831 691905 692270 692717 692830 ] 5540289
+NP  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 NP  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
 NP  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 NP  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-NP  Own_Lock_or_Unlock [393214 393338 393622 393536 393429 393566 393547 393223 ] 3147475
+NP  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
 
-I  Load [0 0 0 0 0 0 0 0 ] 0
+I  Load [1 4 1 0 0 2 4 0 ] 12
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [0 0 0 1 0 0 0 1 ] 2
+I  Store [1 1 1 1 1 0 0 0 ] 5
 I  Atomic [0 0 0 0 0 0 0 0 ] 0
-I  L1_Replacement [468 465 467 419 489 454 467 504 ] 3733
+I  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 I  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 I  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 I  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 I  Ack [0 0 0 0 0 0 0 0 ] 0
 I  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-I  Transient_Local_GETX [2 0 3 3 0 1 1 2 ] 12
+I  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 I  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-I  Transient_Local_GETS [2 1 6 2 0 1 2 3 ] 17
+I  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I  Persistent_GETX [1 0 0 0 1 0 0 1 ] 3
-I  Persistent_GETS [1 0 3 2 0 1 0 1 ] 8
+I  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+I  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+I  Own_Lock_or_Unlock [0 1 0 0 0 1 0 0 ] 2
 
-S  Load [0 0 0 0 0 0 0 0 ] 0
+S  Load [0 0 4 0 0 2 0 2 ] 8
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
-S  Store [0 0 0 0 0 0 0 0 ] 0
+S  Store [0 0 0 0 1 2 0 1 ] 4
 S  Atomic [0 0 0 0 0 0 0 0 ] 0
-S  L1_Replacement [440 427 388 415 425 398 404 415 ] 3312
-S  Data_Shared [0 0 0 0 1 0 0 0 ] 1
-S  Data_Owner [0 0 0 1 0 0 0 0 ] 1
+S  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+S  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+S  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 S  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 S  Ack [0 0 0 0 0 0 0 0 ] 0
 S  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETX [0 0 1 0 0 1 1 0 ] 3
+S  Transient_Local_GETX [0 0 1 0 0 0 0 0 ] 1
 S  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETS [1 1 0 0 1 0 0 0 ] 3
+S  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-S  Transient_Local_GETS_Last_Token [0 1 1 1 1 0 3 0 ] 7
-S  Persistent_GETX [0 1 1 0 1 1 0 0 ] 4
-S  Persistent_GETS [0 0 0 0 0 0 1 0 ] 1
-S  Persistent_GETS_Last_Token [1 0 0 0 0 0 1 2 ] 4
+S  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+S  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+S  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+S  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 S  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
 
-O  Load [0 0 0 0 0 0 1 0 ] 1
+O  Load [7 3 2 5 1 0 9 0 ] 27
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
-O  Store [0 0 0 0 0 1 0 0 ] 1
+O  Store [3 1 1 1 0 0 1 4 ] 11
 O  Atomic [0 0 0 0 0 0 0 0 ] 0
-O  L1_Replacement [326 317 337 361 348 321 336 353 ] 2699
+O  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 O  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 O  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
-O  Ack [0 0 1 0 0 0 0 1 ] 2
-O  Ack_All_Tokens [0 0 0 0 1 0 0 0 ] 1
+O  Ack [0 0 0 0 0 0 1 1 ] 2
+O  Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 O  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-O  Transient_Local_GETX [0 1 1 1 0 0 0 2 ] 5
+O  Transient_Local_GETX [2 5 1 1 1 2 4 0 ] 16
 O  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-O  Transient_Local_GETS [0 2 0 0 1 2 1 2 ] 8
+O  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 O  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-O  Persistent_GETX [0 0 0 0 1 0 0 0 ] 1
-O  Persistent_GETS [1 0 2 1 1 0 1 0 ] 6
+O  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+O  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-O  Own_Lock_or_Unlock [26 20 23 35 37 26 26 43 ] 236
+O  Own_Lock_or_Unlock [4 4 1 2 1 1 4 1 ] 18
 
-M  Load [11 7 9 11 8 11 11 13 ] 81
+M  Load [28 73 44 39 51 47 48 45 ] 375
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [2 5 5 6 6 4 3 3 ] 34
+M  Store [22 27 20 30 34 31 25 34 ] 223
 M  Atomic [0 0 0 0 0 0 0 0 ] 0
-M  L1_Replacement [98109 98682 98114 98075 99009 98717 98125 98021 ] 786852
+M  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 M  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-M  Transient_Local_GETX [130 131 140 116 140 108 116 130 ] 1011
+M  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 M  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-M  Transient_Local_GETS [231 230 236 248 250 231 241 235 ] 1902
-M  Persistent_GETX [45 48 51 39 56 63 50 53 ] 405
-M  Persistent_GETS [92 89 69 81 99 97 85 88 ] 700
-M  Own_Lock_or_Unlock [5953 5846 5581 5706 5728 5637 5674 5916 ] 46041
+M  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+M  Persistent_GETX [2 2 4 1 2 1 3 3 ] 18
+M  Persistent_GETS [4 4 3 1 3 5 2 3 ] 25
+M  Own_Lock_or_Unlock [19 24 20 17 24 22 19 23 ] 168
 
-MM  Load [5 3 4 3 3 5 8 5 ] 36
+MM  Load [37560 37440 37171 37275 39797 38949 36895 37075 ] 302162
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM  Store [8 1 4 3 3 2 1 5 ] 27
+MM  Store [20087 19886 19931 20132 21523 20999 19589 20207 ] 162354
 MM  Atomic [0 0 0 0 0 0 0 0 ] 0
-MM  L1_Replacement [53054 53040 53463 53115 53280 53218 53159 53048 ] 425377
+MM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 MM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-MM  Transient_Local_GETX [86 67 59 74 74 77 70 74 ] 581
+MM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 MM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-MM  Transient_Local_GETS [113 128 134 112 117 117 134 148 ] 1003
-MM  Persistent_GETX [17 26 26 24 34 28 32 35 ] 222
-MM  Persistent_GETS [57 37 37 32 62 53 44 50 ] 372
-MM  Own_Lock_or_Unlock [3131 3110 3076 3014 3065 3089 3077 3111 ] 24673
+MM  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+MM  Persistent_GETX [2470 2470 2418 2451 2479 2469 2466 2510 ] 19733
+MM  Persistent_GETS [4629 4597 4673 4592 4638 4634 4526 4607 ] 36896
+MM  Own_Lock_or_Unlock [6898 6682 6801 6585 7078 6942 6691 7047 ] 54724
 
-M_W  Load [0 0 1 0 0 0 1 0 ] 2
+M_W  Load [8494 8681 8359 8508 8736 8655 8348 8688 ] 68469
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M_W  Store [0 0 0 0 0 0 0 0 ] 0
+M_W  Store [4571 4617 4577 4617 4591 4614 4605 4617 ] 36809
 M_W  Atomic [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_Replacement [438628 439522 436751 434652 442927 440817 438811 440017 ] 3512125
+M_W  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 M_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-M_W  Transient_Local_GETX [21 25 21 19 20 20 17 27 ] 170
+M_W  Transient_Local_GETX [1166 1154 1141 1143 1201 1194 1152 1185 ] 9336
 M_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-M_W  Transient_Local_GETS [39 41 30 39 29 50 32 30 ] 290
-M_W  Persistent_GETX [5 7 7 5 1 0 4 2 ] 31
-M_W  Persistent_GETS [18 17 11 13 3 3 9 8 ] 82
-M_W  Own_Lock_or_Unlock [208 253 255 216 229 259 227 245 ] 1892
-M_W  Use_TimeoutStarverX [8 9 7 6 1 0 5 3 ] 39
-M_W  Use_TimeoutStarverS [22 18 13 13 4 4 10 10 ] 94
-M_W  Use_TimeoutNoStarvers [98609 99185 98616 98565 99559 99221 98620 98530 ] 790905
+M_W  Transient_Local_GETS [2166 2212 2154 2181 2163 2167 2179 2189 ] 17411
+M_W  Persistent_GETX [0 1 0 1 0 0 4 0 ] 6
+M_W  Persistent_GETS [0 1 0 0 0 0 2 0 ] 3
+M_W  Own_Lock_or_Unlock [1 0 0 0 2 3 0 1 ] 7
+M_W  Use_TimeoutStarverX [0 0 0 0 0 0 0 0 ] 0
+M_W  Use_TimeoutStarverS [0 0 0 0 0 0 0 0 ] 0
+M_W  Use_TimeoutNoStarvers [28 33 27 32 39 37 30 40 ] 266
 M_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
-MM_W  Load [0 0 0 0 0 0 0 0 ] 0
+MM_W  Load [46901 46467 46766 47022 46777 46509 46835 46760 ] 374037
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM_W  Store [0 0 0 0 1 0 0 0 ] 1
+MM_W  Store [25226 25106 25236 24857 25022 25371 25142 24970 ] 200930
 MM_W  Atomic [0 0 0 0 0 0 0 0 ] 0
-MM_W  L1_Replacement [238286 236813 235991 235628 235275 235170 238358 238844 ] 1894365
+MM_W  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 MM_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-MM_W  Transient_Local_GETX [12 5 12 9 11 14 10 15 ] 88
+MM_W  Transient_Local_GETX [726 705 680 664 692 661 707 713 ] 5548
 MM_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-MM_W  Transient_Local_GETS [18 20 19 24 8 14 28 19 ] 150
-MM_W  Persistent_GETX [5 5 3 3 2 1 5 3 ] 27
-MM_W  Persistent_GETS [6 10 7 10 1 5 10 6 ] 55
-MM_W  Own_Lock_or_Unlock [124 123 114 122 121 124 142 111 ] 981
-MM_W  Use_TimeoutStarverX [5 5 3 4 2 1 5 3 ] 28
-MM_W  Use_TimeoutStarverS [7 12 7 12 1 5 10 7 ] 61
-MM_W  Use_TimeoutNoStarvers [53325 53293 53714 53351 53561 53490 53436 53352 ] 427522
+MM_W  Transient_Local_GETS [1308 1301 1347 1301 1330 1295 1309 1253 ] 10444
+MM_W  Persistent_GETX [6 17 10 26 0 6 48 0 ] 113
+MM_W  Persistent_GETS [11 26 13 47 0 8 62 1 ] 168
+MM_W  Own_Lock_or_Unlock [56 8 48 0 16 91 27 45 ] 291
+MM_W  Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123
+MM_W  Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177
+MM_W  Use_TimeoutNoStarvers [7077 7040 7071 7014 7084 7072 6967 7083 ] 56408
 MM_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
 IM  Atomic [0 0 0 0 0 0 0 0 ] 0
-IM  L1_Replacement [597681 600323 603709 602923 602449 597924 604184 599055 ] 4808248
+IM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 IM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
-IM  Data_Owner [1 1 0 0 0 1 1 0 ] 4
-IM  Data_All_Tokens [53335 53307 53724 53364 53564 53494 53450 53361 ] 427599
-IM  Ack [1 0 0 1 2 1 2 0 ] 7
+IM  Data_Owner [1 0 1 0 0 1 0 0 ] 3
+IM  Data_All_Tokens [2518 2465 2516 2471 2492 2469 2479 2461 ] 19871
+IM  Ack [0 1 1 1 0 0 0 1 ] 4
 IM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IM  Transient_Local_GETX [169 190 183 191 148 179 202 176 ] 1438
+IM  Transient_Local_GETX [222 216 237 258 221 212 225 232 ] 1823
 IM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IM  Transient_Local_GETS [354 326 324 298 288 304 326 315 ] 2535
+IM  Transient_Local_GETS [400 402 434 422 408 454 399 431 ] 3350
 IM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM  Persistent_GETX [79 76 100 115 61 76 80 82 ] 669
-IM  Persistent_GETS [156 163 192 187 120 109 131 129 ] 1187
+IM  Persistent_GETX [4521 4513 4646 4487 4479 4548 4472 4529 ] 36195
+IM  Persistent_GETS [8641 8405 8595 8462 8549 8387 8536 8357 ] 67932
 IM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM  Own_Lock_or_Unlock [17531 17525 17519 17502 17492 17556 17639 17671 ] 140435
-IM  Request_Timeout [343584 348506 347037 343579 342498 342141 341175 341787 ] 2750307
+IM  Own_Lock_or_Unlock [2182 1996 2007 1984 2492 2470 2235 2406 ] 17772
+IM  Request_Timeout [1799 1793 1784 1765 1766 1755 1871 1763 ] 14296
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -656,12 +574,12 @@ SM  Atomic [0 0 0 0 0 0 0 0 ] 0
 SM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 SM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 SM  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-SM  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+SM  Data_All_Tokens [2 2 0 1 1 3 2 2 ] 13
 SM  Ack [0 0 0 0 0 0 0 0 ] 0
 SM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-SM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_Local_GETX [3 2 3 0 2 2 0 1 ] 13
 SM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-SM  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_Local_GETS [0 0 0 0 0 2 0 0 ] 2
 SM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 SM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 SM  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
@@ -678,65 +596,65 @@ OM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 OM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 OM  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 OM  Ack [0 0 0 0 0 0 0 0 ] 0
-OM  Ack_All_Tokens [1 1 0 0 0 2 1 0 ] 5
+OM  Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11
 OM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-OM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_Local_GETX [3 1 1 0 0 0 0 3 ] 8
 OM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-OM  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_Local_GETS [0 0 0 1 0 0 0 0 ] 1
 OM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 OM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-OM  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-OM  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Persistent_GETX [0 0 0 0 0 1 0 0 ] 1
+OM  Persistent_GETS [1 0 1 0 0 0 0 0 ] 2
 OM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-OM  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+OM  Own_Lock_or_Unlock [0 1 0 0 0 0 0 3 ] 4
 OM  Request_Timeout [0 0 0 0 0 0 0 0 ] 0
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
 IS  Atomic [0 0 0 0 0 0 0 0 ] 0
-IS  L1_Replacement [1116012 1121454 1116280 1115024 1127150 1126599 1111548 1112279 ] 8946346
-IS  Data_Shared [325 321 306 321 322 299 309 317 ] 2520
-IS  Data_Owner [96 88 104 114 101 91 96 120 ] 810
-IS  Data_All_Tokens [98632 99209 98634 98583 99565 99224 98633 98541 ] 791021
+IS  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+IS  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+IS  Data_Owner [5 6 2 2 1 2 5 4 ] 27
+IS  Data_All_Tokens [4599 4650 4604 4647 4630 4651 4631 4657 ] 37069
 IS  Ack [0 0 0 0 0 0 0 0 ] 0
 IS  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IS  Transient_Local_GETX [289 321 356 346 311 328 306 315 ] 2572
+IS  Transient_Local_GETX [400 408 389 443 408 431 429 415 ] 3323
 IS  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IS  Transient_Local_GETS [600 617 562 557 566 572 629 590 ] 4693
+IS  Transient_Local_GETS [769 757 780 755 748 754 760 742 ] 6065
 IS  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IS  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS  Persistent_GETX [144 154 162 195 131 126 125 128 ] 1165
-IS  Persistent_GETS [267 274 314 319 246 229 247 263 ] 2159
+IS  Persistent_GETX [8371 8439 8397 8510 8389 8397 8431 8464 ] 67398
+IS  Persistent_GETS [15722 16004 15772 15880 15673 15863 15872 16008 ] 126794
 IS  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS  Own_Lock_or_Unlock [32690 32804 32386 32521 32797 32862 32379 32627 ] 261066
-IS  Request_Timeout [638170 648266 640666 644805 646272 643689 640188 643189 ] 5145245
+IS  Own_Lock_or_Unlock [3999 3732 3684 3780 4636 4659 4178 4566 ] 33234
+IS  Request_Timeout [3330 3318 3254 3362 3293 3408 3544 3379 ] 26888
 
-I_L  Load [217 206 207 209 206 201 188 205 ] 1639
+I_L  Load [4602 4651 4606 4649 4629 4651 4636 4662 ] 37086
 I_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I_L  Store [94 129 146 110 128 104 134 116 ] 961
+I_L  Store [2516 2464 2512 2471 2490 2467 2482 2459 ] 19861
 I_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-I_L  L1_Replacement [197 153 81 114 157 189 117 56 ] 1064
+I_L  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 I_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 I_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 I_L  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
 I_L  Ack [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-I_L  Transient_Local_GETX [738 698 688 726 723 711 702 691 ] 5677
+I_L  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-I_L  Transient_Local_GETS [1228 1204 1229 1255 1231 1211 1231 1233 ] 9822
+I_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 I_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I_L  Persistent_GETX [124437 124391 124284 124271 124578 124495 124364 124342 ] 995162
-I_L  Persistent_GETS [231075 230903 231210 231076 231220 231143 231542 231236 ] 1849405
+I_L  Persistent_GETX [29 83 67 101 1 11 63 0 ] 355
+I_L  Persistent_GETS [52 140 100 186 1 27 119 0 ] 625
 I_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-I_L  Own_Lock_or_Unlock [141 138 135 119 159 152 146 153 ] 1143
+I_L  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
 
-S_L  Load [0 0 0 0 0 0 0 0 ] 0
+S_L  Load [3 9 6 0 7 12 0 4 ] 41
 S_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
-S_L  Store [0 0 0 0 0 0 0 0 ] 0
+S_L  Store [4 4 2 1 2 3 2 2 ] 20
 S_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-S_L  L1_Replacement [50 48 15 7 15 17 32 21 ] 205
+S_L  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 S_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 S_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
 S_L  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
@@ -748,29 +666,29 @@ S_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 S_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 S_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 S_L  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-S_L  Persistent_GETS [16 14 5 13 0 0 7 6 ] 61
+S_L  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
 S_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-S_L  Own_Lock_or_Unlock [116 107 84 95 104 101 98 100 ] 805
+S_L  Own_Lock_or_Unlock [0 0 1 0 1 2 0 1 ] 5
 
 IM_L  Load [0 0 0 0 0 0 0 0 ] 0
 IM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM_L  Store [0 0 0 0 0 0 0 0 ] 0
 IM_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-IM_L  L1_Replacement [2155 2601 3319 2489 1925 2105 2183 2242 ] 19019
+IM_L  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 IM_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 IM_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-IM_L  Data_All_Tokens [1 2 0 3 0 0 0 1 ] 7
+IM_L  Data_All_Tokens [0 1 0 0 0 0 3 0 ] 4
 IM_L  Ack [0 0 0 0 0 0 0 0 ] 0
 IM_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IM_L  Transient_Local_GETX [1 0 0 0 2 0 1 0 ] 4
+IM_L  Transient_Local_GETX [5265 5143 5258 5229 5111 5141 5302 5088 ] 41537
 IM_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IM_L  Transient_Local_GETS [1 0 1 1 0 2 2 2 ] 9
+IM_L  Transient_Local_GETS [9843 9650 9830 9596 9842 9666 9585 9672 ] 77684
 IM_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IM_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IM_L  Persistent_GETX [21 18 35 42 1 3 15 11 ] 146
-IM_L  Persistent_GETS [33 57 68 63 0 6 22 29 ] 278
-IM_L  Own_Lock_or_Unlock [328 366 438 409 309 289 345 326 ] 2810
-IM_L  Request_Timeout [2931 3158 2730 1836 2012 1948 2127 2455 ] 19197
+IM_L  Persistent_GETX [1517 1566 1504 1478 1373 1311 1418 1290 ] 11457
+IM_L  Persistent_GETS [2742 2736 2735 2863 2483 2456 2680 2521 ] 21216
+IM_L  Own_Lock_or_Unlock [15678 15381 15753 15420 15518 15403 15487 15345 ] 123985
+IM_L  Request_Timeout [719 701 732 708 726 823 763 775 ] 5947
 
 SM_L  Load [0 0 0 0 0 0 0 0 ] 0
 SM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -788,30 +706,30 @@ SM_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
 SM_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 SM_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 SM_L  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
-SM_L  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_L  Persistent_GETS [0 0 0 0 0 0 1 0 ] 1
 SM_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-SM_L  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+SM_L  Own_Lock_or_Unlock [5 4 3 1 2 3 2 2 ] 22
 SM_L  Request_Timeout [0 0 0 0 0 0 0 0 ] 0
 
 IS_L  Load [0 0 0 0 0 0 0 0 ] 0
 IS_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS_L  Store [0 0 0 0 0 0 0 0 ] 0
 IS_L  Atomic [0 0 0 0 0 0 0 0 ] 0
-IS_L  L1_Replacement [4382 4588 4925 4941 3477 3609 3569 3621 ] 33112
+IS_L  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
 IS_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
 IS_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
-IS_L  Data_All_Tokens [7 3 2 1 1 1 2 3 ] 20
+IS_L  Data_All_Tokens [0 0 0 2 0 0 4 0 ] 6
 IS_L  Ack [0 0 0 0 0 0 0 0 ] 0
 IS_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
-IS_L  Transient_Local_GETX [0 1 1 2 0 0 1 2 ] 7
+IS_L  Transient_Local_GETX [9592 9799 9675 9691 9773 9788 9599 9799 ] 77716
 IS_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
-IS_L  Transient_Local_GETS [1 0 1 0 4 0 1 2 ] 9
+IS_L  Transient_Local_GETS [18021 18133 17959 18205 17990 18119 18238 18162 ] 144827
 IS_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
 IS_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
-IS_L  Persistent_GETX [36 45 70 66 1 7 11 22 ] 258
-IS_L  Persistent_GETS [76 76 101 118 0 10 28 56 ] 465
-IS_L  Own_Lock_or_Unlock [621 631 681 722 582 555 558 593 ] 4943
-IS_L  Request_Timeout [3263 3639 4943 4866 4879 4058 3993 2973 ] 32614
+IS_L  Persistent_GETX [2765 2876 2805 2917 2676 2649 2829 2564 ] 22081
+IS_L  Persistent_GETS [4930 5143 5114 5121 4743 4669 4838 4519 ] 39077
+IS_L  Own_Lock_or_Unlock [28695 29094 28775 29037 28691 28911 28935 29134 ] 231272
+IS_L  Request_Timeout [1299 1414 1377 1305 1337 1482 1361 1416 ] 10991
 
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
   system.l1_cntrl1.L1IcacheMemory_total_misses: 0
@@ -822,16 +740,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 153113
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 153113
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 7127
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 7127
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.0611%
-  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.9389%
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.315%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.685%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode:   153113    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode:   7127    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -842,16 +760,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 152495
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 152495
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 7127
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 7127
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.949%
-  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.051%
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   65.1326%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   34.8674%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode:   152495    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode:   7127    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -862,16 +780,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 152346
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 152346
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 7130
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 7130
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.9718%
-  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.0282%
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   65.3997%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   34.6003%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode:   152346    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode:   7130    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -882,16 +800,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 152401
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 152401
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 7129
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 7129
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.0015%
-  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.9985%
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.5953%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.4047%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode:   152401    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode:   7129    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -902,16 +820,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 152935
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 152935
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 7127
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 7127
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.1414%
-  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.8586%
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.3431%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.6569%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode:   152935    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode:   7127    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -922,16 +840,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 152773
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 152773
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 7125
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 7125
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.8334%
-  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.1666%
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.6737%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.3263%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode:   152773    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode:   7125    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -942,63 +860,63 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 152390
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 152390
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 7125
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 7125
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.98%
-  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.02%
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   65.2772%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   34.7228%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode:   152390    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode:   7125    100%
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 1221063
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1221063
+  system.l2_cntrl0.L2cacheMemory_total_misses: 57015
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 57015
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   65.0075%
-  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   34.9925%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   65.0916%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   34.9084%
 
-  system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   1221063    100%
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   57015    100%
 
  --- L2Cache ---
  - Event Counts -
-L1_GETS [794391 ] 794391
+L1_GETS [37112 ] 37112
 L1_GETS_Last_Token [0 ] 0
-L1_GETX [427616 ] 427616
-L1_INV [3735 ] 3735
+L1_GETX [19903 ] 19903
+L1_INV [56964 ] 56964
 Transient_GETX [0 ] 0
 Transient_GETS [0 ] 0
 Transient_GETS_Last_Token [0 ] 0
-L2_Replacement [1216001 ] 1216001
+L2_Replacement [0 ] 0
 Writeback_Tokens [0 ] 0
-Writeback_Shared_Data [3090 ] 3090
-Writeback_All_Tokens [1212600 ] 1212600
-Writeback_Owned [2549 ] 2549
+Writeback_Shared_Data [0 ] 0
+Writeback_All_Tokens [0 ] 0
+Writeback_Owned [0 ] 0
 Data_Shared [0 ] 0
 Data_Owner [0 ] 0
 Data_All_Tokens [0 ] 0
 Ack [0 ] 0
 Ack_All_Tokens [0 ] 0
-Persistent_GETX [142586 ] 142586
-Persistent_GETS [264969 ] 264969
-Persistent_GETS_Last_Token [1 ] 1
-Own_Lock_or_Unlock [403116 ] 403116
+Persistent_GETX [22460 ] 22460
+Persistent_GETS [41771 ] 41771
+Persistent_GETS_Last_Token [0 ] 0
+Own_Lock_or_Unlock [49719 ] 49719
 
  - Transitions -
-NP  L1_GETS [792143 ] 792143
-NP  L1_GETX [426330 ] 426330
-NP  L1_INV [2602 ] 2602
+NP  L1_GETS [26 ] 26
+NP  L1_GETX [27 ] 27
+NP  L1_INV [17 ] 17
 NP  Transient_GETX [0 ] 0
 NP  Transient_GETS [0 ] 0
 NP  Writeback_Tokens [0 ] 0
-NP  Writeback_Shared_Data [3088 ] 3088
-NP  Writeback_All_Tokens [1210366 ] 1210366
-NP  Writeback_Owned [2549 ] 2549
+NP  Writeback_Shared_Data [0 ] 0
+NP  Writeback_All_Tokens [0 ] 0
+NP  Writeback_Owned [0 ] 0
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
 NP  Data_All_Tokens [0 ] 0
@@ -1006,19 +924,19 @@ NP  Ack [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [403006 ] 403006
+NP  Own_Lock_or_Unlock [49719 ] 49719
 
 I  L1_GETS [0 ] 0
 I  L1_GETS_Last_Token [0 ] 0
 I  L1_GETX [0 ] 0
-I  L1_INV [1 ] 1
+I  L1_INV [0 ] 0
 I  Transient_GETX [0 ] 0
 I  Transient_GETS [0 ] 0
 I  Transient_GETS_Last_Token [0 ] 0
-I  L2_Replacement [394 ] 394
+I  L2_Replacement [0 ] 0
 I  Writeback_Tokens [0 ] 0
 I  Writeback_Shared_Data [0 ] 0
-I  Writeback_All_Tokens [54 ] 54
+I  Writeback_All_Tokens [0 ] 0
 I  Writeback_Owned [0 ] 0
 I  Data_Shared [0 ] 0
 I  Data_Owner [0 ] 0
@@ -1031,15 +949,15 @@ I  Own_Lock_or_Unlock [0 ] 0
 
 S  L1_GETS [0 ] 0
 S  L1_GETS_Last_Token [0 ] 0
-S  L1_GETX [2 ] 2
+S  L1_GETX [0 ] 0
 S  L1_INV [0 ] 0
 S  Transient_GETX [0 ] 0
 S  Transient_GETS [0 ] 0
 S  Transient_GETS_Last_Token [0 ] 0
-S  L2_Replacement [2935 ] 2935
+S  L2_Replacement [0 ] 0
 S  Writeback_Tokens [0 ] 0
-S  Writeback_Shared_Data [1 ] 1
-S  Writeback_All_Tokens [150 ] 150
+S  Writeback_Shared_Data [0 ] 0
+S  Writeback_All_Tokens [0 ] 0
 S  Writeback_Owned [0 ] 0
 S  Data_Shared [0 ] 0
 S  Data_Owner [0 ] 0
@@ -1047,20 +965,20 @@ S  Data_All_Tokens [0 ] 0
 S  Ack [0 ] 0
 S  Persistent_GETX [0 ] 0
 S  Persistent_GETS [0 ] 0
-S  Persistent_GETS_Last_Token [1 ] 1
+S  Persistent_GETS_Last_Token [0 ] 0
 S  Own_Lock_or_Unlock [0 ] 0
 
-O  L1_GETS [1 ] 1
+O  L1_GETS [0 ] 0
 O  L1_GETS_Last_Token [0 ] 0
 O  L1_GETX [0 ] 0
 O  L1_INV [0 ] 0
 O  Transient_GETX [0 ] 0
 O  Transient_GETS [0 ] 0
 O  Transient_GETS_Last_Token [0 ] 0
-O  L2_Replacement [2934 ] 2934
+O  L2_Replacement [0 ] 0
 O  Writeback_Tokens [0 ] 0
-O  Writeback_Shared_Data [1 ] 1
-O  Writeback_All_Tokens [222 ] 222
+O  Writeback_Shared_Data [0 ] 0
+O  Writeback_All_Tokens [0 ] 0
 O  Data_Shared [0 ] 0
 O  Data_All_Tokens [0 ] 0
 O  Ack [0 ] 0
@@ -1070,34 +988,34 @@ O  Persistent_GETS [0 ] 0
 O  Persistent_GETS_Last_Token [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 
-M  L1_GETS [607 ] 607
-M  L1_GETX [336 ] 336
+M  L1_GETS [0 ] 0
+M  L1_GETX [0 ] 0
 M  L1_INV [0 ] 0
 M  Transient_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
-M  L2_Replacement [1209281 ] 1209281
-M  Persistent_GETX [208 ] 208
-M  Persistent_GETS [358 ] 358
+M  L2_Replacement [0 ] 0
+M  Persistent_GETX [0 ] 0
+M  Persistent_GETS [0 ] 0
 M  Own_Lock_or_Unlock [0 ] 0
 
-I_L  L1_GETS [1640 ] 1640
-I_L  L1_GETX [948 ] 948
-I_L  L1_INV [1132 ] 1132
+I_L  L1_GETS [37086 ] 37086
+I_L  L1_GETX [19876 ] 19876
+I_L  L1_INV [56947 ] 56947
 I_L  Transient_GETX [0 ] 0
 I_L  Transient_GETS [0 ] 0
 I_L  Transient_GETS_Last_Token [0 ] 0
-I_L  L2_Replacement [456 ] 456
+I_L  L2_Replacement [0 ] 0
 I_L  Writeback_Tokens [0 ] 0
 I_L  Writeback_Shared_Data [0 ] 0
-I_L  Writeback_All_Tokens [1808 ] 1808
+I_L  Writeback_All_Tokens [0 ] 0
 I_L  Writeback_Owned [0 ] 0
 I_L  Data_Shared [0 ] 0
 I_L  Data_Owner [0 ] 0
 I_L  Data_All_Tokens [0 ] 0
 I_L  Ack [0 ] 0
-I_L  Persistent_GETX [142378 ] 142378
-I_L  Persistent_GETS [264611 ] 264611
-I_L  Own_Lock_or_Unlock [110 ] 110
+I_L  Persistent_GETX [22460 ] 22460
+I_L  Persistent_GETS [41771 ] 41771
+I_L  Own_Lock_or_Unlock [0 ] 0
 
 S_L  L1_GETS [0 ] 0
 S_L  L1_GETS_Last_Token [0 ] 0
@@ -1106,7 +1024,7 @@ S_L  L1_INV [0 ] 0
 S_L  Transient_GETX [0 ] 0
 S_L  Transient_GETS [0 ] 0
 S_L  Transient_GETS_Last_Token [0 ] 0
-S_L  L2_Replacement [1 ] 1
+S_L  L2_Replacement [0 ] 0
 S_L  Writeback_Tokens [0 ] 0
 S_L  Writeback_Shared_Data [0 ] 0
 S_L  Writeback_All_Tokens [0 ] 0
@@ -1121,93 +1039,93 @@ S_L  Persistent_GETS_Last_Token [0 ] 0
 S_L  Own_Lock_or_Unlock [0 ] 0
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1638489
-  memory_reads: 1212126
-  memory_writes: 426322
-  memory_refreshes: 81456
-  memory_total_request_delays: 99459030
-  memory_delays_per_request: 60.7017
-  memory_delays_in_input_queue: 1167381
-  memory_delays_behind_head_of_bank_queue: 40964968
-  memory_delays_stalled_at_head_of_bank_queue: 57326681
-  memory_stalls_for_bank_busy: 8863977
+  memory_total_requests: 2
+  memory_reads: 2
+  memory_writes: 0
+  memory_refreshes: 22
+  memory_total_request_delays: 31
+  memory_delays_per_request: 15.5
+  memory_delays_in_input_queue: 1
+  memory_delays_behind_head_of_bank_queue: 10
+  memory_delays_stalled_at_head_of_bank_queue: 20
+  memory_stalls_for_bank_busy: 20
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 13706459
-  memory_stalls_for_arbitration: 11848502
-  memory_stalls_for_bus: 16081023
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 0
+  memory_stalls_for_bus: 0
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 4050192
-  memory_stalls_for_read_read_turnaround: 2776528
-  accesses_per_bank: 51563  51247  51111  51262  51307  51641  51526  50922  51422  51315  51572  51160  51192  51249  51125  50854  51329  50999  51574  51128  51109  51142  51061  51073  51213  50871  50957  50802  51227  51032  51458  51046  
+  memory_stalls_for_read_write_turnaround: 0
+  memory_stalls_for_read_read_turnaround: 0
+  accesses_per_bank: 2  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  
 
  --- Directory ---
  - Event Counts -
-GETX [781168 ] 781168
-GETS [1437822 ] 1437822
-Lockdown [407556 ] 407556
-Unlockdown [403116 ] 403116
+GETX [19962 ] 19962
+GETS [37458 ] 37458
+Lockdown [64231 ] 64231
+Unlockdown [49719 ] 49719
 Own_Lock_or_Unlock [0 ] 0
 Own_Lock_or_Unlock_Tokens [0 ] 0
-Data_Owner [217 ] 217
-Data_All_Tokens [426161 ] 426161
-Ack_Owner [1520 ] 1520
-Ack_Owner_All_Tokens [784319 ] 784319
-Tokens [1303 ] 1303
-Ack_All_Tokens [15697 ] 15697
+Data_Owner [0 ] 0
+Data_All_Tokens [0 ] 0
+Ack_Owner [0 ] 0
+Ack_Owner_All_Tokens [0 ] 0
+Tokens [0 ] 0
+Ack_All_Tokens [0 ] 0
 Request_Timeout [0 ] 0
-Memory_Data [1212121 ] 1212121
-Memory_Ack [426322 ] 426322
+Memory_Data [2 ] 2
+Memory_Ack [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
 DMA_WRITE_All_Tokens [0 ] 0
 
  - Transitions -
-O  GETX [420963 ] 420963
-O  GETS [782334 ] 782334
-O  Lockdown [5301 ] 5301
+O  GETX [0 ] 0
+O  GETS [2 ] 2
+O  Lockdown [0 ] 0
 O  Unlockdown [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 O  Own_Lock_or_Unlock_Tokens [0 ] 0
 O  Data_Owner [0 ] 0
 O  Data_All_Tokens [0 ] 0
-O  Tokens [5 ] 5
-O  Ack_All_Tokens [1720 ] 1720
+O  Tokens [0 ] 0
+O  Ack_All_Tokens [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  DMA_WRITE_All_Tokens [0 ] 0
 
-NO  GETX [3484 ] 3484
-NO  GETS [6315 ] 6315
-NO  Lockdown [13581 ] 13581
+NO  GETX [42 ] 42
+NO  GETS [24 ] 24
+NO  Lockdown [49719 ] 49719
 NO  Unlockdown [0 ] 0
 NO  Own_Lock_or_Unlock [0 ] 0
 NO  Own_Lock_or_Unlock_Tokens [0 ] 0
-NO  Data_Owner [217 ] 217
-NO  Data_All_Tokens [426126 ] 426126
-NO  Ack_Owner [1518 ] 1518
-NO  Ack_Owner_All_Tokens [784251 ] 784251
-NO  Tokens [1211 ] 1211
+NO  Data_Owner [0 ] 0
+NO  Data_All_Tokens [0 ] 0
+NO  Ack_Owner [0 ] 0
+NO  Ack_Owner_All_Tokens [0 ] 0
+NO  Tokens [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
 
-L  GETX [2833 ] 2833
-L  GETS [5134 ] 5134
-L  Lockdown [2527 ] 2527
-L  Unlockdown [403116 ] 403116
+L  GETX [19861 ] 19861
+L  GETS [37086 ] 37086
+L  Lockdown [14512 ] 14512
+L  Unlockdown [49719 ] 49719
 L  Own_Lock_or_Unlock [0 ] 0
 L  Own_Lock_or_Unlock_Tokens [0 ] 0
 L  Data_Owner [0 ] 0
-L  Data_All_Tokens [35 ] 35
-L  Ack_Owner [2 ] 2
-L  Ack_Owner_All_Tokens [68 ] 68
-L  Tokens [6 ] 6
+L  Data_All_Tokens [0 ] 0
+L  Ack_Owner [0 ] 0
+L  Ack_Owner_All_Tokens [0 ] 0
+L  Tokens [0 ] 0
 L  DMA_READ [0 ] 0
 L  DMA_WRITE [0 ] 0
 L  DMA_WRITE_All_Tokens [0 ] 0
 
-O_W  GETX [88763 ] 88763
-O_W  GETS [164639 ] 164639
-O_W  Lockdown [3548 ] 3548
+O_W  GETX [0 ] 0
+O_W  GETS [0 ] 0
+O_W  Lockdown [0 ] 0
 O_W  Unlockdown [0 ] 0
 O_W  Own_Lock_or_Unlock [0 ] 0
 O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1215,16 +1133,16 @@ O_W  Data_Owner [0 ] 0
 O_W  Data_All_Tokens [0 ] 0
 O_W  Ack_Owner [0 ] 0
 O_W  Tokens [0 ] 0
-O_W  Ack_All_Tokens [13339 ] 13339
+O_W  Ack_All_Tokens [0 ] 0
 O_W  Memory_Data [0 ] 0
-O_W  Memory_Ack [422774 ] 422774
+O_W  Memory_Ack [0 ] 0
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  DMA_WRITE_All_Tokens [0 ] 0
 
-L_O_W  GETX [78820 ] 78820
-L_O_W  GETS [141705 ] 141705
-L_O_W  Lockdown [91 ] 91
+L_O_W  GETX [0 ] 0
+L_O_W  GETS [0 ] 0
+L_O_W  Lockdown [0 ] 0
 L_O_W  Unlockdown [0 ] 0
 L_O_W  Own_Lock_or_Unlock [0 ] 0
 L_O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1232,16 +1150,16 @@ L_O_W  Data_Owner [0 ] 0
 L_O_W  Data_All_Tokens [0 ] 0
 L_O_W  Ack_Owner [0 ] 0
 L_O_W  Tokens [0 ] 0
-L_O_W  Ack_All_Tokens [349 ] 349
-L_O_W  Memory_Data [8849 ] 8849
-L_O_W  Memory_Ack [3548 ] 3548
+L_O_W  Ack_All_Tokens [0 ] 0
+L_O_W  Memory_Data [0 ] 0
+L_O_W  Memory_Ack [0 ] 0
 L_O_W  DMA_READ [0 ] 0
 L_O_W  DMA_WRITE [0 ] 0
 L_O_W  DMA_WRITE_All_Tokens [0 ] 0
 
-L_NO_W  GETX [88353 ] 88353
-L_NO_W  GETS [158940 ] 158940
-L_NO_W  Lockdown [1816 ] 1816
+L_NO_W  GETX [0 ] 0
+L_NO_W  GETS [0 ] 0
+L_NO_W  Lockdown [0 ] 0
 L_NO_W  Unlockdown [0 ] 0
 L_NO_W  Own_Lock_or_Unlock [0 ] 0
 L_NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -1249,8 +1167,8 @@ L_NO_W  Data_Owner [0 ] 0
 L_NO_W  Data_All_Tokens [0 ] 0
 L_NO_W  Ack_Owner [0 ] 0
 L_NO_W  Tokens [0 ] 0
-L_NO_W  Ack_All_Tokens [54 ] 54
-L_NO_W  Memory_Data [380687 ] 380687
+L_NO_W  Ack_All_Tokens [0 ] 0
+L_NO_W  Memory_Data [0 ] 0
 L_NO_W  DMA_READ [0 ] 0
 L_NO_W  DMA_WRITE [0 ] 0
 L_NO_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -1289,18 +1207,18 @@ DW_L_W  DMA_READ [0 ] 0
 DW_L_W  DMA_WRITE [0 ] 0
 DW_L_W  DMA_WRITE_All_Tokens [0 ] 0
 
-NO_W  GETX [97952 ] 97952
-NO_W  GETS [178755 ] 178755
-NO_W  Lockdown [380692 ] 380692
+NO_W  GETX [59 ] 59
+NO_W  GETS [346 ] 346
+NO_W  Lockdown [0 ] 0
 NO_W  Unlockdown [0 ] 0
 NO_W  Own_Lock_or_Unlock [0 ] 0
 NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
 NO_W  Data_Owner [0 ] 0
 NO_W  Data_All_Tokens [0 ] 0
 NO_W  Ack_Owner [0 ] 0
-NO_W  Tokens [81 ] 81
-NO_W  Ack_All_Tokens [235 ] 235
-NO_W  Memory_Data [822585 ] 822585
+NO_W  Tokens [0 ] 0
+NO_W  Ack_All_Tokens [0 ] 0
+NO_W  Memory_Data [2 ] 2
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  DMA_WRITE_All_Tokens [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index f35d10727..36afc005b 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -1,74 +1,74 @@
-system.cpu5: completed 10000 read accesses @3921160
-system.cpu1: completed 10000 read accesses @3925580
-system.cpu0: completed 10000 read accesses @3934400
-system.cpu2: completed 10000 read accesses @3939680
-system.cpu3: completed 10000 read accesses @3944050
-system.cpu6: completed 10000 read accesses @3950830
-system.cpu7: completed 10000 read accesses @3958280
-system.cpu4: completed 10000 read accesses @3974010
-system.cpu0: completed 20000 read accesses @7820430
-system.cpu5: completed 20000 read accesses @7822630
-system.cpu1: completed 20000 read accesses @7842540
-system.cpu2: completed 20000 read accesses @7858630
-system.cpu3: completed 20000 read accesses @7865210
-system.cpu4: completed 20000 read accesses @7866290
-system.cpu6: completed 20000 read accesses @7899300
-system.cpu7: completed 20000 read accesses @7926330
-system.cpu0: completed 30000 read accesses @11730870
-system.cpu1: completed 30000 read accesses @11752380
-system.cpu5: completed 30000 read accesses @11754100
-system.cpu4: completed 30000 read accesses @11817260
-system.cpu3: completed 30000 read accesses @11833290
-system.cpu2: completed 30000 read accesses @11849820
-system.cpu6: completed 30000 read accesses @11858520
-system.cpu7: completed 30000 read accesses @11878780
-system.cpu1: completed 40000 read accesses @15666470
-system.cpu0: completed 40000 read accesses @15689570
-system.cpu5: completed 40000 read accesses @15693470
-system.cpu3: completed 40000 read accesses @15770740
-system.cpu2: completed 40000 read accesses @15801030
-system.cpu4: completed 40000 read accesses @15802680
-system.cpu6: completed 40000 read accesses @15812300
-system.cpu7: completed 40000 read accesses @15814020
-system.cpu0: completed 50000 read accesses @19587160
-system.cpu1: completed 50000 read accesses @19609890
-system.cpu5: completed 50000 read accesses @19679290
-system.cpu3: completed 50000 read accesses @19706240
-system.cpu6: completed 50000 read accesses @19738150
-system.cpu2: completed 50000 read accesses @19790350
-system.cpu4: completed 50000 read accesses @19793110
-system.cpu7: completed 50000 read accesses @19826670
-system.cpu0: completed 60000 read accesses @23442420
-system.cpu1: completed 60000 read accesses @23506570
-system.cpu5: completed 60000 read accesses @23555050
-system.cpu3: completed 60000 read accesses @23640540
-system.cpu6: completed 60000 read accesses @23651620
-system.cpu4: completed 60000 read accesses @23764590
-system.cpu2: completed 60000 read accesses @23767160
-system.cpu7: completed 60000 read accesses @23798150
-system.cpu0: completed 70000 read accesses @27346650
-system.cpu1: completed 70000 read accesses @27417040
-system.cpu5: completed 70000 read accesses @27459850
-system.cpu3: completed 70000 read accesses @27568910
-system.cpu7: completed 70000 read accesses @27679260
-system.cpu4: completed 70000 read accesses @27695210
-system.cpu2: completed 70000 read accesses @27695820
-system.cpu6: completed 70000 read accesses @27700350
-system.cpu0: completed 80000 read accesses @31228160
-system.cpu5: completed 80000 read accesses @31278826
-system.cpu1: completed 80000 read accesses @31322150
-system.cpu3: completed 80000 read accesses @31508190
-system.cpu2: completed 80000 read accesses @31596330
-system.cpu6: completed 80000 read accesses @31639000
-system.cpu4: completed 80000 read accesses @31655530
-system.cpu7: completed 80000 read accesses @31659000
-system.cpu0: completed 90000 read accesses @35134550
-system.cpu5: completed 90000 read accesses @35282690
-system.cpu1: completed 90000 read accesses @35298090
-system.cpu2: completed 90000 read accesses @35490890
-system.cpu3: completed 90000 read accesses @35500970
-system.cpu6: completed 90000 read accesses @35564170
-system.cpu7: completed 90000 read accesses @35589110
-system.cpu4: completed 90000 read accesses @35604290
-system.cpu0: completed 100000 read accesses @39098820
+system.cpu0: completed 10000 read accesses @257947
+system.cpu1: completed 10000 read accesses @260311
+system.cpu3: completed 10000 read accesses @264703
+system.cpu7: completed 10000 read accesses @266036
+system.cpu5: completed 10000 read accesses @266378
+system.cpu4: completed 10000 read accesses @267169
+system.cpu2: completed 10000 read accesses @267625
+system.cpu6: completed 10000 read accesses @271366
+system.cpu0: completed 20000 read accesses @515410
+system.cpu1: completed 20000 read accesses @519078
+system.cpu7: completed 20000 read accesses @528562
+system.cpu3: completed 20000 read accesses @529556
+system.cpu5: completed 20000 read accesses @531753
+system.cpu4: completed 20000 read accesses @536204
+system.cpu6: completed 20000 read accesses @537031
+system.cpu2: completed 20000 read accesses @537314
+system.cpu0: completed 30000 read accesses @772994
+system.cpu1: completed 30000 read accesses @780923
+system.cpu3: completed 30000 read accesses @794263
+system.cpu7: completed 30000 read accesses @796675
+system.cpu4: completed 30000 read accesses @797063
+system.cpu5: completed 30000 read accesses @800026
+system.cpu2: completed 30000 read accesses @802601
+system.cpu6: completed 30000 read accesses @805267
+system.cpu0: completed 40000 read accesses @1033304
+system.cpu1: completed 40000 read accesses @1040457
+system.cpu3: completed 40000 read accesses @1058903
+system.cpu7: completed 40000 read accesses @1062178
+system.cpu5: completed 40000 read accesses @1064117
+system.cpu4: completed 40000 read accesses @1065423
+system.cpu6: completed 40000 read accesses @1066744
+system.cpu2: completed 40000 read accesses @1068649
+system.cpu0: completed 50000 read accesses @1292512
+system.cpu1: completed 50000 read accesses @1299935
+system.cpu3: completed 50000 read accesses @1324981
+system.cpu5: completed 50000 read accesses @1327818
+system.cpu7: completed 50000 read accesses @1328780
+system.cpu4: completed 50000 read accesses @1329164
+system.cpu6: completed 50000 read accesses @1332786
+system.cpu2: completed 50000 read accesses @1334645
+system.cpu0: completed 60000 read accesses @1550153
+system.cpu1: completed 60000 read accesses @1559435
+system.cpu7: completed 60000 read accesses @1591474
+system.cpu3: completed 60000 read accesses @1593078
+system.cpu4: completed 60000 read accesses @1594642
+system.cpu5: completed 60000 read accesses @1595392
+system.cpu2: completed 60000 read accesses @1600002
+system.cpu6: completed 60000 read accesses @1600595
+system.cpu0: completed 70000 read accesses @1802423
+system.cpu1: completed 70000 read accesses @1829858
+system.cpu7: completed 70000 read accesses @1853648
+system.cpu5: completed 70000 read accesses @1854214
+system.cpu3: completed 70000 read accesses @1854818
+system.cpu4: completed 70000 read accesses @1855726
+system.cpu6: completed 70000 read accesses @1868528
+system.cpu2: completed 70000 read accesses @1875446
+system.cpu0: completed 80000 read accesses @2061056
+system.cpu1: completed 80000 read accesses @2090957
+system.cpu7: completed 80000 read accesses @2119055
+system.cpu4: completed 80000 read accesses @2119432
+system.cpu5: completed 80000 read accesses @2121677
+system.cpu3: completed 80000 read accesses @2123217
+system.cpu6: completed 80000 read accesses @2133942
+system.cpu2: completed 80000 read accesses @2139530
+system.cpu0: completed 90000 read accesses @2322313
+system.cpu1: completed 90000 read accesses @2351193
+system.cpu4: completed 90000 read accesses @2382901
+system.cpu7: completed 90000 read accesses @2384445
+system.cpu5: completed 90000 read accesses @2387842
+system.cpu3: completed 90000 read accesses @2390630
+system.cpu6: completed 90000 read accesses @2400244
+system.cpu2: completed 90000 read accesses @2403389
+system.cpu0: completed 100000 read accesses @2583072
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index f4b61465c..333832488 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:27:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:27:50
-M5 executing on SC2B0617
+M5 compiled Aug 20 2010 12:14:24
+M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
+M5 started Aug 20 2010 12:14:33
+M5 executing on SC2B0629
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 39098820 because maximum number of loads reached
+Exiting @ tick 2583072 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 68c71ee6c..a96eed002 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 346116                       # Number of bytes of host memory used
-host_seconds                                   308.61                       # Real time elapsed on the host
-host_tick_rate                                 126695                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 341980                       # Number of bytes of host memory used
+host_seconds                                    25.58                       # Real time elapsed on the host
+host_tick_rate                                 100993                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.039099                       # Number of seconds simulated
-sim_ticks                                    39098820                       # Number of ticks simulated
+sim_seconds                                  0.002583                       # Number of seconds simulated
+sim_ticks                                     2583072                       # Number of ticks simulated
 system.cpu0.num_copies                              0                       # number of copy accesses completed
 system.cpu0.num_reads                          100000                       # number of read accesses completed
-system.cpu0.num_writes                          53574                       # number of write accesses completed
+system.cpu0.num_writes                          53663                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99631                       # number of read accesses completed
-system.cpu1.num_writes                          53502                       # number of write accesses completed
+system.cpu1.num_reads                           98827                       # number of read accesses completed
+system.cpu1.num_writes                          53487                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99061                       # number of read accesses completed
-system.cpu2.num_writes                          53455                       # number of write accesses completed
+system.cpu2.num_reads                           96775                       # number of read accesses completed
+system.cpu2.num_writes                          51846                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           98999                       # number of read accesses completed
-system.cpu3.num_writes                          53370                       # number of write accesses completed
+system.cpu3.num_reads                           97235                       # number of read accesses completed
+system.cpu3.num_writes                          52295                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99076                       # number of read accesses completed
-system.cpu4.num_writes                          53347                       # number of write accesses completed
+system.cpu4.num_reads                           97597                       # number of read accesses completed
+system.cpu4.num_writes                          52429                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99631                       # number of read accesses completed
-system.cpu5.num_writes                          53316                       # number of write accesses completed
+system.cpu5.num_reads                           97329                       # number of read accesses completed
+system.cpu5.num_writes                          52105                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99060                       # number of read accesses completed
-system.cpu6.num_writes                          53733                       # number of write accesses completed
+system.cpu6.num_reads                           96958                       # number of read accesses completed
+system.cpu6.num_writes                          52281                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99033                       # number of read accesses completed
-system.cpu7.num_writes                          53376                       # number of write accesses completed
+system.cpu7.num_reads                           97500                       # number of read accesses completed
+system.cpu7.num_writes                          52109                       # number of write accesses completed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 94fb1ffbb..1464a2cc5 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -151,7 +142,6 @@ type=Directory_Controller
 children=directory memBuffer probeFilter
 buffer_size=0
 directory=system.dir_cntrl0.directory
-full_bit_dir_enabled=false
 memBuffer=system.dir_cntrl0.memBuffer
 memory_controller_latency=2
 number_of_TBEs=256
@@ -548,9 +538,10 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
+children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -562,7 +553,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
@@ -575,7 +565,6 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl1.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.L1IcacheMemory
@@ -588,7 +577,6 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl2.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.L1IcacheMemory
@@ -601,7 +589,6 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl3.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.L1IcacheMemory
@@ -614,7 +601,6 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl4.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.L1IcacheMemory
@@ -627,7 +613,6 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl5.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.L1IcacheMemory
@@ -640,7 +625,6 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl6.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.L1IcacheMemory
@@ -653,7 +637,6 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl7.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.L1IcacheMemory
@@ -664,6 +647,14 @@ version=7
 physMemPort=system.physmem.port[7]
 port=system.cpu7.test
 
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index 8e7fdfcfc..dfe8adee6 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:46:26
+Real time: Aug/20/2010 12:18:32
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 245
-Elapsed_time_in_minutes: 4.08333
-Elapsed_time_in_hours: 0.0680556
-Elapsed_time_in_days: 0.00283565
+Elapsed_time_in_seconds: 37
+Elapsed_time_in_minutes: 0.616667
+Elapsed_time_in_hours: 0.0102778
+Elapsed_time_in_days: 0.000428241
 
-Virtual_time_in_seconds: 245.19
-Virtual_time_in_minutes: 4.0865
-Virtual_time_in_hours:   0.0681083
-Virtual_time_in_days:    0.00283785
+Virtual_time_in_seconds: 37.71
+Virtual_time_in_minutes: 0.6285
+Virtual_time_in_hours:   0.010475
+Virtual_time_in_days:    0.000436458
 
-Ruby_current_time: 38059429
+Ruby_current_time: 3305503
 Ruby_start_time: 0
-Ruby_cycles: 38059429
+Ruby_cycles: 3305503
 
-mbytes_resident: 35.4062
-mbytes_total: 337.359
-resident_ratio: 0.104974
+mbytes_resident: 32.625
+mbytes_total: 333.629
+resident_ratio: 0.0978
 
-ruby_cycles_executed: [ 38059430 38059430 38059430 38059430 38059430 38059430 38059430 38059430 ]
+ruby_cycles_executed: [ 3305504 3305504 3305504 3305504 3305504 3305504 3305504 3305504 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -66,35 +66,31 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1223364 average: 15.9992 | standard deviation: 0.0900488 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1223244 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1224677 average: 1.93738 | standard deviation: 0.24228 | 0 76690 1147987 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 20160 count: 1223236 average: 3982.16 | standard deviation: 4665.63 | 3708 13781 25116 33223 31921 38797 43604 45421 39533 34780 37348 35273 29185 26408 23841 22826 19268 17942 17660 14791 14436 14028 13947 12589 11213 12158 12485 11406 11283 10763 11315 10826 10964 11697 10326 10963 11210 11863 11224 10479 11754 12169 11782 11935 11747 12526 12312 12508 13274 11956 12572 12763 13270 12822 11784 12738 12948 12280 11992 11264 11881 10994 10700 10686 9540 9613 9236 9204 8301 7394 7524 7032 6512 5971 5447 5391 4756 4563 4247 3623 3363 3219 3041 2542 2170 2242 2127 1734 1545 1433 1353 1137 1013 958 793 705 672 598 488 422 421 364 276 289 244 209 186 152 145 110 83 83 85 66 45 42 32 36 20 29 27 22 17 15 12 12 9 4 5 3 1 6 2 2 1 2 0 2 1 0 0 1 1 0 0 1 0 2 0 0 0 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 19520 count: 795213 average: 3980.28 | standard deviation: 6214.05 | 2367 8989 16262 21781 20893 25190 28254 29586 25661 22626 24278 23085 19116 17158 15560 14786 12693 11723 11422 9539 9375 9108 9013 8099 7236 7910 8080 7444 7303 7019 7374 7036 7048 7598 6668 7111 7166 7768 7191 6845 7679 7799 7673 7710 7667 8206 8031 8008 8632 7748 8177 8242 8718 8331 7736 8254 8467 7936 7684 7323 7701 7199 6981 6919 6216 6337 6018 5989 5426 4831 4902 4625 4293 3782 3464 3552 3151 2882 2715 2314 2186 2084 1953 1677 1406 1498 1375 1132 1013 946 898 735 673 620 507 432 447 388 325 259 259 241 167 189 158 133 121 101 94 71 56 59 58 46 33 24 20 23 11 20 13 14 12 6 8 8 8 3 3 3 0 5 1 2 1 2 0 2 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 20160 count: 428023 average: 3985.66 | standard deviation: 3071.42 | 1341 4792 8854 11442 11028 13607 15350 15835 13872 12154 13070 12188 10069 9250 8281 8040 6575 6219 6238 5252 5061 4920 4934 4490 3977 4248 4405 3962 3980 3744 3941 3790 3916 4099 3658 3852 4044 4095 4033 3634 4075 4370 4109 4225 4080 4320 4281 4500 4642 4208 4395 4521 4552 4491 4048 4484 4481 4344 4308 3941 4180 3795 3719 3767 3324 3276 3218 3215 2875 2563 2622 2407 2219 2189 1983 1839 1605 1681 1532 1309 1177 1135 1088 865 764 744 752 602 532 487 455 402 340 338 286 273 225 210 163 163 162 123 109 100 86 76 65 51 51 39 27 24 27 20 12 18 12 13 9 9 14 8 5 9 4 4 1 1 2 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 2 count: 176 average:     2 | standard deviation: 0 | 0 0 176 ]
-miss_latency_L2Cache: [binsize: 64 max: 7472 count: 647 average: 674.793 | standard deviation: 949.886 | 268 12 13 15 15 8 17 19 26 15 17 12 17 12 15 13 8 11 9 9 4 10 4 9 2 5 4 7 4 5 7 5 1 6 2 2 0 2 5 1 1 3 0 4 1 4 0 2 1 1 0 0 2 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 20160 count: 1182550 average: 4001.69 | standard deviation: 4756.29 | 0 12309 23695 31625 30233 37429 42404 44206 38629 33981 36572 34570 28577 25889 23291 22353 18824 17509 17291 14387 14068 13636 13573 12231 10859 11836 12110 11025 10944 10379 10965 10457 10610 11373 9950 10594 10822 11428 10873 10097 11367 11761 11360 11563 11359 12094 11869 12090 12837 11507 12185 12339 12855 12403 11403 12328 12532 11909 11633 10917 11522 10662 10413 10434 9274 9366 8979 8967 8097 7196 7351 6853 6357 5834 5324 5273 4642 4463 4172 3515 3292 3166 2981 2489 2127 2187 2091 1692 1524 1406 1325 1115 994 941 773 686 662 588 470 410 414 359 272 283 240 206 183 148 143 110 81 82 85 66 43 41 32 36 20 29 25 22 17 15 11 12 9 4 5 3 1 6 2 2 1 2 0 2 1 0 0 1 1 0 0 1 0 2 0 0 0 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 128 max: 15973 count: 39863 average: 3474.22 | standard deviation: 3059.48 | 3252 1444 1398 1562 1647 1339 1171 1187 885 781 762 690 601 508 541 461 437 429 367 398 364 388 369 356 352 322 373 380 339 384 348 368 354 324 375 368 387 434 351 382 387 407 422 372 387 432 443 418 437 449 386 424 415 419 381 410 416 371 358 347 359 332 287 252 266 247 257 237 204 198 173 179 155 137 123 118 114 100 75 108 71 53 60 53 43 55 36 42 21 27 28 22 19 17 20 19 10 10 18 12 7 5 4 6 4 3 3 4 2 0 2 1 0 0 2 1 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15941 count: 39794 average: 3295.79 | standard deviation: 3041.63 | 4782 1655 1558 1885 1460 1216 1095 1024 767 582 578 581 481 425 399 394 385 379 414 334 341 367 365 355 294 341 373 395 346 384 352 369 343 366 342 387 372 425 345 348 417 436 381 450 375 452 455 418 478 391 388 415 419 432 349 389 407 386 346 309 334 304 278 264 226 222 243 207 205 154 152 150 125 137 103 98 85 85 86 76 57 54 54 49 28 48 39 31 20 19 11 23 13 14 12 20 12 9 11 8 4 5 3 1 4 1 2 1 2 1 1 1 0 0 2 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3937 count: 39794 average: 155.313 | standard deviation: 325.711 | 28442 688 527 562 440 392 416 416 507 395 365 403 377 520 392 381 375 301 320 247 178 189 197 243 149 167 143 140 203 123 119 106 96 124 70 70 86 79 79 54 49 49 54 57 45 54 40 27 39 20 16 19 23 27 11 12 12 7 16 13 9 3 9 7 14 5 7 5 6 4 5 3 2 3 1 8 3 2 1 3 3 0 3 2 1 2 1 1 2 3 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 39794 average:    24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39794 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 39794 average: 0.00693572 | standard deviation: 0.104554 | 39598 116 80 ]
-imcomplete_wCC_Times: 69
-miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18931 count: 1182550 average: 3280.19 | standard deviation: 4734.35 | 141942 48966 47072 55633 43296 35639 31964 31286 23173 17373 17650 17262 14327 13035 12298 12751 11656 11626 11795 10382 10673 10823 11510 10529 9635 10721 10839 10357 10393 10244 10930 10531 10721 11289 10411 11003 11380 12024 11548 10831 12139 12561 12113 12253 11915 12616 12467 12557 13088 11754 12285 12325 12583 11654 10505 11095 11416 10431 9898 9334 9576 8652 8285 8227 7047 6945 6498 6330 5534 4805 4805 4626 4002 3650 3187 3144 2779 2621 2497 1957 1794 1753 1586 1373 1074 1131 1000 900 745 682 575 564 504 441 364 315 262 269 217 181 168 144 126 114 85 73 54 51 54 33 33 39 29 28 16 15 12 13 8 10 8 5 8 3 1 2 1 0 1 0 3 0 0 0 1 0 1 0 0 0 0 0 2 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_dir_initial_forward_request: [binsize: 32 max: 3953 count: 1182550 average: 11.2327 | standard deviation: 55.4198 | 1176058 241 310 250 266 280 304 227 229 176 160 152 130 105 129 136 256 216 237 197 169 232 155 125 118 96 123 99 70 73 79 100 64 99 62 60 89 58 49 46 38 44 20 20 30 18 36 27 22 17 23 29 11 13 11 9 19 13 9 11 8 14 5 8 2 4 7 3 6 0 2 6 2 4 4 4 5 2 3 1 0 2 0 1 1 0 3 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 1182550 average:    24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1182550 ]
-miss_latency_dir_first_response_to_completion: [binsize: 32 max: 5007 count: 1182550 average: 686.263 | standard deviation: 462.949 | 0 0 0 28916 38265 33160 37401 39584 55260 42321 40747 40392 40085 53028 38562 36031 33187 30850 38321 27204 26928 26598 26438 34392 26147 25688 25635 25251 31433 21500 18732 16190 14137 16687 11945 11134 10675 9960 12643 9263 8744 8518 8273 10710 7211 6333 5563 5023 5917 4093 3823 3621 3391 4336 2997 2800 2797 2617 3266 2331 2041 1720 1632 1921 1373 1234 1199 1071 1382 927 873 878 782 1004 681 634 524 463 542 396 347 338 288 365 264 234 227 203 206 169 154 133 127 128 93 83 79 72 78 73 65 42 42 64 28 39 28 19 21 18 17 14 17 17 16 11 10 7 14 15 6 6 5 7 3 3 1 1 4 3 1 2 1 4 1 0 0 1 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 4 max: 483 count: 1224663 average: 41.1802 | standard deviation: 90.1625 | 1000304 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7005 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 10 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 4 max: 483 count: 795679 average: 22.1087 | standard deviation: 64.9617 | 711546 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 1 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 4 max: 442 count: 428984 average: 76.5539 | standard deviation: 115.993 | 288758 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 1000304 average:     2 | standard deviation: 0 | 0 0 1000304 ]
+miss_latency_Directory: [binsize: 2 max: 358 count: 2 average:   303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache_wCC: [binsize: 4 max: 483 count: 224357 average: 215.864 | standard deviation: 83.754 | 0 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7004 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 2 count: 140230 average: 1.99996 | standard deviation: 0.00925064 | 3 0 140227 ]
+miss_latency_wCC_initial_forward_request: [binsize: 4 max: 459 count: 140230 average: 203.958 | standard deviation: 78.4902 | 0 0 6212 20 98 67 95 140 250 0 0 1 1158 74 1037 220 349 551 1081 592 0 5 113 112 1635 2713 530 808 1650 3233 16 19 103 216 2099 6872 447 621 1222 4793 1914 74 320 1024 1743 7379 3458 282 513 2610 6341 300 767 1912 1837 6522 4902 99 141 770 6765 2933 1663 2774 3916 2940 3746 439 31 325 4465 13834 2498 2827 2733 1196 1565 289 2 23 232 2118 382 0 0 0 0 0 0 1 14 199 231 1 0 0 0 0 0 0 1 3 21 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 140230 average:    24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 140230 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 140230 average: 0.125494 | standard deviation: 0.335859 | 122846 17170 214 ]
+imcomplete_wCC_Times: 84127
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 2 count: 2 average:     2 | standard deviation: 0 | 0 0 2 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 8 count: 2 average:     8 | standard deviation: 0 | 0 0 0 0 0 0 0 0 2 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 2 average:    24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+miss_latency_dir_first_response_to_completion: [binsize: 2 max: 324 count: 2 average:   269 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 0
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 117 average:     2 | standard deviation: 0 | 0 0 117 ]
-miss_latency_LD_L2Cache: [binsize: 64 max: 7472 count: 423 average: 721.243 | standard deviation: 1002.1 | 169 5 10 9 10 6 12 13 19 10 10 7 10 7 12 6 7 4 6 6 3 7 1 8 0 4 3 5 3 2 7 5 1 4 2 1 0 2 4 0 1 3 0 3 1 4 0 0 0 0 0 0 2 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_Directory: [binsize: 128 max: 19520 count: 768954 average: 3998.96 | standard deviation: 6374.36 | 0 8067 15339 20744 19789 24322 27482 28826 25078 22121 23786 22622 18734 16823 15188 14462 12401 11434 11189 9267 9144 8876 8767 7886 7020 7694 7848 7175 7086 6778 7145 6786 6816 7394 6443 6876 6929 7495 6966 6597 7427 7531 7396 7462 7396 7925 7739 7737 8360 7461 7913 7959 8456 8051 7484 7985 8193 7682 7464 7088 7471 6971 6801 6771 6039 6174 5851 5848 5297 4701 4785 4511 4188 3693 3385 3469 3070 2819 2665 2239 2143 2043 1914 1647 1379 1466 1350 1105 1001 927 881 722 661 612 493 421 439 384 312 253 257 239 164 183 156 132 119 97 92 71 54 58 58 46 31 23 20 23 11 20 12 14 12 6 8 8 8 3 3 3 0 5 1 2 1 2 0 2 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15443 count: 25719 average: 3493.59 | standard deviation: 3062.21 | 2076 903 907 1012 1075 851 755 742 572 493 482 454 378 327 367 312 287 286 231 268 227 229 241 213 216 216 230 268 217 241 227 249 232 204 224 235 237 273 225 248 252 267 277 248 270 281 292 271 272 287 263 283 262 280 252 269 274 254 219 235 230 228 180 148 177 163 167 141 129 130 117 114 105 89 79 83 81 63 50 75 43 41 39 30 27 32 25 27 12 19 17 13 12 8 14 11 8 4 13 6 2 2 3 6 2 1 2 4 2 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 59 average:     2 | standard deviation: 0 | 0 0 59 ]
-miss_latency_ST_L2Cache: [binsize: 32 max: 4752 count: 224 average: 587.076 | standard deviation: 837.634 | 90 9 2 5 3 0 3 3 1 4 1 1 2 3 2 4 5 2 3 2 6 1 4 1 4 3 3 2 0 3 2 5 0 1 5 2 1 2 0 3 0 1 1 2 0 3 0 1 0 2 0 1 1 0 0 2 1 0 2 1 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 128 max: 20160 count: 413596 average: 4006.77 | standard deviation: 3069.87 | 0 4242 8356 10881 10444 13107 14922 15380 13551 11860 12786 11948 9843 9066 8103 7891 6423 6075 6102 5120 4924 4760 4806 4345 3839 4142 4262 3850 3858 3601 3820 3671 3794 3979 3507 3718 3893 3933 3907 3500 3940 4230 3964 4101 3963 4169 4130 4353 4477 4046 4272 4380 4399 4352 3919 4343 4339 4227 4169 3829 4051 3691 3612 3663 3235 3192 3128 3119 2800 2495 2566 2342 2169 2141 1939 1804 1572 1644 1507 1276 1149 1123 1067 842 748 721 741 587 523 479 444 393 333 329 280 265 223 204 158 157 157 120 108 100 84 74 64 51 51 39 27 24 27 20 12 18 12 13 9 9 13 8 5 9 3 4 1 1 2 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15973 count: 14144 average:  3439 | standard deviation: 3054.29 | 1176 541 491 550 572 488 416 445 313 288 280 236 223 181 174 149 150 143 136 130 137 159 128 143 136 106 143 112 122 143 121 119 122 120 151 133 150 161 126 134 135 140 145 124 117 151 151 147 165 162 123 141 153 139 129 141 142 117 139 112 129 104 107 104 89 84 90 96 75 68 56 65 50 48 44 35 33 37 25 33 28 12 21 23 16 23 11 15 9 8 11 9 7 9 6 8 2 6 5 6 5 3 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 711546 average:     2 | standard deviation: 0 | 0 0 711546 ]
+miss_latency_LD_Directory: [binsize: 2 max: 358 count: 2 average:   303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 483 count: 84131 average: 192.173 | standard deviation: 86.9918 | 0 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 0 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 288758 average:     2 | standard deviation: 0 | 0 0 288758 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 442 count: 140226 average: 230.078 | standard deviation: 78.3858 | 0 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -124,242 +120,203 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev
 Resource Usage
 --------------
 page_size: 4096
-user_time: 245
+user_time: 37
 system_time: 0
-page_reclaims: 10326
+page_reclaims: 9470
 page_faults: 0
 swaps: 0
-block_inputs: 0
+block_inputs: 16
 block_outputs: 0
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 3667506 29340048
-total_msg_count_Response_Data: 3667212 264039264
-total_msg_count_Response_Control: 25550289 204402312
-total_msg_count_Writeback_Data: 1267908 91289376
-total_msg_count_Writeback_Control: 9104502 72836016
-total_msg_count_Broadcast_Control: 18335460 146683680
-total_msg_count_Unblock_Control: 3667290 29338320
-total_msgs: 65260167 total_bytes: 837929016
+total_msg_count_Request_Control: 724737 5797896
+total_msg_count_Response_Data: 603819 43474968
+total_msg_count_Response_Control: 2526462 20211696
+total_msg_count_Broadcast_Control: 2103450 16827600
+total_msg_count_Unblock_Control: 673075 5384600
+total_msgs: 6631543 total_bytes: 91696760
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.199775
-  links_utilized_percent_switch_0_link_0: 0.119966 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.279585 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Data: 152750 10998000 [ 0 0 0 0 152750 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 1064219 8513752 [ 0 0 0 0 1064219 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 144063 1152504 [ 0 0 0 144063 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Broadcast_Control: 1069616 8556928 [ 0 0 0 1069616 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 152755 1222040 [ 0 0 152755 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 4971 357912 [ 0 0 0 0 4971 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Control: 1064653 8517224 [ 0 0 0 0 1064653 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 53143 3826296 [ 0 0 0 0 0 53143 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 234981 1879848 [ 0 0 144063 0 0 90918 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Unblock_Control: 152753 1222024 [ 0 0 0 0 0 152753 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.346445
+  links_utilized_percent_switch_0_link_0: 0.182474 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.510416 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 28166 225328 [ 0 0 28166 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 19532 1406304 [ 0 0 0 0 19532 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 105318 842544 [ 0 0 0 0 105318 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 28164 225312 [ 0 0 0 0 0 28164 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.199595
-  links_utilized_percent_switch_1_link_0: 0.11991 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.279281 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Data: 152625 10989000 [ 0 0 0 0 152625 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Response_Control: 1063478 8507824 [ 0 0 0 0 1063478 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 144096 1152768 [ 0 0 0 144096 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Broadcast_Control: 1069741 8557928 [ 0 0 0 1069741 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 152629 1221032 [ 0 0 152629 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 5123 368856 [ 0 0 0 0 5123 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 1064628 8517024 [ 0 0 0 0 1064628 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 52709 3795048 [ 0 0 0 0 0 52709 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 235480 1883840 [ 0 0 144096 0 0 91384 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Unblock_Control: 152628 1221024 [ 0 0 0 0 0 152628 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.345452
+  links_utilized_percent_switch_1_link_0: 0.181714 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.50919 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 27960 223680 [ 0 0 27960 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 19481 1402632 [ 0 0 0 0 19481 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 105379 843032 [ 0 0 0 0 105379 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 27958 223664 [ 0 0 0 0 0 27958 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.199688
-  links_utilized_percent_switch_2_link_0: 0.119941 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.279435 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 152700 10994400 [ 0 0 0 0 152700 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Control: 1063864 8510912 [ 0 0 0 0 1063864 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 144072 1152576 [ 0 0 0 144072 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Broadcast_Control: 1069676 8557408 [ 0 0 0 1069676 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 152703 1221624 [ 0 0 152703 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 4948 356256 [ 0 0 0 0 4948 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Control: 1064736 8517888 [ 0 0 0 0 1064736 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 53026 3817872 [ 0 0 0 0 0 53026 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Control: 235117 1880936 [ 0 0 144072 0 0 91045 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Unblock_Control: 152703 1221624 [ 0 0 0 0 0 152703 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.347269
+  links_utilized_percent_switch_2_link_0: 0.182656 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.511881 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 28157 225256 [ 0 0 28157 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 19660 1415520 [ 0 0 0 0 19660 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 105153 841224 [ 0 0 0 0 105153 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 28155 225240 [ 0 0 0 0 0 28155 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.199488
-  links_utilized_percent_switch_3_link_0: 0.119939 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.279037 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Data: 152694 10993968 [ 0 0 0 0 152694 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 1063941 8511528 [ 0 0 0 0 1063941 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 143990 1151920 [ 0 0 0 143990 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Broadcast_Control: 1069671 8557368 [ 0 0 0 1069671 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 152697 1221576 [ 0 0 152697 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 4898 352656 [ 0 0 0 0 4898 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Control: 1064781 8518248 [ 0 0 0 0 1064781 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 52720 3795840 [ 0 0 0 0 0 52720 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Control: 235255 1882040 [ 0 0 143990 0 0 91265 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Unblock_Control: 152700 1221600 [ 0 0 0 0 0 152700 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_3: 0.346043
+  links_utilized_percent_switch_3_link_0: 0.181891 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.510195 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 27975 223800 [ 0 0 27975 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 19562 1408464 [ 0 0 0 0 19562 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 105284 842272 [ 0 0 0 0 105284 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 27973 223784 [ 0 0 0 0 0 27973 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0.199798
-  links_utilized_percent_switch_4_link_0: 0.120111 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 0.279484 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_4_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Data: 153036 11018592 [ 0 0 0 0 153036 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Response_Control: 1066246 8529968 [ 0 0 0 0 1066246 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 144181 1153448 [ 0 0 0 144181 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Broadcast_Control: 1069334 8554672 [ 0 0 0 1069334 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Request_Control: 153039 1224312 [ 0 0 153039 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 4983 358776 [ 0 0 0 0 4983 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Control: 1064358 8514864 [ 0 0 0 0 1064358 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Data: 52970 3813840 [ 0 0 0 0 0 52970 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Writeback_Control: 235391 1883128 [ 0 0 144181 0 0 91210 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Unblock_Control: 153037 1224296 [ 0 0 0 0 0 153037 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_4: 0.346195
+  links_utilized_percent_switch_4_link_0: 0.182121 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0.51027 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 28045 224360 [ 0 0 28045 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 19556 1408032 [ 0 0 0 0 19556 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 105248 841984 [ 0 0 0 0 105248 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 28043 224344 [ 0 0 0 0 0 28043 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0.199507
-  links_utilized_percent_switch_5_link_0: 0.12002 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.278994 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_5_link_0_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Data: 152880 11007360 [ 0 0 0 0 152880 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Response_Control: 1065109 8520872 [ 0 0 0 0 1065109 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 143798 1150384 [ 0 0 0 143798 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Broadcast_Control: 1069488 8555904 [ 0 0 0 1069488 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Request_Control: 152883 1223064 [ 0 0 152883 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 5100 367200 [ 0 0 0 0 5100 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Control: 1064397 8515176 [ 0 0 0 0 1064397 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Data: 52502 3780144 [ 0 0 0 0 0 52502 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Writeback_Control: 235092 1880736 [ 0 0 143798 0 0 91294 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Unblock_Control: 152884 1223072 [ 0 0 0 0 0 152884 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_5: 0.346499
+  links_utilized_percent_switch_5_link_0: 0.181925 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.511074 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 27996 223968 [ 0 0 27996 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 19618 1412496 [ 0 0 0 0 19618 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 105319 842552 [ 0 0 0 0 105319 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 27994 223952 [ 0 0 0 0 0 27994 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0.199626
-  links_utilized_percent_switch_6_link_0: 0.120193 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 0.279058 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_6_link_0_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Data: 153186 11029392 [ 0 0 0 0 153186 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Response_Control: 1067322 8538576 [ 0 0 0 0 1067322 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 144401 1155208 [ 0 0 0 144401 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Broadcast_Control: 1069185 8553480 [ 0 0 0 1069185 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Request_Control: 153191 1225528 [ 0 0 153191 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 4877 351144 [ 0 0 0 0 4877 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Control: 1064317 8514536 [ 0 0 0 0 1064317 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Data: 52596 3786912 [ 0 0 0 0 0 52596 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Writeback_Control: 236204 1889632 [ 0 0 144401 0 0 91803 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Unblock_Control: 153190 1225520 [ 0 0 0 0 0 153190 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_6: 0.34662
+  links_utilized_percent_switch_6_link_0: 0.182139 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 0.511101 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 28036 224288 [ 0 0 28036 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 19615 1412280 [ 0 0 0 0 19615 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 105283 842264 [ 0 0 0 0 105283 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 28035 224280 [ 0 0 0 0 0 28035 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0.199581
-  links_utilized_percent_switch_7_link_0: 0.11985 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 0.279313 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_7_link_0_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Data: 152533 10982376 [ 0 0 0 0 152533 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Response_Control: 1062584 8500672 [ 0 0 0 0 1062584 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 143895 1151160 [ 0 0 0 143895 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Broadcast_Control: 1069837 8558696 [ 0 0 0 1069837 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Request_Control: 152536 1220288 [ 0 0 152536 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 4954 356688 [ 0 0 0 0 4954 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Control: 1064893 8519144 [ 0 0 0 0 1064893 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Data: 52970 3813840 [ 0 0 0 0 0 52970 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Writeback_Control: 234818 1878544 [ 0 0 143895 0 0 90923 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Unblock_Control: 152535 1220280 [ 0 0 0 0 0 152535 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_7: 0.346674
+  links_utilized_percent_switch_7_link_0: 0.182194 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 0.511154 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 28038 224304 [ 0 0 28038 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 19631 1413432 [ 0 0 0 0 19631 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 105170 841360 [ 0 0 0 0 105170 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 28037 224296 [ 0 0 0 0 0 28037 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 0.988626
-  links_utilized_percent_switch_8_link_0: 0.267047 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 1.7102 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_8_link_0_Request_Control: 1222433 9779464 [ 0 0 1222433 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Data: 422636 30429792 [ 0 0 0 0 0 422636 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Writeback_Control: 1882338 15058704 [ 0 0 1152496 0 0 729842 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Unblock_Control: 1222430 9779440 [ 0 0 0 0 0 1222430 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Request_Control: 69 552 [ 0 0 0 69 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 1182550 85143600 [ 0 0 0 0 1182550 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 1152496 9219968 [ 0 0 0 1152496 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Broadcast_Control: 1222364 9778912 [ 0 0 0 1222364 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_8: 0.20393
+  links_utilized_percent_switch_8_link_0: 0.169691 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 0.23817 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 17206 137648 [ 0 0 0 17206 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Broadcast_Control: 140230 1121840 [ 0 0 0 140230 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 9
 switch_9_outlinks: 9
-links_utilized_percent_switch_9: 0.545323
-  links_utilized_percent_switch_9_link_0: 0.479862 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 0.479638 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_2: 0.479765 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_3: 0.479757 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_4: 0.480445 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_5: 0.480081 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_6: 0.480773 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_7: 0.479398 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_8: 1.06819 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Data: 152750 10998000 [ 0 0 0 0 152750 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Response_Control: 1064219 8513752 [ 0 0 0 0 1064219 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 144063 1152504 [ 0 0 0 144063 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Broadcast_Control: 1069616 8556928 [ 0 0 0 1069616 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 152625 10989000 [ 0 0 0 0 152625 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Control: 1063478 8507824 [ 0 0 0 0 1063478 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 144096 1152768 [ 0 0 0 144096 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Broadcast_Control: 1069741 8557928 [ 0 0 0 1069741 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Data: 152700 10994400 [ 0 0 0 0 152700 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Control: 1063864 8510912 [ 0 0 0 0 1063864 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Writeback_Control: 144072 1152576 [ 0 0 0 144072 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Broadcast_Control: 1069676 8557408 [ 0 0 0 1069676 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Data: 152694 10993968 [ 0 0 0 0 152694 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Control: 1063941 8511528 [ 0 0 0 0 1063941 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Writeback_Control: 143990 1151920 [ 0 0 0 143990 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Broadcast_Control: 1069671 8557368 [ 0 0 0 1069671 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Data: 153036 11018592 [ 0 0 0 0 153036 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Control: 1066246 8529968 [ 0 0 0 0 1066246 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Writeback_Control: 144181 1153448 [ 0 0 0 144181 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Broadcast_Control: 1069334 8554672 [ 0 0 0 1069334 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Data: 152880 11007360 [ 0 0 0 0 152880 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Control: 1065109 8520872 [ 0 0 0 0 1065109 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Writeback_Control: 143798 1150384 [ 0 0 0 143798 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Broadcast_Control: 1069488 8555904 [ 0 0 0 1069488 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Data: 153186 11029392 [ 0 0 0 0 153186 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Control: 1067322 8538576 [ 0 0 0 0 1067322 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Writeback_Control: 144401 1155208 [ 0 0 0 144401 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Broadcast_Control: 1069185 8553480 [ 0 0 0 1069185 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Data: 152533 10982376 [ 0 0 0 0 152533 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Control: 1062584 8500672 [ 0 0 0 0 1062584 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Writeback_Control: 143895 1151160 [ 0 0 0 143895 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Broadcast_Control: 1069837 8558696 [ 0 0 0 1069837 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Request_Control: 1222433 9779464 [ 0 0 1222433 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Data: 422636 30429792 [ 0 0 0 0 0 422636 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Writeback_Control: 1882338 15058704 [ 0 0 1152496 0 0 729842 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Unblock_Control: 1222430 9779440 [ 0 0 0 0 0 1222430 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 0.723025
+  links_utilized_percent_switch_9_link_0: 0.729898 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 0.726855 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 0.730626 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 0.727564 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 0.728482 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 0.727702 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 0.728558 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 0.728777 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 0.678764 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.L1IcacheMemory
   system.l1_cntrl0.L1IcacheMemory_total_misses: 0
@@ -370,242 +327,229 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 152935
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 152935
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 28166
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 28166
   system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   64.8125%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   35.1875%
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   37.8364%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   62.1636%
 
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   152935    100%
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   28166    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 152935
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 152935
+  system.l1_cntrl0.L2cacheMemory_total_misses: 28166
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 28166
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   64.8125%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   35.1875%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   37.8364%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   62.1636%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   152935    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   28166    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [99535 99829 100085 99136 99177 99443 99228 99488 ] 795921
+Load [99210 99376 100000 99219 99692 99063 99665 99458 ] 795683
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [53745 53262 53330 53614 53839 53432 53726 53441 ] 428389
-L2_Replacement [153026 152866 153174 152520 152738 152617 152685 152681 ] 1222307
-L1_to_L2 [1699797 1701512 1708689 1694889 1695562 1699555 1697205 1695495 ] 13592704
-Trigger_L2_to_L1D [143 150 148 151 180 162 162 168 ] 1264
+Store [53780 53529 53389 53948 53675 53375 53908 53390 ] 428994
+L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-Complete_L2_to_L1 [143 150 148 151 180 162 162 168 ] 1264
-Other_GETX [374083 374559 374492 374205 373994 374401 374093 374381 ] 2994208
-Other_GETS [695251 694929 694693 695632 695622 695340 695583 695290 ] 5562340
-Merged_GETS [7 9 9 10 8 10 8 8 ] 69
+Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
+Other_GETX [122682 122718 122712 122644 122719 122751 122647 122709 ] 981582
+Other_GETS [3 3 3 3 2 2 2 3 ] 21
+Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206
 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 Invalidate [0 0 0 0 0 0 0 0 ] 0
-Ack [1066123 1064987 1067202 1062483 1064107 1063381 1063754 1063815 ] 8515852
-Shared_Ack [123 122 120 101 112 97 110 126 ] 911
-Data [5950 5907 5831 5728 5802 5574 5668 5755 ] 46215
-Shared_Data [2067 2123 2065 2036 2070 1972 2052 2038 ] 16423
-Exclusive_Data [145019 144850 145290 144769 144878 145079 144980 144901 ] 1159766
-Writeback_Ack [144181 143798 144401 143895 144063 144096 144072 143990 ] 1152496
+Ack [105371 105154 105165 105596 105154 104959 105564 105191 ] 842154
+Shared_Ack [0 0 0 0 0 0 0 0 ] 0
+Data [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428
+Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130
+Exclusive_Data [15418 15411 15413 15387 15339 15302 15409 15344 ] 123023
+Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
-All_acks [2171 2229 2168 2123 2163 2061 2147 2146 ] 17208
-All_acks_no_sharers [150865 150653 151021 150410 150588 150564 150555 150549 ] 1205205
+All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130
+All_acks_no_sharers [17544 17508 17514 17582 17508 17476 17580 17517 ] 140229
 
  - Transitions -
-I  Load [99378 99698 99939 98997 99005 99286 99052 99334 ] 794689
+I  Load [10500 10487 10521 10455 10657 10484 10576 10457 ] 84137
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [53661 53180 53249 53537 53748 53342 53646 53360 ] 427723
-I  L2_Replacement [2971 3090 2945 2931 2939 3020 2985 2971 ] 23852
-I  L1_to_L2 [649 680 667 679 598 653 650 638 ] 5214
-I  Trigger_L2_to_L1D [5 2 8 5 6 2 1 4 ] 33
+I  Store [5743 5634 5649 5815 5592 5753 5650 5790 ] 45626
+I  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+I  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+I  Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 I  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-I  Other_GETX [372211 372642 372741 372402 372213 372557 372267 372508 ] 2979541
-I  Other_GETS [691950 691574 691373 692315 692230 691866 692295 692094 ] 5535697
+I  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+I  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-I  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 I  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-S  Load [2 2 0 0 3 3 4 5 ] 19
+S  Load [18002 18238 18415 17804 18407 18155 18219 18081 ] 145321
 S  Ifetch [0 0 0 0 0 0 0 0 ] 0
-S  Store [0 3 0 2 1 1 3 2 ] 12
-S  L2_Replacement [5874 5978 5827 5694 5736 5501 5628 5720 ] 45958
-S  L1_to_L2 [5937 6035 5876 5736 5789 5558 5672 5775 ] 46378
-S  Trigger_L2_to_L1D [5 7 1 3 9 7 10 7 ] 49
+S  Store [9708 9676 9707 9635 9816 9635 9796 9625 ] 77598
+S  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+S  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+S  Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 S  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-S  Other_GETX [73 65 58 57 62 67 47 60 ] 489
-S  Other_GETS [115 105 122 102 132 122 105 108 ] 911
+S  Other_GETX [791 810 814 820 840 847 779 831 ] 6532
+S  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-S  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 S  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-O  Load [0 3 1 0 2 2 2 0 ] 10
+O  Load [3730 3928 4020 4060 4122 3754 4001 3925 ] 31540
 O  Ifetch [0 0 0 0 0 0 0 0 ] 0
-O  Store [0 2 3 0 1 0 2 1 ] 9
-O  L2_Replacement [2042 2030 1928 2030 2034 2118 1959 1937 ] 16078
-O  L1_to_L2 [435 455 385 450 468 458 455 434 ] 3540
-O  Trigger_L2_to_L1D [0 8 4 1 8 2 5 1 ] 29
+O  Store [2094 2199 2159 2133 2101 2088 2135 2103 ] 17012
+O  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+O  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+O  Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 O  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-O  Other_GETX [15 12 16 12 16 13 18 13 ] 115
-O  Other_GETS [20 22 24 23 28 27 21 20 ] 185
-O  Merged_GETS [3 4 7 5 5 4 3 4 ] 35
+O  Other_GETX [25 17 24 21 28 19 29 31 ] 194
+O  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+O  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-O  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 O  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-M  Load [44 35 46 36 37 47 48 44 ] 337
+M  Load [0 0 0 0 1 1 1 0 ] 3
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [19 20 17 27 19 25 17 19 ] 163
-M  L2_Replacement [90283 90403 91011 90081 90028 90430 90271 90451 ] 722958
-M  L1_to_L2 [92829 93023 93501 92610 92598 93076 92754 92971 ] 743362
-M  Trigger_L2_to_L1D [81 91 94 94 89 95 94 111 ] 749
+M  Store [0 0 0 0 1 1 1 0 ] 3
+M  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+M  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+M  Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 M  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-M  Other_GETX [1067 1179 1072 1089 1101 1126 1103 1126 ] 8863
-M  Other_GETS [2053 2039 1945 2037 2048 2125 1974 1948 ] 16169
-M  Merged_GETS [2 1 2 3 3 4 3 2 ] 20
+M  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+M  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+M  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 M  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-M  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 M  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-MM  Load [24 15 15 20 27 25 27 21 ] 174
+MM  Load [66978 66723 67044 66900 66505 66669 66868 66995 ] 534682
 MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MM  Store [19 11 21 10 20 16 9 14 ] 120
-MM  L2_Replacement [51856 51365 51463 51784 52001 51548 51842 51602 ] 413461
-MM  L1_to_L2 [53325 52830 52899 53202 53471 53040 53323 53038 ] 425128
-MM  Trigger_L2_to_L1D [52 42 41 48 68 56 52 45 ] 404
+MM  Store [36235 36020 35874 36365 36165 35898 36326 35872 ] 288755
+MM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM  Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0
 MM  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
-MM  Other_GETX [712 654 595 640 595 631 647 665 ] 5139
-MM  Other_GETS [1107 1181 1208 1137 1170 1184 1172 1109 ] 9268
-MM  Merged_GETS [2 4 0 2 0 2 2 2 ] 14
+MM  Other_GETX [15425 15292 15330 15427 15379 15368 15416 15383 ] 123020
+MM  Other_GETS [0 0 0 0 0 1 0 0 ] 1
+MM  Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206
 MM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-MM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MM  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
 IM  Load [0 0 0 0 0 0 0 0 ] 0
 IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IM  Store [0 0 0 0 0 0 0 0 ] 0
 IM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IM  L1_to_L2 [539558 542842 538232 540761 543621 538326 538778 539689 ] 4321807
-IM  Other_GETX [1 1 5 1 2 3 2 4 ] 19
-IM  Other_GETS [1 3 6 4 5 3 4 3 ] 29
+IM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+IM  Other_GETX [61926 61585 61837 61982 61426 61580 61822 61858 ] 494016
+IM  Other_GETS [0 0 1 0 0 0 0 2 ] 3
 IM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-IM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IM  Ack [368543 365321 365720 367312 369025 366472 368657 366475 ] 2937525
-IM  Data [2070 1981 2009 2009 2072 1976 2039 2009 ] 16165
-IM  Exclusive_Data [51591 51199 51239 51528 51674 51365 51607 51351 ] 411554
+IM  Ack [50324 50375 50462 50772 50076 50008 49747 50687 ] 402451
+IM  Data [1296 1262 1251 1350 1269 1317 1265 1314 ] 10324
+IM  Exclusive_Data [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020
 
 SM  Load [0 0 0 0 0 0 0 0 ] 0
 SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SM  Store [0 0 0 0 0 0 0 0 ] 0
 SM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-SM  L1_to_L2 [0 0 0 0 0 1 1 3 ] 5
-SM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+SM  Other_GETX [8985 8947 8938 8894 9021 8880 8974 8855 ] 71494
 SM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 SM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-SM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 SM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-SM  Ack [0 13 0 10 7 7 16 14 ] 67
-SM  Data [0 3 0 2 1 1 3 2 ] 12
-SM  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+SM  Ack [2116 2161 2439 2130 2490 2249 2469 2247 ] 18301
+SM  Data [723 729 769 741 795 755 822 770 ] 6104
 
 OM  Load [0 0 0 0 0 0 0 0 ] 0
 OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 OM  Store [0 0 0 0 0 0 0 0 ] 0
 OM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 OM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
-OM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Other_GETX [1987 2093 2078 2029 1996 1986 2051 2014 ] 16234
 OM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-OM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OM  Invalidate [0 0 0 0 0 0 0 0 ] 0
-OM  Ack [0 14 21 0 7 0 14 7 ] 63
+OM  Ack [749 742 567 728 735 714 588 623 ] 5446
 OM  All_acks [0 0 0 0 0 0 0 0 ] 0
-OM  All_acks_no_sharers [0 2 3 0 1 0 2 1 ] 9
+OM  All_acks_no_sharers [107 106 81 104 105 102 84 89 ] 778
 
 ISM  Load [0 0 0 0 0 0 0 0 ] 0
 ISM  Ifetch [0 0 0 0 0 0 0 0 ] 0
 ISM  Store [0 0 0 0 0 0 0 0 ] 0
 ISM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-ISM  L1_to_L2 [0 0 4 0 0 0 0 0 ] 4
-ISM  Ack [84 65 58 53 39 31 61 37 ] 428
-ISM  All_acks_no_sharers [2070 1984 2009 2011 2073 1977 2042 2011 ] 16177
+ISM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+ISM  Ack [6059 6066 6055 6411 6149 6074 6336 6177 ] 49327
+ISM  All_acks_no_sharers [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428
 
 M_W  Load [0 0 0 0 0 0 0 0 ] 0
 M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 M_W  Store [0 0 0 0 0 0 0 0 ] 0
 M_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-M_W  L1_to_L2 [72 52 30 60 49 82 77 110 ] 532
-M_W  Ack [3358 3397 3332 3546 3317 3311 3651 3384 ] 27296
-M_W  All_acks_no_sharers [93428 93651 94051 93241 93204 93714 93373 93550 ] 748212
+M_W  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+M_W  Ack [0 0 0 0 0 0 1 0 ] 1
+M_W  All_acks_no_sharers [0 0 0 0 1 1 1 0 ] 3
 
 MM_W  Load [0 0 0 0 0 0 0 0 ] 0
 MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
 MM_W  Store [0 0 0 0 0 0 0 0 ] 0
 MM_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MM_W  L1_to_L2 [55 48 93 90 84 118 105 65 ] 658
-MM_W  Ack [5222 5127 5236 5525 5374 5150 5095 5261 ] 41990
-MM_W  All_acks_no_sharers [51591 51199 51239 51528 51674 51365 51607 51351 ] 411554
+MM_W  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM_W  Ack [46123 45810 45642 45555 45697 45907 46418 45457 ] 366609
+MM_W  All_acks_no_sharers [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020
 
 IS  Load [0 0 0 0 0 0 0 0 ] 0
 IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 IS  Store [0 0 0 0 0 0 0 0 ] 0
 IS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IS  L1_to_L2 [1006185 1004923 1016403 1000684 998249 1007712 1004842 1002120 ] 8041118
-IS  Other_GETX [3 4 3 2 3 1 8 0 ] 24
-IS  Other_GETS [4 3 9 10 6 9 8 4 ] 53
+IS  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+IS  Other_GETX [33543 33974 33691 33471 34029 34071 33576 33737 ] 270092
+IS  Other_GETS [3 3 2 3 2 1 2 1 ] 17
 IS  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-IS  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IS  Invalidate [0 0 0 0 0 0 0 0 ] 0
-IS  Ack [682852 684688 686562 680152 680140 682667 680182 682564 ] 5459807
-IS  Shared_Ack [115 113 114 100 103 93 103 120 ] 861
-IS  Data [3880 3923 3822 3717 3729 3597 3626 3744 ] 30038
-IS  Shared_Data [2067 2123 2065 2036 2070 1972 2052 2038 ] 16423
-IS  Exclusive_Data [93428 93651 94051 93241 93204 93714 93373 93550 ] 748212
+IS  Ack [0 0 0 0 7 7 5 0 ] 19
+IS  Shared_Ack [0 0 0 0 0 0 0 0 ] 0
+IS  Data [0 0 0 0 0 0 0 0 ] 0
+IS  Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130
+IS  Exclusive_Data [0 0 0 0 1 1 1 0 ] 3
 
 SS  Load [0 0 0 0 0 0 0 0 ] 0
 SS  Ifetch [0 0 0 0 0 0 0 0 ] 0
 SS  Store [0 0 0 0 0 0 0 0 ] 0
 SS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-SS  L1_to_L2 [129 89 102 92 113 107 138 70 ] 840
-SS  Ack [6064 6362 6273 5885 6198 5743 6078 6073 ] 48676
-SS  Shared_Ack [8 9 6 1 9 4 7 6 ] 50
-SS  All_acks [2171 2229 2168 2123 2163 2061 2147 2146 ] 17208
-SS  All_acks_no_sharers [3776 3817 3719 3630 3636 3508 3531 3636 ] 29253
+SS  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+SS  Ack [0 0 0 0 0 0 0 0 ] 0
+SS  Shared_Ack [0 0 0 0 0 0 0 0 ] 0
+SS  All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130
+SS  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
 
-OI  Load [0 1 0 0 0 0 2 1 ] 4
+OI  Load [0 0 0 0 0 0 0 0 ] 0
 OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
-OI  Store [0 1 0 0 0 0 0 0 ] 1
+OI  Store [0 0 0 0 0 0 0 0 ] 0
 OI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 OI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-OI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-OI  Writeback_Ack [2043 2032 1934 2034 2037 2122 1963 1941 ] 16106
+OI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
 
-MI  Load [26 13 23 19 21 18 24 9 ] 153
+MI  Load [0 0 0 0 0 0 0 0 ] 0
 MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MI  Store [13 9 9 6 13 10 14 11 ] 85
+MI  Store [0 0 0 0 0 0 0 0 ] 0
 MI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
 MI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
-MI  Other_GETX [1 2 2 2 2 3 1 5 ] 18
-MI  Other_GETS [1 2 6 4 3 4 4 4 ] 28
+MI  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+MI  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-MI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MI  Invalidate [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack [142137 141764 142465 141859 142024 141971 142108 142044 ] 1136372
+MI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
 
 II  Load [0 0 0 0 0 0 0 0 ] 0
 II  Ifetch [0 0 0 0 0 0 0 0 ] 0
@@ -615,74 +559,68 @@ II  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
 II  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 II  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 II  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-II  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 II  Invalidate [0 0 0 0 0 0 0 0 ] 0
-II  Writeback_Ack [1 2 2 2 2 3 1 5 ] 18
+II  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
 II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
-IT  Load [3 1 4 1 1 1 0 3 ] 14
+IT  Load [0 0 0 0 0 0 0 0 ] 0
 IT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-IT  Store [0 0 2 1 0 0 0 0 ] 3
+IT  Store [0 0 0 0 0 0 0 0 ] 0
 IT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-IT  L1_to_L2 [14 3 22 2 1 4 0 16 ] 62
-IT  Complete_L2_to_L1 [5 2 8 5 6 2 1 4 ] 33
+IT  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+IT  Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
 IT  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 IT  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 IT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 IT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-IT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 IT  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-ST  Load [2 3 1 2 3 3 3 3 ] 20
+ST  Load [0 0 0 0 0 0 0 0 ] 0
 ST  Ifetch [0 0 0 0 0 0 0 0 ] 0
-ST  Store [2 0 0 0 4 1 2 1 ] 10
+ST  Store [0 0 0 0 0 0 0 0 ] 0
 ST  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-ST  L1_to_L2 [23 6 9 13 42 48 24 46 ] 211
-ST  Complete_L2_to_L1 [5 7 1 3 9 7 10 7 ] 49
+ST  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+ST  Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
 ST  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 ST  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 ST  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 ST  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-ST  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 ST  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-OT  Load [0 2 0 1 5 1 1 0 ] 10
+OT  Load [0 0 0 0 0 0 0 0 ] 0
 OT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-OT  Store [0 2 1 0 1 0 3 0 ] 7
+OT  Store [0 0 0 0 0 0 0 0 ] 0
 OT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-OT  L1_to_L2 [0 15 0 10 23 8 16 0 ] 72
-OT  Complete_L2_to_L1 [0 8 4 1 8 2 5 1 ] 29
+OT  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+OT  Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
 OT  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 OT  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 OT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 OT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-OT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 OT  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-MT  Load [37 39 47 38 42 35 45 50 ] 333
+MT  Load [0 0 0 0 0 0 0 0 ] 0
 MT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MT  Store [18 21 16 21 20 19 22 27 ] 164
+MT  Store [0 0 0 0 0 0 0 0 ] 0
 MT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MT  L1_to_L2 [374 324 343 328 308 218 245 407 ] 2547
-MT  Complete_L2_to_L1 [81 91 94 94 89 95 94 111 ] 749
+MT  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MT  Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
 MT  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 MT  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 MT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-MT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MT  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
-MMT  Load [19 17 9 22 31 22 20 18 ] 158
+MMT  Load [0 0 0 0 0 0 0 0 ] 0
 MMT  Ifetch [0 0 0 0 0 0 0 0 ] 0
-MMT  Store [13 13 12 10 12 18 8 6 ] 92
+MMT  Store [0 0 0 0 0 0 0 0 ] 0
 MMT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
-MMT  L1_to_L2 [212 187 123 172 148 146 125 113 ] 1226
-MMT  Complete_L2_to_L1 [52 42 41 48 68 56 52 45 ] 404
+MMT  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MMT  Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0
 MMT  Other_GETX [0 0 0 0 0 0 0 0 ] 0
 MMT  Other_GETS [0 0 0 0 0 0 0 0 ] 0
 MMT  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
 MMT  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
-MMT  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
 MMT  Invalidate [0 0 0 0 0 0 0 0 ] 0
 
 Cache Stats: system.l1_cntrl1.L1IcacheMemory
@@ -694,28 +632,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl1.L1DcacheMemory
-  system.l1_cntrl1.L1DcacheMemory_total_misses: 152791
-  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 152791
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 27960
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 27960
   system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.047%
-  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.953%
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   37.4964%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   62.5036%
 
-  system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode:   152791    100%
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode:   27960    100%
 
 Cache Stats: system.l1_cntrl1.L2cacheMemory
-  system.l1_cntrl1.L2cacheMemory_total_misses: 152791
-  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 152791
+  system.l1_cntrl1.L2cacheMemory_total_misses: 27960
+  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 27960
   system.l1_cntrl1.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.047%
-  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.953%
+  system.l1_cntrl1.L2cacheMemory_request_type_LD:   37.4964%
+  system.l1_cntrl1.L2cacheMemory_request_type_ST:   62.5036%
 
-  system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode:   152791    100%
+  system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode:   27960    100%
 
 Cache Stats: system.l1_cntrl2.L1IcacheMemory
   system.l1_cntrl2.L1IcacheMemory_total_misses: 0
@@ -726,28 +664,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl2.L1DcacheMemory
-  system.l1_cntrl2.L1DcacheMemory_total_misses: 152865
-  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 152865
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 28157
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 28157
   system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.8723%
-  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.1277%
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   37.5608%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   62.4392%
 
-  system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode:   152865    100%
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode:   28157    100%
 
 Cache Stats: system.l1_cntrl2.L2cacheMemory
-  system.l1_cntrl2.L2cacheMemory_total_misses: 152865
-  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 152865
+  system.l1_cntrl2.L2cacheMemory_total_misses: 28157
+  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 28157
   system.l1_cntrl2.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.L2cacheMemory_request_type_LD:   64.8723%
-  system.l1_cntrl2.L2cacheMemory_request_type_ST:   35.1277%
+  system.l1_cntrl2.L2cacheMemory_request_type_LD:   37.5608%
+  system.l1_cntrl2.L2cacheMemory_request_type_ST:   62.4392%
 
-  system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode:   152865    100%
+  system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode:   28157    100%
 
 Cache Stats: system.l1_cntrl3.L1IcacheMemory
   system.l1_cntrl3.L1IcacheMemory_total_misses: 0
@@ -758,28 +696,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl3.L1DcacheMemory
-  system.l1_cntrl3.L1DcacheMemory_total_misses: 152865
-  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 152865
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 27975
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 27975
   system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   65.0522%
-  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   34.9478%
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   37.3798%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   62.6202%
 
-  system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode:   152865    100%
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode:   27975    100%
 
 Cache Stats: system.l1_cntrl3.L2cacheMemory
-  system.l1_cntrl3.L2cacheMemory_total_misses: 152865
-  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 152865
+  system.l1_cntrl3.L2cacheMemory_total_misses: 27975
+  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 27975
   system.l1_cntrl3.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.L2cacheMemory_request_type_LD:   65.0522%
-  system.l1_cntrl3.L2cacheMemory_request_type_ST:   34.9478%
+  system.l1_cntrl3.L2cacheMemory_request_type_LD:   37.3798%
+  system.l1_cntrl3.L2cacheMemory_request_type_ST:   62.6202%
 
-  system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode:   152865    100%
+  system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode:   27975    100%
 
 Cache Stats: system.l1_cntrl4.L1IcacheMemory
   system.l1_cntrl4.L1IcacheMemory_total_misses: 0
@@ -790,28 +728,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl4.L1DcacheMemory
-  system.l1_cntrl4.L1DcacheMemory_total_misses: 153182
-  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 153182
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 28045
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 28045
   system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.9371%
-  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.0629%
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   37.4398%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   62.5602%
 
-  system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode:   153182    100%
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode:   28045    100%
 
 Cache Stats: system.l1_cntrl4.L2cacheMemory
-  system.l1_cntrl4.L2cacheMemory_total_misses: 153182
-  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 153182
+  system.l1_cntrl4.L2cacheMemory_total_misses: 28045
+  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 28045
   system.l1_cntrl4.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.L2cacheMemory_request_type_LD:   64.9371%
-  system.l1_cntrl4.L2cacheMemory_request_type_ST:   35.0629%
+  system.l1_cntrl4.L2cacheMemory_request_type_LD:   37.4398%
+  system.l1_cntrl4.L2cacheMemory_request_type_ST:   62.5602%
 
-  system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode:   153182    100%
+  system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode:   28045    100%
 
 Cache Stats: system.l1_cntrl5.L1IcacheMemory
   system.l1_cntrl5.L1IcacheMemory_total_misses: 0
@@ -822,28 +760,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl5.L1DcacheMemory
-  system.l1_cntrl5.L1DcacheMemory_total_misses: 153033
-  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 153033
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 27996
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 27996
   system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.2088%
-  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.7912%
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   37.4589%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   62.5411%
 
-  system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode:   153033    100%
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode:   27996    100%
 
 Cache Stats: system.l1_cntrl5.L2cacheMemory
-  system.l1_cntrl5.L2cacheMemory_total_misses: 153033
-  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 153033
+  system.l1_cntrl5.L2cacheMemory_total_misses: 27996
+  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 27996
   system.l1_cntrl5.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.L2cacheMemory_request_type_LD:   65.2088%
-  system.l1_cntrl5.L2cacheMemory_request_type_ST:   34.7912%
+  system.l1_cntrl5.L2cacheMemory_request_type_LD:   37.4589%
+  system.l1_cntrl5.L2cacheMemory_request_type_ST:   62.5411%
 
-  system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode:   153033    100%
+  system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode:   27996    100%
 
 Cache Stats: system.l1_cntrl6.L1IcacheMemory
   system.l1_cntrl6.L1IcacheMemory_total_misses: 0
@@ -854,28 +792,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl6.L1DcacheMemory
-  system.l1_cntrl6.L1DcacheMemory_total_misses: 153339
-  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 153339
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 28036
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 28036
   system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   65.2345%
-  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   34.7655%
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   37.5268%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   62.4732%
 
-  system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode:   153339    100%
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode:   28036    100%
 
 Cache Stats: system.l1_cntrl6.L2cacheMemory
-  system.l1_cntrl6.L2cacheMemory_total_misses: 153339
-  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 153339
+  system.l1_cntrl6.L2cacheMemory_total_misses: 28036
+  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 28036
   system.l1_cntrl6.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.L2cacheMemory_request_type_LD:   65.2345%
-  system.l1_cntrl6.L2cacheMemory_request_type_ST:   34.7655%
+  system.l1_cntrl6.L2cacheMemory_request_type_LD:   37.5268%
+  system.l1_cntrl6.L2cacheMemory_request_type_ST:   62.4732%
 
-  system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode:   153339    100%
+  system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode:   28036    100%
 
 Cache Stats: system.l1_cntrl7.L1IcacheMemory
   system.l1_cntrl7.L1IcacheMemory_total_misses: 0
@@ -886,28 +824,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory
 
 
 Cache Stats: system.l1_cntrl7.L1DcacheMemory
-  system.l1_cntrl7.L1DcacheMemory_total_misses: 152687
-  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 152687
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 28038
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 28038
   system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.8994%
-  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.1006%
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   37.2887%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   62.7113%
 
-  system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode:   152687    100%
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode:   28038    100%
 
 Cache Stats: system.l1_cntrl7.L2cacheMemory
-  system.l1_cntrl7.L2cacheMemory_total_misses: 152687
-  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 152687
+  system.l1_cntrl7.L2cacheMemory_total_misses: 28038
+  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 28038
   system.l1_cntrl7.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.8994%
-  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.1006%
+  system.l1_cntrl7.L2cacheMemory_request_type_LD:   37.2887%
+  system.l1_cntrl7.L2cacheMemory_request_type_ST:   62.7113%
 
-  system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode:   152687    100%
+  system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode:   28038    100%
 
 Cache Stats: system.dir_cntrl0.probeFilter
   system.dir_cntrl0.probeFilter_total_misses: 0
@@ -918,42 +856,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
 
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1605206
-  memory_reads: 1182555
-  memory_writes: 422632
-  memory_refreshes: 79291
-  memory_total_request_delays: 102402684
-  memory_delays_per_request: 63.7941
-  memory_delays_in_input_queue: 1299437
-  memory_delays_behind_head_of_bank_queue: 41856577
-  memory_delays_stalled_at_head_of_bank_queue: 59246670
-  memory_stalls_for_bank_busy: 8937619
+  memory_total_requests: 2
+  memory_reads: 2
+  memory_writes: 0
+  memory_refreshes: 22
+  memory_total_request_delays: 31
+  memory_delays_per_request: 15.5
+  memory_delays_in_input_queue: 1
+  memory_delays_behind_head_of_bank_queue: 10
+  memory_delays_stalled_at_head_of_bank_queue: 20
+  memory_stalls_for_bank_busy: 20
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 15070759
-  memory_stalls_for_arbitration: 12094661
-  memory_stalls_for_bus: 16398548
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 0
+  memory_stalls_for_bus: 0
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 4057082
-  memory_stalls_for_read_read_turnaround: 2688001
-  accesses_per_bank: 50458  50374  50220  50357  50425  50704  50742  49982  50496  50326  50505  50322  50256  50180  50160  49801  50242  49867  50410  49981  49983  50012  49966  49937  50095  49827  49802  49652  50037  49876  50349  49862  
+  memory_stalls_for_read_write_turnaround: 0
+  memory_stalls_for_read_read_turnaround: 0
+  accesses_per_bank: 2  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  
 
  --- Directory ---
  - Event Counts -
-GETX [434154 ] 434154
-GETS [806552 ] 806552
-PUT [1152892 ] 1152892
-Unblock [18 ] 18
-UnblockS [46460 ] 46460
-UnblockM [1175952 ] 1175952
-Writeback_Clean [15933 ] 15933
-Writeback_Dirty [173 ] 173
-Writeback_Exclusive_Clean [713909 ] 713909
-Writeback_Exclusive_Dirty [422463 ] 422463
+GETX [829725 ] 829725
+GETS [354236 ] 354236
+PUT [0 ] 0
+Unblock [0 ] 0
+UnblockS [84130 ] 84130
+UnblockM [140228 ] 140228
+Writeback_Clean [0 ] 0
+Writeback_Dirty [0 ] 0
+Writeback_Exclusive_Clean [0 ] 0
+Writeback_Exclusive_Dirty [0 ] 0
 Pf_Replacement [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [1182550 ] 1182550
-Memory_Ack [422632 ] 422632
+Memory_Data [2 ] 2
+Memory_Ack [0 ] 0
 Ack [0 ] 0
 Shared_Ack [0 ] 0
 Shared_Data [0 ] 0
@@ -962,19 +900,19 @@ Exclusive_Data [0 ] 0
 All_acks_and_shared_data [0 ] 0
 All_acks_and_owner_data [0 ] 0
 All_acks_and_data_no_sharers [0 ] 0
-All_Unblocks [69 ] 69
+All_Unblocks [17206 ] 17206
 
  - Transitions -
-NX  GETX [124 ] 124
-NX  GETS [185 ] 185
-NX  PUT [16124 ] 16124
+NX  GETX [17206 ] 17206
+NX  GETS [0 ] 0
+NX  PUT [0 ] 0
 NX  Pf_Replacement [0 ] 0
 NX  DMA_READ [0 ] 0
 NX  DMA_WRITE [0 ] 0
 
-NO  GETX [14020 ] 14020
-NO  GETS [25465 ] 25465
-NO  PUT [1136372 ] 1136372
+NO  GETX [123021 ] 123021
+NO  GETS [1 ] 1
+NO  PUT [0 ] 0
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
@@ -986,15 +924,15 @@ S  Pf_Replacement [0 ] 0
 S  DMA_READ [0 ] 0
 S  DMA_WRITE [0 ] 0
 
-O  GETX [16045 ] 16045
-O  GETS [30010 ] 30010
+O  GETX [0 ] 0
+O  GETS [0 ] 0
 O  PUT [0 ] 0
 O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 
-E  GETX [397555 ] 397555
-E  GETS [738960 ] 738960
+E  GETX [0 ] 0
+E  GETS [2 ] 2
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
@@ -1029,69 +967,66 @@ NO_R  Data [0 ] 0
 NO_R  Exclusive_Data [0 ] 0
 NO_R  All_acks_and_data_no_sharers [0 ] 0
 
-NO_B  GETX [44 ] 44
-NO_B  GETS [69 ] 69
-NO_B  PUT [395 ] 395
-NO_B  UnblockS [16331 ] 16331
-NO_B  UnblockM [1175890 ] 1175890
+NO_B  GETX [123022 ] 123022
+NO_B  GETS [17206 ] 17206
+NO_B  PUT [0 ] 0
+NO_B  UnblockS [0 ] 0
+NO_B  UnblockM [2 ] 2
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
 
-NO_B_X  GETX [0 ] 0
-NO_B_X  GETS [0 ] 0
+NO_B_X  GETX [468040 ] 468040
+NO_B_X  GETS [270091 ] 270091
 NO_B_X  PUT [0 ] 0
-NO_B_X  UnblockS [16 ] 16
-NO_B_X  UnblockM [28 ] 28
+NO_B_X  UnblockS [0 ] 0
+NO_B_X  UnblockM [123020 ] 123020
 NO_B_X  Pf_Replacement [0 ] 0
-NO_B_X  DMA_READ [0 ] 0
-NO_B_X  DMA_WRITE [0 ] 0
 
-NO_B_S  GETX [0 ] 0
-NO_B_S  GETS [0 ] 0
+NO_B_S  GETX [36312 ] 36312
+NO_B_S  GETS [66924 ] 66924
 NO_B_S  PUT [0 ] 0
-NO_B_S  UnblockS [35 ] 35
-NO_B_S  UnblockM [34 ] 34
+NO_B_S  UnblockS [0 ] 0
+NO_B_S  UnblockM [17206 ] 17206
 NO_B_S  Pf_Replacement [0 ] 0
 NO_B_S  DMA_READ [0 ] 0
 NO_B_S  DMA_WRITE [0 ] 0
 
-NO_B_S_W  GETX [0 ] 0
+NO_B_S_W  GETX [62122 ] 62122
 NO_B_S_W  GETS [0 ] 0
-NO_B_S_W  PUT [1 ] 1
-NO_B_S_W  UnblockS [69 ] 69
+NO_B_S_W  PUT [0 ] 0
+NO_B_S_W  UnblockS [84130 ] 84130
 NO_B_S_W  Pf_Replacement [0 ] 0
 NO_B_S_W  DMA_READ [0 ] 0
 NO_B_S_W  DMA_WRITE [0 ] 0
-NO_B_S_W  All_Unblocks [69 ] 69
+NO_B_S_W  All_Unblocks [17206 ] 17206
 
 O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
-O_B  UnblockS [30009 ] 30009
-O_B  UnblockM [0 ] 0
+O_B  UnblockS [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
 
-NO_B_W  GETX [3976 ] 3976
-NO_B_W  GETS [7420 ] 7420
+NO_B_W  GETX [2 ] 2
+NO_B_W  GETS [12 ] 12
 NO_B_W  PUT [0 ] 0
 NO_B_W  UnblockS [0 ] 0
 NO_B_W  UnblockM [0 ] 0
 NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
-NO_B_W  Memory_Data [1152540 ] 1152540
+NO_B_W  Memory_Data [2 ] 2
 
-O_B_W  GETX [103 ] 103
-O_B_W  GETS [194 ] 194
+O_B_W  GETX [0 ] 0
+O_B_W  GETS [0 ] 0
 O_B_W  PUT [0 ] 0
 O_B_W  UnblockS [0 ] 0
 O_B_W  Pf_Replacement [0 ] 0
 O_B_W  DMA_READ [0 ] 0
 O_B_W  DMA_WRITE [0 ] 0
-O_B_W  Memory_Data [30010 ] 30010
+O_B_W  Memory_Data [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
@@ -1192,14 +1127,14 @@ O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
 
-WB  GETX [171 ] 171
-WB  GETS [322 ] 322
+WB  GETX [0 ] 0
+WB  GETS [0 ] 0
 WB  PUT [0 ] 0
-WB  Unblock [18 ] 18
-WB  Writeback_Clean [15933 ] 15933
-WB  Writeback_Dirty [173 ] 173
-WB  Writeback_Exclusive_Clean [713909 ] 713909
-WB  Writeback_Exclusive_Dirty [422463 ] 422463
+WB  Unblock [0 ] 0
+WB  Writeback_Clean [0 ] 0
+WB  Writeback_Dirty [0 ] 0
+WB  Writeback_Exclusive_Clean [0 ] 0
+WB  Writeback_Exclusive_Dirty [0 ] 0
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
@@ -1210,10 +1145,10 @@ WB_O_W  PUT [0 ] 0
 WB_O_W  Pf_Replacement [0 ] 0
 WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
-WB_O_W  Memory_Ack [173 ] 173
+WB_O_W  Memory_Ack [0 ] 0
 
-WB_E_W  GETX [2116 ] 2116
-WB_E_W  GETS [3927 ] 3927
+WB_E_W  GETX [0 ] 0
+WB_E_W  GETS [0 ] 0
 WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index 894fb5f71..1aa1be599 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -1,74 +1,74 @@
-system.cpu5: completed 10000 read accesses @3773579
-system.cpu6: completed 10000 read accesses @3800919
-system.cpu4: completed 10000 read accesses @3806319
-system.cpu7: completed 10000 read accesses @3815919
-system.cpu3: completed 10000 read accesses @3847469
-system.cpu1: completed 10000 read accesses @3858049
-system.cpu2: completed 10000 read accesses @3865769
-system.cpu0: completed 10000 read accesses @3909119
-system.cpu6: completed 20000 read accesses @7545009
-system.cpu5: completed 20000 read accesses @7578569
-system.cpu3: completed 20000 read accesses @7650419
-system.cpu4: completed 20000 read accesses @7653039
-system.cpu7: completed 20000 read accesses @7660349
-system.cpu1: completed 20000 read accesses @7666509
-system.cpu2: completed 20000 read accesses @7676969
-system.cpu0: completed 20000 read accesses @7778949
-system.cpu5: completed 30000 read accesses @11400279
-system.cpu6: completed 30000 read accesses @11403319
-system.cpu3: completed 30000 read accesses @11463329
-system.cpu4: completed 30000 read accesses @11476649
-system.cpu1: completed 30000 read accesses @11482109
-system.cpu2: completed 30000 read accesses @11515599
-system.cpu7: completed 30000 read accesses @11523379
-system.cpu0: completed 30000 read accesses @11644619
-system.cpu6: completed 40000 read accesses @15163509
-system.cpu5: completed 40000 read accesses @15247859
-system.cpu1: completed 40000 read accesses @15285159
-system.cpu4: completed 40000 read accesses @15331509
-system.cpu2: completed 40000 read accesses @15338199
-system.cpu3: completed 40000 read accesses @15352259
-system.cpu7: completed 40000 read accesses @15377169
-system.cpu0: completed 40000 read accesses @15448399
-system.cpu6: completed 50000 read accesses @18963379
-system.cpu5: completed 50000 read accesses @19066919
-system.cpu1: completed 50000 read accesses @19138729
-system.cpu3: completed 50000 read accesses @19175839
-system.cpu4: completed 50000 read accesses @19193269
-system.cpu2: completed 50000 read accesses @19229269
-system.cpu0: completed 50000 read accesses @19286699
-system.cpu7: completed 50000 read accesses @19288339
-system.cpu6: completed 60000 read accesses @22830379
-system.cpu5: completed 60000 read accesses @22876169
-system.cpu1: completed 60000 read accesses @22895139
-system.cpu4: completed 60000 read accesses @23008339
-system.cpu3: completed 60000 read accesses @23024099
-system.cpu2: completed 60000 read accesses @23042669
-system.cpu7: completed 60000 read accesses @23113989
-system.cpu0: completed 60000 read accesses @23166249
-system.cpu6: completed 70000 read accesses @26656369
-system.cpu5: completed 70000 read accesses @26704159
-system.cpu1: completed 70000 read accesses @26732409
-system.cpu4: completed 70000 read accesses @26782879
-system.cpu3: completed 70000 read accesses @26845059
-system.cpu2: completed 70000 read accesses @26884599
-system.cpu7: completed 70000 read accesses @26960819
-system.cpu0: completed 70000 read accesses @26960869
-system.cpu6: completed 80000 read accesses @30376569
-system.cpu5: completed 80000 read accesses @30517259
-system.cpu4: completed 80000 read accesses @30578729
-system.cpu1: completed 80000 read accesses @30606099
-system.cpu3: completed 80000 read accesses @30658599
-system.cpu2: completed 80000 read accesses @30711719
-system.cpu0: completed 80000 read accesses @30713219
-system.cpu7: completed 80000 read accesses @30760569
-system.cpu6: completed 90000 read accesses @34228379
-system.cpu5: completed 90000 read accesses @34328029
-system.cpu4: completed 90000 read accesses @34428059
-system.cpu1: completed 90000 read accesses @34475699
-system.cpu3: completed 90000 read accesses @34504539
-system.cpu0: completed 90000 read accesses @34548119
-system.cpu7: completed 90000 read accesses @34567549
-system.cpu2: completed 90000 read accesses @34597039
-system.cpu6: completed 100000 read accesses @38059429
+system.cpu2: completed 10000 read accesses @332309
+system.cpu0: completed 10000 read accesses @332762
+system.cpu3: completed 10000 read accesses @333275
+system.cpu7: completed 10000 read accesses @334660
+system.cpu4: completed 10000 read accesses @336400
+system.cpu6: completed 10000 read accesses @336827
+system.cpu1: completed 10000 read accesses @336833
+system.cpu5: completed 10000 read accesses @339345
+system.cpu3: completed 20000 read accesses @659139
+system.cpu0: completed 20000 read accesses @662762
+system.cpu2: completed 20000 read accesses @662918
+system.cpu4: completed 20000 read accesses @663822
+system.cpu6: completed 20000 read accesses @664214
+system.cpu7: completed 20000 read accesses @673557
+system.cpu1: completed 20000 read accesses @673720
+system.cpu5: completed 20000 read accesses @675222
+system.cpu3: completed 30000 read accesses @990404
+system.cpu6: completed 30000 read accesses @991868
+system.cpu0: completed 30000 read accesses @993980
+system.cpu2: completed 30000 read accesses @994621
+system.cpu4: completed 30000 read accesses @995936
+system.cpu5: completed 30000 read accesses @1005609
+system.cpu1: completed 30000 read accesses @1008145
+system.cpu7: completed 30000 read accesses @1008840
+system.cpu6: completed 40000 read accesses @1322251
+system.cpu0: completed 40000 read accesses @1324139
+system.cpu3: completed 40000 read accesses @1324341
+system.cpu2: completed 40000 read accesses @1325019
+system.cpu4: completed 40000 read accesses @1328462
+system.cpu5: completed 40000 read accesses @1335869
+system.cpu1: completed 40000 read accesses @1336407
+system.cpu7: completed 40000 read accesses @1342910
+system.cpu6: completed 50000 read accesses @1654106
+system.cpu0: completed 50000 read accesses @1654925
+system.cpu3: completed 50000 read accesses @1657897
+system.cpu2: completed 50000 read accesses @1658205
+system.cpu1: completed 50000 read accesses @1668347
+system.cpu5: completed 50000 read accesses @1668465
+system.cpu4: completed 50000 read accesses @1670315
+system.cpu7: completed 50000 read accesses @1681232
+system.cpu6: completed 60000 read accesses @1984633
+system.cpu0: completed 60000 read accesses @1986549
+system.cpu2: completed 60000 read accesses @1989981
+system.cpu3: completed 60000 read accesses @1993690
+system.cpu1: completed 60000 read accesses @2001694
+system.cpu4: completed 60000 read accesses @2002313
+system.cpu5: completed 60000 read accesses @2005561
+system.cpu7: completed 60000 read accesses @2014675
+system.cpu6: completed 70000 read accesses @2317222
+system.cpu0: completed 70000 read accesses @2318277
+system.cpu2: completed 70000 read accesses @2322048
+system.cpu3: completed 70000 read accesses @2324750
+system.cpu4: completed 70000 read accesses @2332151
+system.cpu1: completed 70000 read accesses @2332386
+system.cpu5: completed 70000 read accesses @2332911
+system.cpu7: completed 70000 read accesses @2343337
+system.cpu0: completed 80000 read accesses @2646207
+system.cpu6: completed 80000 read accesses @2646561
+system.cpu3: completed 80000 read accesses @2652685
+system.cpu2: completed 80000 read accesses @2655532
+system.cpu5: completed 80000 read accesses @2662477
+system.cpu4: completed 80000 read accesses @2665813
+system.cpu7: completed 80000 read accesses @2668350
+system.cpu1: completed 80000 read accesses @2668666
+system.cpu6: completed 90000 read accesses @2976982
+system.cpu0: completed 90000 read accesses @2982010
+system.cpu2: completed 90000 read accesses @2983845
+system.cpu3: completed 90000 read accesses @2993125
+system.cpu5: completed 90000 read accesses @2995492
+system.cpu4: completed 90000 read accesses @2998220
+system.cpu7: completed 90000 read accesses @3003787
+system.cpu1: completed 90000 read accesses @3004322
+system.cpu6: completed 100000 read accesses @3305503
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index c6863d275..9fe27411d 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:21
-M5 executing on SC2B0617
+M5 compiled Aug 20 2010 12:17:38
+M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
+M5 started Aug 20 2010 12:17:55
+M5 executing on SC2B0629
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 38059429 because maximum number of loads reached
+Exiting @ tick 3305503 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 17e12e395..d441ad68e 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 345460                       # Number of bytes of host memory used
-host_seconds                                   245.24                       # Real time elapsed on the host
-host_tick_rate                                 155190                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 341640                       # Number of bytes of host memory used
+host_seconds                                    37.52                       # Real time elapsed on the host
+host_tick_rate                                  88100                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.038059                       # Number of seconds simulated
-sim_ticks                                    38059429                       # Number of ticks simulated
+sim_seconds                                  0.003306                       # Number of seconds simulated
+sim_ticks                                     3305503                       # Number of ticks simulated
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99072                       # number of read accesses completed
-system.cpu0.num_writes                          53787                       # number of write accesses completed
+system.cpu0.num_reads                           99692                       # number of read accesses completed
+system.cpu0.num_writes                          53673                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99360                       # number of read accesses completed
-system.cpu1.num_writes                          53383                       # number of write accesses completed
+system.cpu1.num_reads                           99062                       # number of read accesses completed
+system.cpu1.num_writes                          53374                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99132                       # number of read accesses completed
-system.cpu2.num_writes                          53677                       # number of write accesses completed
+system.cpu2.num_reads                           99665                       # number of read accesses completed
+system.cpu2.num_writes                          53906                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99402                       # number of read accesses completed
-system.cpu3.num_writes                          53396                       # number of write accesses completed
+system.cpu3.num_reads                           99457                       # number of read accesses completed
+system.cpu3.num_writes                          53389                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99445                       # number of read accesses completed
-system.cpu4.num_writes                          53699                       # number of write accesses completed
+system.cpu4.num_reads                           99209                       # number of read accesses completed
+system.cpu4.num_writes                          53779                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99752                       # number of read accesses completed
-system.cpu5.num_writes                          53216                       # number of write accesses completed
+system.cpu5.num_reads                           99375                       # number of read accesses completed
+system.cpu5.num_writes                          53528                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
 system.cpu6.num_reads                          100000                       # number of read accesses completed
-system.cpu6.num_writes                          53289                       # number of write accesses completed
+system.cpu6.num_writes                          53388                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99050                       # number of read accesses completed
-system.cpu7.num_writes                          53576                       # number of write accesses completed
+system.cpu7.num_reads                           99219                       # number of read accesses completed
+system.cpu7.num_writes                          53946                       # number of write accesses completed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index 499a69fa0..370a5746b 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
@@ -377,9 +368,10 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer
+children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -391,7 +383,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports0]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.cacheMemory
@@ -404,7 +395,6 @@ port=system.cpu0.test
 
 [system.ruby.cpu_ruby_ports1]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl1.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl1.cacheMemory
@@ -417,7 +407,6 @@ port=system.cpu1.test
 
 [system.ruby.cpu_ruby_ports2]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl2.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl2.cacheMemory
@@ -430,7 +419,6 @@ port=system.cpu2.test
 
 [system.ruby.cpu_ruby_ports3]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl3.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl3.cacheMemory
@@ -443,7 +431,6 @@ port=system.cpu3.test
 
 [system.ruby.cpu_ruby_ports4]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl4.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl4.cacheMemory
@@ -456,7 +443,6 @@ port=system.cpu4.test
 
 [system.ruby.cpu_ruby_ports5]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl5.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl5.cacheMemory
@@ -469,7 +455,6 @@ port=system.cpu5.test
 
 [system.ruby.cpu_ruby_ports6]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl6.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl6.cacheMemory
@@ -482,7 +467,6 @@ port=system.cpu6.test
 
 [system.ruby.cpu_ruby_ports7]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl7.cacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl7.cacheMemory
@@ -493,6 +477,14 @@ version=7
 physMemPort=system.physmem.port[7]
 port=system.cpu7.test
 
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index 706957847..f3ddd5354 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -34,29 +34,29 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:44:25
+Real time: Aug/20/2010 13:39:31
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 87
-Elapsed_time_in_minutes: 1.45
-Elapsed_time_in_hours: 0.0241667
-Elapsed_time_in_days: 0.00100694
+Elapsed_time_in_seconds: 69
+Elapsed_time_in_minutes: 1.15
+Elapsed_time_in_hours: 0.0191667
+Elapsed_time_in_days: 0.000798611
 
-Virtual_time_in_seconds: 87.74
-Virtual_time_in_minutes: 1.46233
-Virtual_time_in_hours:   0.0243722
-Virtual_time_in_days:    0.00101551
+Virtual_time_in_seconds: 68.75
+Virtual_time_in_minutes: 1.14583
+Virtual_time_in_hours:   0.0190972
+Virtual_time_in_days:    0.000795718
 
-Ruby_current_time: 57251340
+Ruby_current_time: 11059012
 Ruby_start_time: 0
-Ruby_cycles: 57251340
+Ruby_cycles: 11059012
 
-mbytes_resident: 35.5586
-mbytes_total: 337.539
-resident_ratio: 0.105358
+mbytes_resident: 32.25
+mbytes_total: 333.105
+resident_ratio: 0.0968279
 
-ruby_cycles_executed: [ 57251341 57251341 57251341 57251341 57251341 57251341 57251341 57251341 ]
+ruby_cycles_executed: [ 11059013 11059013 11059013 11059013 11059013 11059013 11059013 11059013 ]
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
@@ -66,29 +66,31 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1227441 average: 15.9992 | standard deviation: 0.0898992 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1227321 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1228772 average: 1.9375 | standard deviation: 0.242071 | 0 76804 1151968 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 128 max: 16170 count: 1227313 average: 5970.6 | standard deviation: 6226.1 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 28 67 117 196 325 493 850 1372 2115 2889 3474 5267 7331 8923 10961 13117 17439 19106 22197 27797 27598 30754 34950 40376 40150 37193 44218 47799 45035 44430 44397 47887 43214 42194 45299 37620 36866 36136 37155 31716 26415 28478 27184 22299 20319 18521 18170 14600 13557 13481 10233 9188 8568 8384 6564 5202 5341 4736 3697 3355 2785 2534 2139 1813 1715 1305 1213 1037 977 761 540 516 459 368 287 221 221 156 133 132 101 86 57 64 45 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 128 max: 16170 count: 797864 average: 5970.96 | standard deviation: 5567.96 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 23 42 79 125 214 331 544 877 1397 1863 2231 3466 4741 5801 7112 8516 11461 12380 14439 17894 17955 19944 22577 26201 26233 24153 28751 31184 29257 28993 28655 31123 28291 27538 29428 24371 23978 23499 24308 20557 17139 18652 17606 14368 13155 11966 11765 9607 8837 8844 6659 5936 5560 5504 4210 3414 3473 3145 2395 2145 1816 1622 1380 1171 1141 849 772 673 638 482 346 347 309 240 185 140 136 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 128 max: 15290 count: 429449 average: 5969.93 | standard deviation: 1423.42 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 38 71 111 162 306 495 718 1026 1243 1801 2590 3122 3849 4601 5978 6726 7758 9903 9643 10810 12373 14175 13917 13040 15467 16615 15778 15437 15742 16764 14923 14656 15871 13249 12888 12637 12847 11159 9276 9826 9578 7931 7164 6555 6405 4993 4720 4637 3574 3252 3008 2880 2354 1788 1868 1591 1302 1210 969 912 759 642 574 456 441 364 339 279 194 169 150 128 102 81 85 61 49 47 36 27 17 22 14 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 128 max: 16170 count: 1210799 average: 5976.91 | standard deviation: 6306.43 | 0 5 5 5 5 5 5 5 3 0 6 5 4 9 25 62 110 189 305 465 806 1312 2035 2792 3339 5094 7111 8663 10701 12775 17023 18729 21808 27255 27055 30221 34375 39759 39511 36575 43613 47122 44479 43852 43802 47301 42687 41791 44754 37147 36463 35788 36800 31395 26170 28198 26928 22083 20141 18352 18010 14477 13445 13354 10138 9095 8497 8327 6511 5159 5306 4695 3671 3321 2764 2511 2121 1803 1701 1296 1209 1028 975 758 537 511 458 365 284 218 218 156 133 132 101 86 57 62 43 25 28 41 28 25 18 17 8 7 9 7 4 5 8 3 2 0 0 1 0 2 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache_wCC: [binsize: 64 max: 12585 count: 16514 average: 5507.92 | standard deviation: 1405.44 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 3 4 3 4 10 10 16 12 19 25 26 34 35 45 45 52 71 64 84 89 98 122 124 136 137 123 165 177 197 219 187 190 187 202 274 268 276 267 243 290 258 317 297 320 337 302 325 293 290 315 320 357 281 275 296 282 331 264 270 316 252 275 203 200 297 248 265 208 206 197 170 178 187 168 186 135 131 114 140 140 129 127 114 102 100 78 86 83 72 88 56 67 54 58 72 55 56 39 45 48 44 27 26 31 22 31 24 19 19 16 27 14 14 12 24 10 13 8 8 15 10 8 4 6 9 5 3 6 2 2 2 7 1 1 0 3 1 2 3 2 0 1 2 1 2 1 2 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ]
-miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_wCC_Times: 16514
-miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 8 average:     0 | standard deviation: 0 | 8 ]
-miss_latency_dir_first_response_to_completion: [binsize: 4 max: 569 count: 8 average: 330.25 | standard deviation: 178.281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-imcomplete_dir_Times: 1210791
-miss_latency_LD_Directory: [binsize: 128 max: 16170 count: 787157 average: 5977.4 | standard deviation: 5638.59 | 0 4 4 4 4 4 4 4 1 0 1 4 4 6 20 37 73 120 198 310 520 832 1338 1800 2148 3355 4608 5614 6946 8289 11207 12142 14179 17561 17587 19588 22210 25807 25824 23747 28369 30735 28910 28603 28263 30729 27952 27268 29067 24058 23732 23284 24091 20357 16975 18458 17439 14222 13051 11864 11662 9526 8758 8751 6596 5876 5513 5476 4177 3395 3452 3117 2376 2125 1802 1609 1370 1164 1131 844 770 668 638 481 345 344 308 238 182 138 133 95 84 85 65 59 40 42 31 15 21 23 20 16 13 11 6 3 6 5 3 3 6 3 1 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11604 count: 10707 average: 5497.29 | standard deviation: 1398.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 3 2 2 4 2 3 10 6 11 10 12 12 21 24 26 33 30 33 43 40 49 62 62 71 90 97 85 81 109 118 117 137 123 115 124 136 167 166 175 193 160 196 158 209 187 207 224 185 212 194 180 202 215 234 180 167 201 189 218 174 184 210 163 176 141 129 197 164 169 144 128 118 105 110 104 113 120 80 90 74 101 93 83 84 71 75 61 43 49 53 49 54 38 43 42 37 49 44 36 27 27 33 26 21 9 19 11 22 10 9 12 9 20 8 11 8 14 6 9 5 6 7 5 5 4 3 6 4 3 2 1 1 1 4 0 0 0 1 0 1 2 1 0 1 2 0 2 1 2 0 1 2 ]
-miss_latency_ST_Directory: [binsize: 128 max: 15290 count: 423642 average:  5976 | standard deviation: 1422.53 | 0 1 1 1 1 1 1 1 2 0 5 1 0 3 5 25 37 69 107 155 286 480 697 992 1191 1739 2503 3049 3755 4486 5816 6587 7629 9694 9468 10633 12165 13952 13687 12828 15244 16387 15569 15249 15539 16572 14735 14523 15687 13089 12731 12504 12709 11038 9195 9740 9489 7861 7090 6488 6348 4951 4687 4603 3542 3219 2984 2851 2334 1764 1854 1578 1295 1196 962 902 751 639 570 452 439 360 337 277 192 167 150 127 102 80 85 61 49 47 36 27 17 20 12 10 7 18 8 9 5 6 2 4 3 2 1 2 2 0 1 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 12585 count: 5807 average: 5527.52 | standard deviation: 1418.56 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 4 5 2 7 13 5 10 9 12 15 19 28 24 35 27 36 51 34 39 52 42 56 59 80 82 64 75 63 66 107 102 101 74 83 94 100 108 110 113 113 117 113 99 110 113 105 123 101 108 95 93 113 90 86 106 89 99 62 71 100 84 96 64 78 79 65 68 83 55 66 55 41 40 39 47 46 43 43 27 39 35 37 30 23 34 18 24 12 21 23 11 20 12 18 15 18 6 17 12 11 9 14 10 7 7 7 6 3 4 10 4 4 3 2 8 5 3 0 3 3 1 0 4 1 1 1 3 1 1 0 2 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 ]
+miss_latency: [binsize: 4 max: 548 count: 1228757 average: 141.941 | standard deviation: 1.79768 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 4 max: 548 count: 798474 average: 141.942 | standard deviation: 1.87927 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 4 max: 459 count: 430283 average: 141.94 | standard deviation: 1.63553 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 14 average:     3 | standard deviation: 0 | 0 0 0 14 ]
+miss_latency_Directory: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache_wCC: [binsize: 4 max: 548 count: 1228741 average: 141.942 | standard deviation: 1.72165 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 272 4811 76194 1147428 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average:     0 | standard deviation: 0 | 6 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 495 count: 6 average: 412.667 | standard deviation: 76.4147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_wCC_Times: 1228735
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average:     0 | standard deviation: 0 | 2 ]
+miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
+miss_latency_LD_Directory: [binsize: 2 max: 359 count: 2 average:   304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 548 count: 798465 average: 141.943 | standard deviation: 1.81358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 174 3144 49367 745750 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 459 count: 430276 average: 141.942 | standard deviation: 1.53653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 98 1667 26827 401678 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -102,11 +104,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.000321739 | standard deviation: 0.0752325 | 2458470 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
+Total_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
+Total_nonPF_delay_cycles: [binsize: 4 max: 151 count: 2457486 average: 47.4696 | standard deviation: 47.4806 | 1228745 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
   virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227313 average:     0 | standard deviation: 0 | 1227313 ]
-  virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 1231202 average: 0.000642462 | standard deviation: 0.106311 | 1231157 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 26 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1228743 average:     0 | standard deviation: 0 | 1228743 ]
+  virtual_network_2_delay_cycles: [binsize: 4 max: 151 count: 1228743 average: 94.9391 | standard deviation: 1.44451 | 2 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 0 7 145 2397 38169 611708 576306 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -118,9 +120,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 2458515 average: 0.00032173
 Resource Usage
 --------------
 page_size: 4096
-user_time: 87
+user_time: 68
 system_time: 0
-page_reclaims: 10421
+page_reclaims: 9322
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -129,326 +131,315 @@ block_outputs: 0
 Network Stats
 -------------
 
-total_msg_count_Control: 3681972 29455776
-total_msg_count_Data: 3644124 262376928
-total_msg_count_Response_Data: 3681939 265099608
-total_msg_count_Writeback_Control: 3693606 29548848
-total_msgs: 14701641 total_bytes: 586481160
+total_msg_count_Control: 3686271 29490168
+total_msg_count_Response_Data: 3686229 265408488
+total_msg_count_Writeback_Control: 3686259 29490072
+total_msgs: 11058759 total_bytes: 324388728
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.083792
-  links_utilized_percent_switch_0_link_0: 0.0334493 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.134135 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.434016
+  links_utilized_percent_switch_0_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.694426 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Control: 153154 1225232 [ 0 0 153154 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Data: 151525 10909800 [ 0 0 151525 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 2111 151992 [ 0 0 0 0 2111 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0839004
-  links_utilized_percent_switch_1_link_0: 0.0334929 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.134308 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.434016
+  links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.694426 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Control: 153355 1226840 [ 0 0 153355 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Data: 151790 10928880 [ 0 0 151790 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 2044 147168 [ 0 0 0 0 2044 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.0839292
-  links_utilized_percent_switch_2_link_0: 0.0334995 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.134359 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.434016
+  links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.694426 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Control: 153381 1227048 [ 0 0 153381 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Data: 151808 10930176 [ 0 0 151808 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 2088 150336 [ 0 0 0 0 2088 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 2
 switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.0839178
-  links_utilized_percent_switch_3_link_0: 0.0335004 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.134335 bw: 160000 base_latency: 1
+links_utilized_percent_switch_3: 0.434016
+  links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.694426 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_3_link_0_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Control: 153389 1227112 [ 0 0 153389 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Data: 151791 10928952 [ 0 0 151791 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Response_Data: 2074 149328 [ 0 0 0 0 2074 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
 
 switch_4_inlinks: 2
 switch_4_outlinks: 2
-links_utilized_percent_switch_4: 0.0841195
-  links_utilized_percent_switch_4_link_0: 0.0335808 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_4_link_1: 0.134658 bw: 160000 base_latency: 1
+links_utilized_percent_switch_4: 0.434014
+  links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_4_link_0_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_0_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Control: 153758 1230064 [ 0 0 153758 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Data: 152172 10956384 [ 0 0 152172 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_4_link_1_Response_Data: 2063 148536 [ 0 0 0 0 2063 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
 
 switch_5_inlinks: 2
 switch_5_outlinks: 2
-links_utilized_percent_switch_5: 0.0840452
-  links_utilized_percent_switch_5_link_0: 0.0335493 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_5_link_1: 0.134541 bw: 160000 base_latency: 1
+links_utilized_percent_switch_5: 0.434016
+  links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 0.694426 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_5_link_0_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_0_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Control: 153613 1228904 [ 0 0 153613 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Data: 152110 10951920 [ 0 0 152110 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_5_link_1_Response_Data: 1992 143424 [ 0 0 0 0 1992 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Control: 153595 1228760 [ 0 0 153595 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
 
 switch_6_inlinks: 2
 switch_6_outlinks: 2
-links_utilized_percent_switch_6: 0.084233
-  links_utilized_percent_switch_6_link_0: 0.0336256 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_6_link_1: 0.13484 bw: 160000 base_latency: 1
+links_utilized_percent_switch_6: 0.434014
+  links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_6_link_0_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_0_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Control: 153962 1231696 [ 0 0 153962 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Data: 152406 10973232 [ 0 0 152406 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_6_link_1_Response_Data: 2038 146736 [ 0 0 0 0 2038 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
 
 switch_7_inlinks: 2
 switch_7_outlinks: 2
-links_utilized_percent_switch_7: 0.0835571
-  links_utilized_percent_switch_7_link_0: 0.033353 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_7_link_1: 0.133761 bw: 160000 base_latency: 1
+links_utilized_percent_switch_7: 0.434013
+  links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_7_link_0_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_0_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Control: 152712 1221696 [ 0 0 152712 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Data: 151106 10879632 [ 0 0 151106 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_7_link_1_Response_Data: 2104 151488 [ 0 0 0 0 2104 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Control: 153594 1228752 [ 0 0 153594 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
 
 switch_8_inlinks: 2
 switch_8_outlinks: 2
-links_utilized_percent_switch_8: 0.662356
-  links_utilized_percent_switch_8_link_0: 0.265489 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_8_link_1: 1.05922 bw: 160000 base_latency: 1
+links_utilized_percent_switch_8: 0.347219
+  links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_8_link_0_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_0_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Response_Data: 1210799 87177528 [ 0 0 0 0 1210799 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_8_link_1_Writeback_Control: 1231202 9849616 [ 0 0 0 1231202 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 1228753 9830024 [ 0 0 0 1228753 0 0 0 0 0 0 ] base_latency: 1
 
 switch_9_inlinks: 9
 switch_9_outlinks: 9
-links_utilized_percent_switch_9: 0.237129
-  links_utilized_percent_switch_9_link_0: 0.133797 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_1: 0.133972 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_2: 0.133998 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_3: 0.134002 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_4: 0.134323 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_5: 0.134197 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_6: 0.134503 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_7: 0.133412 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_9_link_8: 1.06196 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_9_link_0_Response_Data: 153153 11027016 [ 0 0 0 0 153153 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_0_Writeback_Control: 153635 1229080 [ 0 0 0 153635 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Response_Data: 153353 11041416 [ 0 0 0 0 153353 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_1_Writeback_Control: 153833 1230664 [ 0 0 0 153833 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Response_Data: 153380 11043360 [ 0 0 0 0 153380 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_2_Writeback_Control: 153895 1231160 [ 0 0 0 153895 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Response_Data: 153388 11043936 [ 0 0 0 0 153388 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_3_Writeback_Control: 153864 1230912 [ 0 0 0 153864 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Response_Data: 153756 11070432 [ 0 0 0 0 153756 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_4_Writeback_Control: 154232 1233856 [ 0 0 0 154232 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Response_Data: 153611 11059992 [ 0 0 0 0 153611 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_5_Writeback_Control: 154097 1232776 [ 0 0 0 154097 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Response_Data: 153961 11085192 [ 0 0 0 0 153961 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_6_Writeback_Control: 154441 1235528 [ 0 0 0 154441 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Response_Data: 152711 10995192 [ 0 0 0 0 152711 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_7_Writeback_Control: 153205 1225640 [ 0 0 0 153205 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Control: 1227324 9818592 [ 0 0 1227324 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_9_link_8_Data: 1214708 87458976 [ 0 0 1214708 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_9: 0.678994
+  links_utilized_percent_switch_9_link_0: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 0.694426 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 0.694425 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 0.694421 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 153595 1228760 [ 0 0 0 153595 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 153593 11058696 [ 0 0 0 0 153593 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 153592 11058624 [ 0 0 0 0 153592 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 153594 1228752 [ 0 0 0 153594 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Control: 1228757 9830056 [ 0 0 1228757 0 0 0 0 0 0 0 ] base_latency: 1
 
 Cache Stats: system.l1_cntrl0.cacheMemory
-  system.l1_cntrl0.cacheMemory_total_misses: 153154
-  system.l1_cntrl0.cacheMemory_total_demand_misses: 153154
+  system.l1_cntrl0.cacheMemory_total_misses: 153595
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 153595
   system.l1_cntrl0.cacheMemory_total_prefetches: 0
   system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.cacheMemory_request_type_LD:   65.2232%
-  system.l1_cntrl0.cacheMemory_request_type_ST:   34.7768%
+  system.l1_cntrl0.cacheMemory_request_type_LD:   64.8608%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   35.1392%
 
-  system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode:   153154    100%
+  system.l1_cntrl0.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870
+Load [100001 99948 99718 99978 99623 99719 99984 99512 ] 798483
 Ifetch [0 0 0 0 0 0 0 0 ] 0
-Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454
-Data [153756 153611 153961 152711 153153 153353 153380 153388 ] 1227313
-Fwd_GETX [2063 1992 2038 2104 2111 2044 2088 2074 ] 16514
+Store [53593 53647 53876 53616 53974 53880 53619 54083 ] 430288
+Data [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
+Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
 Inv [0 0 0 0 0 0 0 0 ] 0
-Replacement [153754 153609 153958 152708 153150 153351 153377 153385 ] 1227292
-Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758
-Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930
+Replacement [0 0 0 0 0 0 0 0 ] 0
+Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
  - Transitions -
-I  Load [99856 100002 99839 99184 99892 99648 99764 99685 ] 797870
+I  Load [100001 99948 99718 99978 99623 99718 99978 99512 ] 798476
 I  Ifetch [0 0 0 0 0 0 0 0 ] 0
-I  Store [53902 53611 54123 53528 53262 53707 53617 53704 ] 429454
+I  Store [53593 53647 53876 53616 53972 53877 53617 54083 ] 430281
 I  Inv [0 0 0 0 0 0 0 0 ] 0
-I  Replacement [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584
+I  Replacement [0 0 0 0 0 0 0 0 ] 0
 
-II  Writeback_Nack [481 493 486 502 486 483 519 480 ] 3930
+II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
-M  Load [0 0 0 0 0 0 0 0 ] 0
+M  Load [0 0 0 0 0 1 6 0 ] 7
 M  Ifetch [0 0 0 0 0 0 0 0 ] 0
-M  Store [0 0 0 0 0 0 0 0 ] 0
-M  Fwd_GETX [1582 1499 1552 1602 1625 1561 1569 1594 ] 12584
+M  Store [0 0 0 0 2 3 2 0 ] 7
+M  Fwd_GETX [153593 153593 153593 153592 153593 153593 153593 153593 ] 1228743
 M  Inv [0 0 0 0 0 0 0 0 ] 0
-M  Replacement [152172 152110 152406 151106 151525 151790 151808 151791 ] 1214708
+M  Replacement [0 0 0 0 0 0 0 0 ] 0
 
-MI  Fwd_GETX [481 493 486 502 486 483 519 480 ] 3930
+MI  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
 MI  Inv [0 0 0 0 0 0 0 0 ] 0
-MI  Writeback_Ack [151688 151612 151917 150599 151038 151306 151288 151310 ] 1210758
+MI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
 MI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
 
 MII  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
 
-IS  Data [99856 100000 99838 99183 99892 99647 99764 99684 ] 797864
+IS  Data [100000 99946 99718 99976 99622 99716 99977 99512 ] 798467
 
-IM  Data [53900 53611 54123 53528 53261 53706 53616 53704 ] 429449
+IM  Data [53593 53647 53875 53616 53971 53877 53616 54081 ] 430276
 
 Cache Stats: system.l1_cntrl1.cacheMemory
-  system.l1_cntrl1.cacheMemory_total_misses: 153355
-  system.l1_cntrl1.cacheMemory_total_demand_misses: 153355
+  system.l1_cntrl1.cacheMemory_total_misses: 153595
+  system.l1_cntrl1.cacheMemory_total_demand_misses: 153595
   system.l1_cntrl1.cacheMemory_total_prefetches: 0
   system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl1.cacheMemory_request_type_LD:   64.9786%
-  system.l1_cntrl1.cacheMemory_request_type_ST:   35.0214%
+  system.l1_cntrl1.cacheMemory_request_type_LD:   64.9227%
+  system.l1_cntrl1.cacheMemory_request_type_ST:   35.0773%
 
-  system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode:   153355    100%
+  system.l1_cntrl1.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
 
 Cache Stats: system.l1_cntrl2.cacheMemory
-  system.l1_cntrl2.cacheMemory_total_misses: 153381
-  system.l1_cntrl2.cacheMemory_total_demand_misses: 153381
+  system.l1_cntrl2.cacheMemory_total_misses: 153595
+  system.l1_cntrl2.cacheMemory_total_demand_misses: 153595
   system.l1_cntrl2.cacheMemory_total_prefetches: 0
   system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl2.cacheMemory_request_type_LD:   65.0433%
-  system.l1_cntrl2.cacheMemory_request_type_ST:   34.9567%
+  system.l1_cntrl2.cacheMemory_request_type_LD:   65.092%
+  system.l1_cntrl2.cacheMemory_request_type_ST:   34.908%
 
-  system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode:   153381    100%
+  system.l1_cntrl2.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
 
 Cache Stats: system.l1_cntrl3.cacheMemory
-  system.l1_cntrl3.cacheMemory_total_misses: 153389
-  system.l1_cntrl3.cacheMemory_total_demand_misses: 153389
+  system.l1_cntrl3.cacheMemory_total_misses: 153595
+  system.l1_cntrl3.cacheMemory_total_demand_misses: 153595
   system.l1_cntrl3.cacheMemory_total_prefetches: 0
   system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl3.cacheMemory_request_type_LD:   64.9884%
-  system.l1_cntrl3.cacheMemory_request_type_ST:   35.0116%
+  system.l1_cntrl3.cacheMemory_request_type_LD:   64.7886%
+  system.l1_cntrl3.cacheMemory_request_type_ST:   35.2114%
 
-  system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode:   153389    100%
+  system.l1_cntrl3.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
 
 Cache Stats: system.l1_cntrl4.cacheMemory
-  system.l1_cntrl4.cacheMemory_total_misses: 153758
-  system.l1_cntrl4.cacheMemory_total_demand_misses: 153758
+  system.l1_cntrl4.cacheMemory_total_misses: 153594
+  system.l1_cntrl4.cacheMemory_total_demand_misses: 153594
   system.l1_cntrl4.cacheMemory_total_prefetches: 0
   system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl4.cacheMemory_request_type_LD:   64.9436%
-  system.l1_cntrl4.cacheMemory_request_type_ST:   35.0564%
+  system.l1_cntrl4.cacheMemory_request_type_LD:   65.1074%
+  system.l1_cntrl4.cacheMemory_request_type_ST:   34.8926%
 
-  system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode:   153758    100%
+  system.l1_cntrl4.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
 
 Cache Stats: system.l1_cntrl5.cacheMemory
-  system.l1_cntrl5.cacheMemory_total_misses: 153613
-  system.l1_cntrl5.cacheMemory_total_demand_misses: 153613
+  system.l1_cntrl5.cacheMemory_total_misses: 153595
+  system.l1_cntrl5.cacheMemory_total_demand_misses: 153595
   system.l1_cntrl5.cacheMemory_total_prefetches: 0
   system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl5.cacheMemory_request_type_LD:   65.1%
-  system.l1_cntrl5.cacheMemory_request_type_ST:   34.9%
+  system.l1_cntrl5.cacheMemory_request_type_LD:   65.0724%
+  system.l1_cntrl5.cacheMemory_request_type_ST:   34.9276%
 
-  system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode:   153613    100%
+  system.l1_cntrl5.cacheMemory_access_mode_type_SupervisorMode:   153595    100%
 
 Cache Stats: system.l1_cntrl6.cacheMemory
-  system.l1_cntrl6.cacheMemory_total_misses: 153962
-  system.l1_cntrl6.cacheMemory_total_demand_misses: 153962
+  system.l1_cntrl6.cacheMemory_total_misses: 153594
+  system.l1_cntrl6.cacheMemory_total_demand_misses: 153594
   system.l1_cntrl6.cacheMemory_total_prefetches: 0
   system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl6.cacheMemory_request_type_LD:   64.8465%
-  system.l1_cntrl6.cacheMemory_request_type_ST:   35.1535%
+  system.l1_cntrl6.cacheMemory_request_type_LD:   64.9231%
+  system.l1_cntrl6.cacheMemory_request_type_ST:   35.0769%
 
-  system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode:   153962    100%
+  system.l1_cntrl6.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
 
 Cache Stats: system.l1_cntrl7.cacheMemory
-  system.l1_cntrl7.cacheMemory_total_misses: 152712
-  system.l1_cntrl7.cacheMemory_total_demand_misses: 152712
+  system.l1_cntrl7.cacheMemory_total_misses: 153594
+  system.l1_cntrl7.cacheMemory_total_demand_misses: 153594
   system.l1_cntrl7.cacheMemory_total_prefetches: 0
   system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl7.cacheMemory_request_type_LD:   64.9484%
-  system.l1_cntrl7.cacheMemory_request_type_ST:   35.0516%
+  system.l1_cntrl7.cacheMemory_request_type_LD:   65.0924%
+  system.l1_cntrl7.cacheMemory_request_type_ST:   34.9076%
 
-  system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode:   152712    100%
+  system.l1_cntrl7.cacheMemory_access_mode_type_SupervisorMode:   153594    100%
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 2421588
-  memory_reads: 1210803
-  memory_writes: 1210758
-  memory_refreshes: 119274
-  memory_total_request_delays: 190155514
-  memory_delays_per_request: 78.5251
-  memory_delays_in_input_queue: 11307810
-  memory_delays_behind_head_of_bank_queue: 85310074
-  memory_delays_stalled_at_head_of_bank_queue: 93537630
-  memory_stalls_for_bank_busy: 14384463
+  memory_total_requests: 2
+  memory_reads: 2
+  memory_writes: 0
+  memory_refreshes: 22
+  memory_total_request_delays: 31
+  memory_delays_per_request: 15.5
+  memory_delays_in_input_queue: 1
+  memory_delays_behind_head_of_bank_queue: 10
+  memory_delays_stalled_at_head_of_bank_queue: 20
+  memory_stalls_for_bank_busy: 20
   memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 24076432
-  memory_stalls_for_arbitration: 18499124
-  memory_stalls_for_bus: 25289267
+  memory_stalls_for_anti_starvation: 0
+  memory_stalls_for_arbitration: 0
+  memory_stalls_for_bus: 0
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 9173208
-  memory_stalls_for_read_read_turnaround: 2115136
-  accesses_per_bank: 75973  75871  75584  75990  75871  76208  76264  75323  76082  76056  76271  75892  75688  75751  75586  75406  75587  75216  76023  75699  75573  75534  75382  75564  75891  75161  75298  74700  75598  75166  76030  75350  
+  memory_stalls_for_read_write_turnaround: 0
+  memory_stalls_for_read_read_turnaround: 0
+  accesses_per_bank: 2  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  
 
  --- Directory ---
  - Event Counts -
-GETX [2497405 ] 2497405
+GETX [1229168 ] 1229168
 GETS [0 ] 0
-PUTX [1210778 ] 1210778
-PUTX_NotOwner [3930 ] 3930
+PUTX [0 ] 0
+PUTX_NotOwner [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [1210799 ] 1210799
-Memory_Ack [1210758 ] 1210758
+Memory_Data [2 ] 2
+Memory_Ack [0 ] 0
 
  - Transitions -
-I  GETX [1210810 ] 1210810
+I  GETX [2 ] 2
 I  PUTX_NotOwner [0 ] 0
 I  DMA_READ [0 ] 0
 I  DMA_WRITE [0 ] 0
 
-M  GETX [16514 ] 16514
-M  PUTX [1210778 ] 1210778
-M  PUTX_NotOwner [3930 ] 3930
+M  GETX [1228755 ] 1228755
+M  PUTX [0 ] 0
+M  PUTX_NotOwner [0 ] 0
 M  DMA_READ [0 ] 0
 M  DMA_WRITE [0 ] 0
 
@@ -464,21 +455,21 @@ M_DWRI  Memory_Ack [0 ] 0
 M_DRDI  GETX [0 ] 0
 M_DRDI  Memory_Ack [0 ] 0
 
-IM  GETX [491344 ] 491344
+IM  GETX [411 ] 411
 IM  GETS [0 ] 0
 IM  PUTX [0 ] 0
 IM  PUTX_NotOwner [0 ] 0
 IM  DMA_READ [0 ] 0
 IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [1210799 ] 1210799
+IM  Memory_Data [2 ] 2
 
-MI  GETX [778737 ] 778737
+MI  GETX [0 ] 0
 MI  GETS [0 ] 0
 MI  PUTX [0 ] 0
 MI  PUTX_NotOwner [0 ] 0
 MI  DMA_READ [0 ] 0
 MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [1210758 ] 1210758
+MI  Memory_Ack [0 ] 0
 
 ID  GETX [0 ] 0
 ID  GETS [0 ] 0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index e2711df60..bc0af1811 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -1,74 +1,74 @@
-system.cpu5: completed 10000 read accesses @5727250
-system.cpu4: completed 10000 read accesses @5731690
-system.cpu7: completed 10000 read accesses @5735040
-system.cpu3: completed 10000 read accesses @5738300
-system.cpu6: completed 10000 read accesses @5748590
-system.cpu2: completed 10000 read accesses @5761080
-system.cpu0: completed 10000 read accesses @5773280
-system.cpu1: completed 10000 read accesses @5776650
-system.cpu4: completed 20000 read accesses @11398130
-system.cpu1: completed 20000 read accesses @11455110
-system.cpu3: completed 20000 read accesses @11459820
-system.cpu6: completed 20000 read accesses @11463230
-system.cpu0: completed 20000 read accesses @11469310
-system.cpu5: completed 20000 read accesses @11490080
-system.cpu2: completed 20000 read accesses @11498750
-system.cpu7: completed 20000 read accesses @11572610
-system.cpu4: completed 30000 read accesses @17076120
-system.cpu1: completed 30000 read accesses @17150670
-system.cpu5: completed 30000 read accesses @17204690
-system.cpu3: completed 30000 read accesses @17209580
-system.cpu0: completed 30000 read accesses @17264545
-system.cpu6: completed 30000 read accesses @17274220
-system.cpu2: completed 30000 read accesses @17284860
-system.cpu7: completed 30000 read accesses @17343350
-system.cpu4: completed 40000 read accesses @22747010
-system.cpu1: completed 40000 read accesses @22900920
-system.cpu5: completed 40000 read accesses @22928450
-system.cpu3: completed 40000 read accesses @22962360
-system.cpu0: completed 40000 read accesses @22981310
-system.cpu6: completed 40000 read accesses @23018750
-system.cpu2: completed 40000 read accesses @23061180
-system.cpu7: completed 40000 read accesses @23154824
-system.cpu4: completed 50000 read accesses @28547090
-system.cpu5: completed 50000 read accesses @28620310
-system.cpu1: completed 50000 read accesses @28677730
-system.cpu3: completed 50000 read accesses @28690730
-system.cpu6: completed 50000 read accesses @28729220
-system.cpu0: completed 50000 read accesses @28766380
-system.cpu2: completed 50000 read accesses @28834360
-system.cpu7: completed 50000 read accesses @28946860
-system.cpu4: completed 60000 read accesses @34313400
-system.cpu5: completed 60000 read accesses @34314670
-system.cpu3: completed 60000 read accesses @34419440
-system.cpu1: completed 60000 read accesses @34450630
-system.cpu6: completed 60000 read accesses @34477780
-system.cpu0: completed 60000 read accesses @34500340
-system.cpu2: completed 60000 read accesses @34535810
-system.cpu7: completed 60000 read accesses @34657810
-system.cpu5: completed 70000 read accesses @40003670
-system.cpu4: completed 70000 read accesses @40058990
-system.cpu3: completed 70000 read accesses @40162430
-system.cpu0: completed 70000 read accesses @40197610
-system.cpu6: completed 70000 read accesses @40218844
-system.cpu1: completed 70000 read accesses @40223070
-system.cpu2: completed 70000 read accesses @40246640
-system.cpu7: completed 70000 read accesses @40416250
-system.cpu5: completed 80000 read accesses @45745700
-system.cpu4: completed 80000 read accesses @45764460
-system.cpu3: completed 80000 read accesses @45881080
-system.cpu0: completed 80000 read accesses @45887290
-system.cpu2: completed 80000 read accesses @45902430
-system.cpu6: completed 80000 read accesses @45914170
-system.cpu1: completed 80000 read accesses @46020320
-system.cpu7: completed 80000 read accesses @46126230
-system.cpu5: completed 90000 read accesses @51539850
-system.cpu6: completed 90000 read accesses @51572100
-system.cpu4: completed 90000 read accesses @51579370
-system.cpu0: completed 90000 read accesses @51603670
-system.cpu3: completed 90000 read accesses @51633670
-system.cpu2: completed 90000 read accesses @51656890
-system.cpu1: completed 90000 read accesses @51768690
-system.cpu7: completed 90000 read accesses @51933040
-system.cpu5: completed 100000 read accesses @57251340
+system.cpu5: completed 10000 read accesses @1097056
+system.cpu4: completed 10000 read accesses @1101790
+system.cpu2: completed 10000 read accesses @1104058
+system.cpu0: completed 10000 read accesses @1107910
+system.cpu7: completed 10000 read accesses @1111870
+system.cpu1: completed 10000 read accesses @1114192
+system.cpu6: completed 10000 read accesses @1114876
+system.cpu3: completed 10000 read accesses @1117090
+system.cpu5: completed 20000 read accesses @2192968
+system.cpu0: completed 20000 read accesses @2201554
+system.cpu2: completed 20000 read accesses @2213290
+system.cpu4: completed 20000 read accesses @2213470
+system.cpu6: completed 20000 read accesses @2213812
+system.cpu7: completed 20000 read accesses @2222758
+system.cpu1: completed 20000 read accesses @2232856
+system.cpu3: completed 20000 read accesses @2238562
+system.cpu5: completed 30000 read accesses @3309256
+system.cpu6: completed 30000 read accesses @3313180
+system.cpu0: completed 30000 read accesses @3314566
+system.cpu4: completed 30000 read accesses @3316942
+system.cpu2: completed 30000 read accesses @3324682
+system.cpu7: completed 30000 read accesses @3331702
+system.cpu1: completed 30000 read accesses @3337912
+system.cpu3: completed 30000 read accesses @3342322
+system.cpu5: completed 40000 read accesses @4420792
+system.cpu7: completed 40000 read accesses @4420990
+system.cpu6: completed 40000 read accesses @4421692
+system.cpu4: completed 40000 read accesses @4422430
+system.cpu0: completed 40000 read accesses @4424770
+system.cpu2: completed 40000 read accesses @4424842
+system.cpu3: completed 40000 read accesses @4446316
+system.cpu1: completed 40000 read accesses @4448440
+system.cpu5: completed 50000 read accesses @5519584
+system.cpu4: completed 50000 read accesses @5528980
+system.cpu0: completed 50000 read accesses @5530150
+system.cpu2: completed 50000 read accesses @5533210
+system.cpu7: completed 50000 read accesses @5537782
+system.cpu6: completed 50000 read accesses @5538916
+system.cpu3: completed 50000 read accesses @5549410
+system.cpu1: completed 50000 read accesses @5549536
+system.cpu7: completed 60000 read accesses @6629734
+system.cpu5: completed 60000 read accesses @6636160
+system.cpu4: completed 60000 read accesses @6637060
+system.cpu2: completed 60000 read accesses @6637402
+system.cpu0: completed 60000 read accesses @6644710
+system.cpu1: completed 60000 read accesses @6651352
+system.cpu6: completed 60000 read accesses @6651892
+system.cpu3: completed 60000 read accesses @6661234
+system.cpu7: completed 70000 read accesses @7727014
+system.cpu4: completed 70000 read accesses @7730110
+system.cpu5: completed 70000 read accesses @7736608
+system.cpu2: completed 70000 read accesses @7742746
+system.cpu6: completed 70000 read accesses @7757092
+system.cpu0: completed 70000 read accesses @7759378
+system.cpu1: completed 70000 read accesses @7770088
+system.cpu3: completed 70000 read accesses @7773058
+system.cpu5: completed 80000 read accesses @8842240
+system.cpu7: completed 80000 read accesses @8843086
+system.cpu4: completed 80000 read accesses @8844580
+system.cpu2: completed 80000 read accesses @8853131
+system.cpu0: completed 80000 read accesses @8863426
+system.cpu6: completed 80000 read accesses @8876836
+system.cpu1: completed 80000 read accesses @8878960
+system.cpu3: completed 80000 read accesses @8885602
+system.cpu5: completed 90000 read accesses @9955126
+system.cpu7: completed 90000 read accesses @9956782
+system.cpu4: completed 90000 read accesses @9957844
+system.cpu2: completed 90000 read accesses @9967690
+system.cpu1: completed 90000 read accesses @9973576
+system.cpu0: completed 90000 read accesses @9976024
+system.cpu6: completed 90000 read accesses @9981604
+system.cpu3: completed 90000 read accesses @9999874
+system.cpu4: completed 100000 read accesses @11059012
 hack: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 444f67465..5cb14d0de 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:58
-M5 executing on SC2B0617
+M5 compiled Aug 20 2010 12:21:09
+M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
+M5 started Aug 20 2010 13:38:22
+M5 executing on SC2B0629
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 57251340 because maximum number of loads reached
+Exiting @ tick 11059012 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 7a7c704fc..09849fe3c 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 345644                       # Number of bytes of host memory used
-host_seconds                                    87.47                       # Real time elapsed on the host
-host_tick_rate                                 654526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 341104                       # Number of bytes of host memory used
+host_seconds                                    68.57                       # Real time elapsed on the host
+host_tick_rate                                 161272                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.057251                       # Number of seconds simulated
-sim_ticks                                    57251340                       # Number of ticks simulated
+sim_seconds                                  0.011059                       # Number of seconds simulated
+sim_ticks                                    11059012                       # Number of ticks simulated
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99892                       # number of read accesses completed
-system.cpu0.num_writes                          53261                       # number of write accesses completed
+system.cpu0.num_reads                           99622                       # number of read accesses completed
+system.cpu0.num_writes                          53973                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99647                       # number of read accesses completed
-system.cpu1.num_writes                          53706                       # number of write accesses completed
+system.cpu1.num_reads                           99717                       # number of read accesses completed
+system.cpu1.num_writes                          53880                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99764                       # number of read accesses completed
-system.cpu2.num_writes                          53616                       # number of write accesses completed
+system.cpu2.num_reads                           99983                       # number of read accesses completed
+system.cpu2.num_writes                          53618                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99684                       # number of read accesses completed
-system.cpu3.num_writes                          53704                       # number of write accesses completed
+system.cpu3.num_reads                           99512                       # number of read accesses completed
+system.cpu3.num_writes                          54081                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99856                       # number of read accesses completed
-system.cpu4.num_writes                          53900                       # number of write accesses completed
+system.cpu4.num_reads                          100000                       # number of read accesses completed
+system.cpu4.num_writes                          53593                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                          100000                       # number of read accesses completed
-system.cpu5.num_writes                          53611                       # number of write accesses completed
+system.cpu5.num_reads                           99946                       # number of read accesses completed
+system.cpu5.num_writes                          53647                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           99838                       # number of read accesses completed
-system.cpu6.num_writes                          54123                       # number of write accesses completed
+system.cpu6.num_reads                           99718                       # number of read accesses completed
+system.cpu6.num_writes                          53875                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                           99183                       # number of read accesses completed
-system.cpu7.num_writes                          53528                       # number of write accesses completed
+system.cpu7.num_reads                           99976                       # number of read accesses completed
+system.cpu7.num_writes                          53616                       # number of write accesses completed
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index 4e966d986..5a4805332 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.cpu0]
 type=MemTest
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
index 04203f57c..073fadf83 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:36
-M5 executing on SC2B0617
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
+M5 compiled Sep 20 2010 15:04:49
+M5 revision 0c4a7d867247 7686 default qtip print-identical tip
+M5 started Sep 20 2010 15:50:04
+M5 executing on phenom
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
index 8f03d7ea4..54a425295 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 331768                       # Number of bytes of host memory used
-host_seconds                                   205.21                       # Real time elapsed on the host
-host_tick_rate                                1284021                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318984                       # Number of bytes of host memory used
+host_seconds                                   150.28                       # Real time elapsed on the host
+host_tick_rate                                1753313                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000263                       # Number of seconds simulated
 sim_ticks                                   263488655                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
index f899b1907..d0385930a 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
 children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -139,7 +130,6 @@ tracer=system.ruby.tracer
 
 [system.ruby.cpu_ruby_ports]
 type=RubySequencer
-access_phys_mem=true
 dcache=system.l1_cntrl0.L1DcacheMemory
 deadlock_threshold=500000
 icache=system.l1_cntrl0.L1IcacheMemory
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 662729671..4c6a0f41e 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:26
+Real time: Jan/13/2011 22:36:32
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 2
+Elapsed_time_in_minutes: 0.0333333
+Elapsed_time_in_hours: 0.000555556
+Elapsed_time_in_days: 2.31481e-05
 
-Virtual_time_in_seconds: 0.77
-Virtual_time_in_minutes: 0.0128333
-Virtual_time_in_hours:   0.000213889
-Virtual_time_in_days:    8.91204e-06
+Virtual_time_in_seconds: 2.32
+Virtual_time_in_minutes: 0.0386667
+Virtual_time_in_hours:   0.000644444
+Virtual_time_in_days:    2.68519e-05
 
 Ruby_current_time: 352261
 Ruby_start_time: 0
 Ruby_cycles: 352261
 
-mbytes_resident: 33.6758
-mbytes_total: 208.004
-resident_ratio: 0.161937
+mbytes_resident: 19.4023
+mbytes_total: 155.219
+resident_ratio: 0.12505
 
 ruby_cycles_executed: [ 352262 ]
 
@@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4457 average:     0 | standa
 Resource Usage
 --------------
 page_size: 4096
-user_time: 0
+user_time: 2
 system_time: 0
-page_reclaims: 9855
+page_reclaims: 5638
 page_faults: 0
 swaps: 0
 block_inputs: 0
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index 060588f40..866f889aa 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:58
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:26
-M5 executing on SC2B0617
+M5 compiled Jan 13 2011 22:36:25
+M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip
+M5 started Jan 13 2011 22:36:30
+M5 executing on scamorza.cs.wisc.edu
 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index 8b5ff7aed..ea583927f 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 213000                       # Number of bytes of host memory used
-host_seconds                                     0.50                       # Real time elapsed on the host
-host_tick_rate                                 702206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 158948                       # Number of bytes of host memory used
+host_seconds                                     1.84                       # Real time elapsed on the host
+host_tick_rate                                 191255                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000352                       # Number of seconds simulated
 sim_ticks                                      352261                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index 326e421d1..f737a2a36 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -61,19 +52,32 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 buffer_size=0
 l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 request_latency=2
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=3
@@ -81,7 +85,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=3
@@ -117,13 +121,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -133,18 +138,13 @@ randomization=true
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -160,9 +160,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
@@ -224,10 +224,3 @@ num_of_sequencers=1
 type=RubyTracer
 warmup_length=100000
 
-[system.tester]
-type=RubyTester
-checks_to_complete=100
-deadlock_threshold=50000
-wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
-
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index ecf0309aa..8aa6f62e7 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, unordered
 virtual_net_1: active, unordered
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:43:54
+Real time: Aug/05/2010 10:40:25
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.75
-Virtual_time_in_minutes: 0.0125
-Virtual_time_in_hours:   0.000208333
-Virtual_time_in_days:    8.68056e-06
+Virtual_time_in_seconds: 1.03
+Virtual_time_in_minutes: 0.0171667
+Virtual_time_in_hours:   0.000286111
+Virtual_time_in_days:    1.19213e-05
 
 Ruby_current_time: 372291
 Ruby_start_time: 0
 Ruby_cycles: 372291
 
-mbytes_resident: 33.7773
-mbytes_total: 208.145
-resident_ratio: 0.162316
+mbytes_resident: 31.6016
+mbytes_total: 31.6094
+resident_ratio: 1
 
 ruby_cycles_executed: [ 372292 ]
 
@@ -119,8 +119,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9852
-page_faults: 0
+page_reclaims: 7050
+page_faults: 1907
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.174693
   outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
 
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
 
  --- L1Cache ---
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 54b47c790..f20a07162 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:43:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:43:54
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:34:54
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:40:24
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 39fab38a1..c117a9137 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 213144                       # Number of bytes of host memory used
-host_seconds                                     0.49                       # Real time elapsed on the host
-host_tick_rate                                 753490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210064                       # Number of bytes of host memory used
+host_seconds                                     0.80                       # Real time elapsed on the host
+host_tick_rate                                 465329                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000372                       # Number of seconds simulated
 sim_ticks                                      372291                       # Number of ticks simulated
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 76dc82aa2..e21f56989 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -64,9 +55,9 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L1DcacheMemory L1IcacheMemory
-L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
-L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+children=sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 N_tokens=2
 buffer_size=0
 dynamic_timeout_enabled=true
@@ -78,11 +69,24 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
-[system.l1_cntrl0.L1DcacheMemory]
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=dcache icache
+dcache=system.l1_cntrl0.sequencer.dcache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -90,7 +94,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.l1_cntrl0.L1IcacheMemory]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -128,13 +132,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -144,18 +149,13 @@ randomization=true
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-access_phys_mem=true
-dcache=system.l1_cntrl0.L1DcacheMemory
-deadlock_threshold=500000
-icache=system.l1_cntrl0.L1IcacheMemory
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -171,9 +171,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
+name=Crossbar
 num_int_nodes=4
 print_config=false
 
@@ -235,10 +235,3 @@ num_of_sequencers=1
 type=RubyTracer
 warmup_length=100000
 
-[system.tester]
-type=RubyTester
-checks_to_complete=100
-deadlock_threshold=50000
-wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
-
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index 86720f36f..10b36c0bf 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, unordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:27:50
+Real time: Aug/05/2010 10:45:27
 
 Profiler Stats
 --------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.41
-Virtual_time_in_minutes: 0.00683333
-Virtual_time_in_hours:   0.000113889
-Virtual_time_in_days:    4.74537e-06
+Virtual_time_in_seconds: 0.75
+Virtual_time_in_minutes: 0.0125
+Virtual_time_in_hours:   0.000208333
+Virtual_time_in_days:    8.68056e-06
 
-Ruby_current_time: 267511
+Ruby_current_time: 273851
 Ruby_start_time: 0
-Ruby_cycles: 267511
+Ruby_cycles: 273851
 
-mbytes_resident: 33.7539
-mbytes_total: 208.121
-resident_ratio: 0.16224
+mbytes_resident: 31.5859
+mbytes_total: 31.5938
+resident_ratio: 1
 
-ruby_cycles_executed: [ 267512 ]
+ruby_cycles_executed: [ 273852 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -66,17 +66,17 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.8225 | standard deviation: 1.14181 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 902 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 64 max: 6580 count: 954 average: 4444.74 | standard deviation: 1862.02 | 67 9 3 1 6 4 9 12 10 7 1 8 5 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 8 max: 1214 count: 48 average: 548.458 | standard deviation: 260.39 | 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
-miss_latency_LD: [binsize: 32 max: 6135 count: 52 average: 4940.85 | standard deviation: 1334.03 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
-miss_latency_ST: [binsize: 64 max: 6580 count: 854 average: 4633.53 | standard deviation: 1690.7 | 62 8 1 0 3 2 5 7 3 2 0 1 1 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 117 count: 73 average: 12.8356 | standard deviation: 32.0687 | 0 17 17 15 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 2 ]
-miss_latency_L2Cache: [binsize: 8 max: 812 count: 13 average: 309.154 | standard deviation: 223.678 | 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Directory: [binsize: 64 max: 6580 count: 868 average: 4879.41 | standard deviation: 1307.99 | 0 0 1 1 4 2 7 12 10 6 1 8 4 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
+miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -86,15 +86,16 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
 miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_dir_Times: 868
-miss_latency_IFETCH_L1Cache: [binsize: 1 max: 108 count: 2 average:  55.5 | standard deviation: 74.2496 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH_L2Cache: [binsize: 2 max: 359 count: 3 average: 181.333 | standard deviation: 165.7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_IFETCH_Directory: [binsize: 8 max: 1214 count: 43 average:   597 | standard deviation: 225.443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 3 average: 1.66667 | standard deviation: 0.707107 | 0 1 2 ]
-miss_latency_LD_Directory: [binsize: 32 max: 6135 count: 49 average: 5243.24 | standard deviation: 522.306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 68 average: 12.0735 | standard deviation: 31.0217 | 0 16 15 14 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 2 ]
-miss_latency_ST_L2Cache: [binsize: 8 max: 812 count: 10 average: 347.5 | standard deviation: 231.361 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_Directory: [binsize: 64 max: 6580 count: 776 average: 5093.73 | standard deviation: 906.859 | 0 0 0 0 1 1 3 7 3 1 0 1 0 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 902
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average:     4 | standard deviation: 0 | 0 0 0 0 1 ]
+miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ]
+miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ]
+miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -126,8 +127,8 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9852
-page_faults: 0
+page_reclaims: 7004
+page_faults: 1904
 swaps: 0
 block_inputs: 0
 block_outputs: 0
@@ -135,116 +136,120 @@ block_outputs: 0
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 5259 42072
-total_msg_count_Response_Data: 2727 196344
-total_msg_count_ResponseL2hit_Data: 33 2376
-total_msg_count_Response_Control: 3 24
-total_msg_count_Writeback_Data: 5187 373464
-total_msg_count_Writeback_Control: 234 1872
-total_msg_count_Persistent_Control: 2388 19104
-total_msgs: 15831 total_bytes: 635256
+total_msg_count_Request_Control: 5485 43880
+total_msg_count_Response_Data: 2871 206712
+total_msg_count_ResponseL2hit_Data: 51 3672
+total_msg_count_Response_Control: 9 72
+total_msg_count_Writeback_Data: 5349 385128
+total_msg_count_Writeback_Control: 246 1968
+total_msg_count_Persistent_Control: 2292 18336
+total_msgs: 16303 total_bytes: 659768
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.115486
-  links_utilized_percent_switch_0_link_0: 0.0430356 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.187936 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_0_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 0 0 0 955 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.115928
+  links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0975123
-  links_utilized_percent_switch_1_link_0: 0.0428627 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.152162 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 768 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.0997532
+  links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.0934167
-  links_utilized_percent_switch_2_link_0: 0.0396432 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.14719 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.09541
+  links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
 
 switch_3_inlinks: 3
 switch_3_outlinks: 3
-links_utilized_percent_switch_3: 0.164909
-  links_utilized_percent_switch_3_link_0: 0.164704 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_3_link_1: 0.171451 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_3_link_2: 0.158573 bw: 160000 base_latency: 1
-
-  outgoing_messages_switch_3_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_3_link_2_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1
-
-Cache Stats: system.l1_cntrl0.L1IcacheMemory
-  system.l1_cntrl0.L1IcacheMemory_total_misses: 46
-  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 46
-  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
-
-  system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH:   100%
-
-  system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode:   46    100%
-
-Cache Stats: system.l1_cntrl0.L1DcacheMemory
-  system.l1_cntrl0.L1DcacheMemory_total_misses: 836
-  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 836
-  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
-  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
-
-  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   5.86124%
-  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   94.1388%
-
-  system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode:   836    100%
+links_utilized_percent_switch_3: 0.167305
+  links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 58
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 58
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
+
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
+
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   58    100%
+
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 865
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
+
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   4.39306%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   95.6069%
+
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   865    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [52 ] 52
-Ifetch [48 ] 48
-Store [855 ] 855
+Load [41 ] 41
+Ifetch [59 ] 59
+Store [901 ] 901
 Atomic [0 ] 0
-L1_Replacement [19142 ] 19142
-Data_Shared [3 ] 3
-Data_Owner [0 ] 0
-Data_All_Tokens [976 ] 976
-Ack [1 ] 1
-Ack_All_Tokens [0 ] 0
+L1_Replacement [388292 ] 388292
+Data_Shared [9 ] 9
+Data_Owner [2 ] 2
+Data_All_Tokens [998 ] 998
+Ack [2 ] 2
+Ack_All_Tokens [2 ] 2
 Transient_GETX [0 ] 0
 Transient_Local_GETX [0 ] 0
 Transient_GETS [0 ] 0
@@ -254,21 +259,21 @@ Transient_Local_GETS_Last_Token [0 ] 0
 Persistent_GETX [0 ] 0
 Persistent_GETS [0 ] 0
 Persistent_GETS_Last_Token [0 ] 0
-Own_Lock_or_Unlock [398 ] 398
-Request_Timeout [783 ] 783
+Own_Lock_or_Unlock [382 ] 382
+Request_Timeout [674 ] 674
 Use_TimeoutStarverX [0 ] 0
 Use_TimeoutStarverS [0 ] 0
-Use_TimeoutNoStarvers [877 ] 877
+Use_TimeoutNoStarvers [912 ] 912
 Use_TimeoutNoStarvers_NoMig [0 ] 0
 
  - Transitions -
-NP  Load [49 ] 49
-NP  Ifetch [46 ] 46
-NP  Store [787 ] 787
+NP  Load [38 ] 38
+NP  Ifetch [58 ] 58
+NP  Store [826 ] 826
 NP  Atomic [0 ] 0
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
-NP  Data_All_Tokens [98 ] 98
+NP  Data_All_Tokens [87 ] 87
 NP  Ack [0 ] 0
 NP  Transient_GETX [0 ] 0
 NP  Transient_Local_GETX [0 ] 0
@@ -277,7 +282,7 @@ NP  Transient_Local_GETS [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [190 ] 190
+NP  Own_Lock_or_Unlock [175 ] 175
 
 I  Load [0 ] 0
 I  Ifetch [0 ] 0
@@ -300,10 +305,10 @@ I  Persistent_GETS_Last_Token [0 ] 0
 I  Own_Lock_or_Unlock [0 ] 0
 
 S  Load [0 ] 0
-S  Ifetch [2 ] 2
-S  Store [0 ] 0
+S  Ifetch [1 ] 1
+S  Store [1 ] 1
 S  Atomic [0 ] 0
-S  L1_Replacement [3 ] 3
+S  L1_Replacement [8 ] 8
 S  Data_Shared [0 ] 0
 S  Data_Owner [0 ] 0
 S  Data_All_Tokens [0 ] 0
@@ -343,33 +348,33 @@ M  Load [0 ] 0
 M  Ifetch [0 ] 0
 M  Store [0 ] 0
 M  Atomic [0 ] 0
-M  L1_Replacement [88 ] 88
+M  L1_Replacement [83 ] 83
 M  Transient_GETX [0 ] 0
 M  Transient_Local_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
 M  Transient_Local_GETS [0 ] 0
 M  Persistent_GETX [0 ] 0
 M  Persistent_GETS [0 ] 0
-M  Own_Lock_or_Unlock [15 ] 15
+M  Own_Lock_or_Unlock [12 ] 12
 
 MM  Load [2 ] 2
 MM  Ifetch [0 ] 0
-MM  Store [57 ] 57
+MM  Store [64 ] 64
 MM  Atomic [0 ] 0
-MM  L1_Replacement [786 ] 786
+MM  L1_Replacement [826 ] 826
 MM  Transient_GETX [0 ] 0
 MM  Transient_Local_GETX [0 ] 0
 MM  Transient_GETS [0 ] 0
 MM  Transient_Local_GETS [0 ] 0
 MM  Persistent_GETX [0 ] 0
 MM  Persistent_GETS [0 ] 0
-MM  Own_Lock_or_Unlock [15 ] 15
+MM  Own_Lock_or_Unlock [27 ] 27
 
-M_W  Load [1 ] 1
+M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
 M_W  Store [1 ] 1
 M_W  Atomic [0 ] 0
-M_W  L1_Replacement [396 ] 396
+M_W  L1_Replacement [1338 ] 1338
 M_W  Transient_GETX [0 ] 0
 M_W  Transient_Local_GETX [0 ] 0
 M_W  Transient_GETS [0 ] 0
@@ -379,35 +384,35 @@ M_W  Persistent_GETS [0 ] 0
 M_W  Own_Lock_or_Unlock [1 ] 1
 M_W  Use_TimeoutStarverX [0 ] 0
 M_W  Use_TimeoutStarverS [0 ] 0
-M_W  Use_TimeoutNoStarvers [90 ] 90
+M_W  Use_TimeoutNoStarvers [85 ] 85
 M_W  Use_TimeoutNoStarvers_NoMig [0 ] 0
 
-MM_W  Load [0 ] 0
+MM_W  Load [1 ] 1
 MM_W  Ifetch [0 ] 0
-MM_W  Store [10 ] 10
+MM_W  Store [9 ] 9
 MM_W  Atomic [0 ] 0
-MM_W  L1_Replacement [7395 ] 7395
+MM_W  L1_Replacement [30069 ] 30069
 MM_W  Transient_GETX [0 ] 0
 MM_W  Transient_Local_GETX [0 ] 0
 MM_W  Transient_GETS [0 ] 0
 MM_W  Transient_Local_GETS [0 ] 0
 MM_W  Persistent_GETX [0 ] 0
 MM_W  Persistent_GETS [0 ] 0
-MM_W  Own_Lock_or_Unlock [25 ] 25
+MM_W  Own_Lock_or_Unlock [26 ] 26
 MM_W  Use_TimeoutStarverX [0 ] 0
 MM_W  Use_TimeoutStarverS [0 ] 0
-MM_W  Use_TimeoutNoStarvers [787 ] 787
+MM_W  Use_TimeoutNoStarvers [827 ] 827
 MM_W  Use_TimeoutNoStarvers_NoMig [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
 IM  Store [0 ] 0
 IM  Atomic [0 ] 0
-IM  L1_Replacement [9791 ] 9791
+IM  L1_Replacement [341249 ] 341249
 IM  Data_Shared [0 ] 0
-IM  Data_Owner [0 ] 0
-IM  Data_All_Tokens [786 ] 786
-IM  Ack [1 ] 1
+IM  Data_Owner [2 ] 2
+IM  Data_All_Tokens [823 ] 823
+IM  Ack [2 ] 2
 IM  Transient_GETX [0 ] 0
 IM  Transient_Local_GETX [0 ] 0
 IM  Transient_GETS [0 ] 0
@@ -417,8 +422,8 @@ IM  Transient_Local_GETS_Last_Token [0 ] 0
 IM  Persistent_GETX [0 ] 0
 IM  Persistent_GETS [0 ] 0
 IM  Persistent_GETS_Last_Token [0 ] 0
-IM  Own_Lock_or_Unlock [135 ] 135
-IM  Request_Timeout [709 ] 709
+IM  Own_Lock_or_Unlock [124 ] 124
+IM  Request_Timeout [608 ] 608
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -427,7 +432,7 @@ SM  Atomic [0 ] 0
 SM  L1_Replacement [0 ] 0
 SM  Data_Shared [0 ] 0
 SM  Data_Owner [0 ] 0
-SM  Data_All_Tokens [0 ] 0
+SM  Data_All_Tokens [1 ] 1
 SM  Ack [0 ] 0
 SM  Transient_GETX [0 ] 0
 SM  Transient_Local_GETX [0 ] 0
@@ -449,7 +454,7 @@ OM  L1_Replacement [0 ] 0
 OM  Data_Shared [0 ] 0
 OM  Data_All_Tokens [0 ] 0
 OM  Ack [0 ] 0
-OM  Ack_All_Tokens [0 ] 0
+OM  Ack_All_Tokens [2 ] 2
 OM  Transient_GETX [0 ] 0
 OM  Transient_Local_GETX [0 ] 0
 OM  Transient_GETS [0 ] 0
@@ -459,17 +464,17 @@ OM  Transient_Local_GETS_Last_Token [0 ] 0
 OM  Persistent_GETX [0 ] 0
 OM  Persistent_GETS [0 ] 0
 OM  Persistent_GETS_Last_Token [0 ] 0
-OM  Own_Lock_or_Unlock [0 ] 0
-OM  Request_Timeout [0 ] 0
+OM  Own_Lock_or_Unlock [1 ] 1
+OM  Request_Timeout [1 ] 1
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
 IS  Store [0 ] 0
 IS  Atomic [0 ] 0
-IS  L1_Replacement [683 ] 683
-IS  Data_Shared [3 ] 3
+IS  L1_Replacement [14719 ] 14719
+IS  Data_Shared [9 ] 9
 IS  Data_Owner [0 ] 0
-IS  Data_All_Tokens [92 ] 92
+IS  Data_All_Tokens [87 ] 87
 IS  Ack [0 ] 0
 IS  Transient_GETX [0 ] 0
 IS  Transient_Local_GETX [0 ] 0
@@ -480,8 +485,8 @@ IS  Transient_Local_GETS_Last_Token [0 ] 0
 IS  Persistent_GETX [0 ] 0
 IS  Persistent_GETS [0 ] 0
 IS  Persistent_GETS_Last_Token [0 ] 0
-IS  Own_Lock_or_Unlock [17 ] 17
-IS  Request_Timeout [74 ] 74
+IS  Own_Lock_or_Unlock [16 ] 16
+IS  Request_Timeout [65 ] 65
 
 I_L  Load [0 ] 0
 I_L  Ifetch [0 ] 0
@@ -585,50 +590,50 @@ IS_L  Own_Lock_or_Unlock [0 ] 0
 IS_L  Request_Timeout [0 ] 0
 
 Cache Stats: system.l2_cntrl0.L2cacheMemory
-  system.l2_cntrl0.L2cacheMemory_total_misses: 871
-  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 871
+  system.l2_cntrl0.L2cacheMemory_total_misses: 906
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906
   system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   10.5626%
-  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   89.4374%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   9.60265%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   90.3974%
 
-  system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   871    100%
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   906    100%
 
  --- L2Cache ---
  - Event Counts -
 L1_GETS [95 ] 95
-L1_GETS_Last_Token [0 ] 0
-L1_GETX [787 ] 787
+L1_GETS_Last_Token [1 ] 1
+L1_GETX [826 ] 826
 L1_INV [0 ] 0
 Transient_GETX [0 ] 0
 Transient_GETS [0 ] 0
 Transient_GETS_Last_Token [0 ] 0
-L2_Replacement [799 ] 799
+L2_Replacement [857 ] 857
 Writeback_Tokens [0 ] 0
-Writeback_Shared_Data [3 ] 3
-Writeback_All_Tokens [874 ] 874
+Writeback_Shared_Data [8 ] 8
+Writeback_All_Tokens [908 ] 908
 Writeback_Owned [0 ] 0
 Data_Shared [0 ] 0
 Data_Owner [0 ] 0
 Data_All_Tokens [0 ] 0
 Ack [0 ] 0
 Ack_All_Tokens [0 ] 0
-Persistent_GETX [179 ] 179
-Persistent_GETS [20 ] 20
+Persistent_GETX [173 ] 173
+Persistent_GETS [18 ] 18
 Persistent_GETS_Last_Token [0 ] 0
-Own_Lock_or_Unlock [199 ] 199
+Own_Lock_or_Unlock [191 ] 191
 
  - Transitions -
-NP  L1_GETS [92 ] 92
-NP  L1_GETX [777 ] 777
+NP  L1_GETS [87 ] 87
+NP  L1_GETX [816 ] 816
 NP  L1_INV [0 ] 0
 NP  Transient_GETX [0 ] 0
 NP  Transient_GETS [0 ] 0
 NP  Writeback_Tokens [0 ] 0
-NP  Writeback_Shared_Data [3 ] 3
-NP  Writeback_All_Tokens [798 ] 798
+NP  Writeback_Shared_Data [7 ] 7
+NP  Writeback_All_Tokens [852 ] 852
 NP  Writeback_Owned [0 ] 0
 NP  Data_Shared [0 ] 0
 NP  Data_Owner [0 ] 0
@@ -637,7 +642,7 @@ NP  Ack [0 ] 0
 NP  Persistent_GETX [0 ] 0
 NP  Persistent_GETS [0 ] 0
 NP  Persistent_GETS_Last_Token [0 ] 0
-NP  Own_Lock_or_Unlock [181 ] 181
+NP  Own_Lock_or_Unlock [168 ] 168
 
 I  L1_GETS [0 ] 0
 I  L1_GETS_Last_Token [0 ] 0
@@ -646,10 +651,10 @@ I  L1_INV [0 ] 0
 I  Transient_GETX [0 ] 0
 I  Transient_GETS [0 ] 0
 I  Transient_GETS_Last_Token [0 ] 0
-I  L2_Replacement [24 ] 24
+I  L2_Replacement [28 ] 28
 I  Writeback_Tokens [0 ] 0
-I  Writeback_Shared_Data [0 ] 0
-I  Writeback_All_Tokens [3 ] 3
+I  Writeback_Shared_Data [1 ] 1
+I  Writeback_All_Tokens [5 ] 5
 I  Writeback_Owned [0 ] 0
 I  Data_Shared [0 ] 0
 I  Data_Owner [0 ] 0
@@ -661,13 +666,13 @@ I  Persistent_GETS_Last_Token [0 ] 0
 I  Own_Lock_or_Unlock [0 ] 0
 
 S  L1_GETS [0 ] 0
-S  L1_GETS_Last_Token [0 ] 0
-S  L1_GETX [1 ] 1
+S  L1_GETS_Last_Token [1 ] 1
+S  L1_GETX [2 ] 2
 S  L1_INV [0 ] 0
 S  Transient_GETX [0 ] 0
 S  Transient_GETS [0 ] 0
 S  Transient_GETS_Last_Token [0 ] 0
-S  L2_Replacement [2 ] 2
+S  L2_Replacement [5 ] 5
 S  Writeback_Tokens [0 ] 0
 S  Writeback_Shared_Data [0 ] 0
 S  Writeback_All_Tokens [0 ] 0
@@ -683,12 +688,12 @@ S  Own_Lock_or_Unlock [0 ] 0
 
 O  L1_GETS [0 ] 0
 O  L1_GETS_Last_Token [0 ] 0
-O  L1_GETX [0 ] 0
+O  L1_GETX [1 ] 1
 O  L1_INV [0 ] 0
 O  Transient_GETX [0 ] 0
 O  Transient_GETS [0 ] 0
 O  Transient_GETS_Last_Token [0 ] 0
-O  L2_Replacement [3 ] 3
+O  L2_Replacement [7 ] 7
 O  Writeback_Tokens [0 ] 0
 O  Writeback_Shared_Data [0 ] 0
 O  Writeback_All_Tokens [0 ] 0
@@ -701,34 +706,34 @@ O  Persistent_GETS [0 ] 0
 O  Persistent_GETS_Last_Token [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 
-M  L1_GETS [3 ] 3
-M  L1_GETX [8 ] 8
+M  L1_GETS [8 ] 8
+M  L1_GETX [7 ] 7
 M  L1_INV [0 ] 0
 M  Transient_GETX [0 ] 0
 M  Transient_GETS [0 ] 0
-M  L2_Replacement [768 ] 768
-M  Persistent_GETX [20 ] 20
+M  L2_Replacement [814 ] 814
+M  Persistent_GETX [26 ] 26
 M  Persistent_GETS [0 ] 0
 M  Own_Lock_or_Unlock [0 ] 0
 
 I_L  L1_GETS [0 ] 0
-I_L  L1_GETX [1 ] 1
+I_L  L1_GETX [0 ] 0
 I_L  L1_INV [0 ] 0
 I_L  Transient_GETX [0 ] 0
 I_L  Transient_GETS [0 ] 0
 I_L  Transient_GETS_Last_Token [0 ] 0
-I_L  L2_Replacement [2 ] 2
+I_L  L2_Replacement [3 ] 3
 I_L  Writeback_Tokens [0 ] 0
 I_L  Writeback_Shared_Data [0 ] 0
-I_L  Writeback_All_Tokens [73 ] 73
+I_L  Writeback_All_Tokens [51 ] 51
 I_L  Writeback_Owned [0 ] 0
 I_L  Data_Shared [0 ] 0
 I_L  Data_Owner [0 ] 0
 I_L  Data_All_Tokens [0 ] 0
 I_L  Ack [0 ] 0
-I_L  Persistent_GETX [159 ] 159
-I_L  Persistent_GETS [20 ] 20
-I_L  Own_Lock_or_Unlock [18 ] 18
+I_L  Persistent_GETX [147 ] 147
+I_L  Persistent_GETS [18 ] 18
+I_L  Own_Lock_or_Unlock [23 ] 23
 
 S_L  L1_GETS [0 ] 0
 S_L  L1_GETS_Last_Token [0 ] 0
@@ -752,93 +757,93 @@ S_L  Persistent_GETS_Last_Token [0 ] 0
 S_L  Own_Lock_or_Unlock [0 ] 0
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1655
-  memory_reads: 869
-  memory_writes: 786
-  memory_refreshes: 558
-  memory_total_request_delays: 1116
-  memory_delays_per_request: 0.67432
-  memory_delays_in_input_queue: 156
-  memory_delays_behind_head_of_bank_queue: 3
-  memory_delays_stalled_at_head_of_bank_queue: 957
-  memory_stalls_for_bank_busy: 245
+  memory_total_requests: 1720
+  memory_reads: 902
+  memory_writes: 818
+  memory_refreshes: 571
+  memory_total_request_delays: 1302
+  memory_delays_per_request: 0.756977
+  memory_delays_in_input_queue: 202
+  memory_delays_behind_head_of_bank_queue: 0
+  memory_delays_stalled_at_head_of_bank_queue: 1100
+  memory_stalls_for_bank_busy: 220
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 76
-  memory_stalls_for_bus: 363
+  memory_stalls_for_arbitration: 97
+  memory_stalls_for_bus: 424
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 197
-  memory_stalls_for_read_read_turnaround: 76
-  accesses_per_bank: 42  44  54  72  110  62  62  43  42  53  38  40  51  47  54  42  48  54  39  56  64  58  51  54  48  46  43  52  46  43  49  48  
+  memory_stalls_for_read_write_turnaround: 268
+  memory_stalls_for_read_read_turnaround: 91
+  accesses_per_bank: 61  42  48  69  122  69  58  56  55  51  54  41  43  47  55  55  46  45  53  50  43  51  55  52  43  56  60  54  49  40  40  57  
 
  --- Directory ---
  - Event Counts -
-GETX [807 ] 807
-GETS [92 ] 92
-Lockdown [199 ] 199
-Unlockdown [199 ] 199
+GETX [828 ] 828
+GETS [87 ] 87
+Lockdown [191 ] 191
+Unlockdown [191 ] 191
 Own_Lock_or_Unlock [0 ] 0
 Own_Lock_or_Unlock_Tokens [0 ] 0
-Data_Owner [3 ] 3
-Data_All_Tokens [790 ] 790
+Data_Owner [7 ] 7
+Data_All_Tokens [825 ] 825
 Ack_Owner [0 ] 0
 Ack_Owner_All_Tokens [76 ] 76
-Tokens [0 ] 0
-Ack_All_Tokens [2 ] 2
+Tokens [2 ] 2
+Ack_All_Tokens [3 ] 3
 Request_Timeout [0 ] 0
-Memory_Data [868 ] 868
-Memory_Ack [786 ] 786
+Memory_Data [902 ] 902
+Memory_Ack [817 ] 817
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
 DMA_WRITE_All_Tokens [0 ] 0
 
  - Transitions -
-O  GETX [773 ] 773
-O  GETS [90 ] 90
-O  Lockdown [5 ] 5
+O  GETX [811 ] 811
+O  GETS [83 ] 83
+O  Lockdown [6 ] 6
 O  Unlockdown [0 ] 0
 O  Own_Lock_or_Unlock [0 ] 0
 O  Own_Lock_or_Unlock_Tokens [0 ] 0
 O  Data_Owner [0 ] 0
 O  Data_All_Tokens [0 ] 0
 O  Tokens [0 ] 0
-O  Ack_All_Tokens [2 ] 2
+O  Ack_All_Tokens [3 ] 3
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 O  DMA_WRITE_All_Tokens [0 ] 0
 
-NO  GETX [2 ] 2
-NO  GETS [2 ] 2
-NO  Lockdown [180 ] 180
+NO  GETX [8 ] 8
+NO  GETS [4 ] 4
+NO  Lockdown [168 ] 168
 NO  Unlockdown [0 ] 0
 NO  Own_Lock_or_Unlock [0 ] 0
 NO  Own_Lock_or_Unlock_Tokens [0 ] 0
-NO  Data_Owner [3 ] 3
-NO  Data_All_Tokens [783 ] 783
+NO  Data_Owner [7 ] 7
+NO  Data_All_Tokens [811 ] 811
 NO  Ack_Owner [0 ] 0
 NO  Ack_Owner_All_Tokens [76 ] 76
-NO  Tokens [0 ] 0
+NO  Tokens [1 ] 1
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
 
-L  GETX [4 ] 4
+L  GETX [0 ] 0
 L  GETS [0 ] 0
 L  Lockdown [0 ] 0
-L  Unlockdown [199 ] 199
+L  Unlockdown [189 ] 189
 L  Own_Lock_or_Unlock [0 ] 0
 L  Own_Lock_or_Unlock_Tokens [0 ] 0
 L  Data_Owner [0 ] 0
-L  Data_All_Tokens [7 ] 7
+L  Data_All_Tokens [14 ] 14
 L  Ack_Owner [0 ] 0
 L  Ack_Owner_All_Tokens [0 ] 0
-L  Tokens [0 ] 0
+L  Tokens [1 ] 1
 L  DMA_READ [0 ] 0
 L  DMA_WRITE [0 ] 0
 L  DMA_WRITE_All_Tokens [0 ] 0
 
-O_W  GETX [0 ] 0
+O_W  GETX [9 ] 9
 O_W  GETS [0 ] 0
-O_W  Lockdown [1 ] 1
+O_W  Lockdown [3 ] 3
 O_W  Unlockdown [0 ] 0
 O_W  Own_Lock_or_Unlock [0 ] 0
 O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -847,16 +852,16 @@ O_W  Data_All_Tokens [0 ] 0
 O_W  Ack_Owner [0 ] 0
 O_W  Tokens [0 ] 0
 O_W  Ack_All_Tokens [0 ] 0
-O_W  Memory_Data [0 ] 0
-O_W  Memory_Ack [785 ] 785
+O_W  Memory_Data [1 ] 1
+O_W  Memory_Ack [815 ] 815
 O_W  DMA_READ [0 ] 0
 O_W  DMA_WRITE [0 ] 0
 O_W  DMA_WRITE_All_Tokens [0 ] 0
 
-L_O_W  GETX [28 ] 28
+L_O_W  GETX [0 ] 0
 L_O_W  GETS [0 ] 0
 L_O_W  Lockdown [0 ] 0
-L_O_W  Unlockdown [0 ] 0
+L_O_W  Unlockdown [2 ] 2
 L_O_W  Own_Lock_or_Unlock [0 ] 0
 L_O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
 L_O_W  Data_Owner [0 ] 0
@@ -864,8 +869,8 @@ L_O_W  Data_All_Tokens [0 ] 0
 L_O_W  Ack_Owner [0 ] 0
 L_O_W  Tokens [0 ] 0
 L_O_W  Ack_All_Tokens [0 ] 0
-L_O_W  Memory_Data [6 ] 6
-L_O_W  Memory_Ack [1 ] 1
+L_O_W  Memory_Data [7 ] 7
+L_O_W  Memory_Ack [2 ] 2
 L_O_W  DMA_READ [0 ] 0
 L_O_W  DMA_WRITE [0 ] 0
 L_O_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -881,7 +886,7 @@ L_NO_W  Data_All_Tokens [0 ] 0
 L_NO_W  Ack_Owner [0 ] 0
 L_NO_W  Tokens [0 ] 0
 L_NO_W  Ack_All_Tokens [0 ] 0
-L_NO_W  Memory_Data [13 ] 13
+L_NO_W  Memory_Data [14 ] 14
 L_NO_W  DMA_READ [0 ] 0
 L_NO_W  DMA_WRITE [0 ] 0
 L_NO_W  DMA_WRITE_All_Tokens [0 ] 0
@@ -922,7 +927,7 @@ DW_L_W  DMA_WRITE_All_Tokens [0 ] 0
 
 NO_W  GETX [0 ] 0
 NO_W  GETS [0 ] 0
-NO_W  Lockdown [13 ] 13
+NO_W  Lockdown [14 ] 14
 NO_W  Unlockdown [0 ] 0
 NO_W  Own_Lock_or_Unlock [0 ] 0
 NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
@@ -931,7 +936,7 @@ NO_W  Data_All_Tokens [0 ] 0
 NO_W  Ack_Owner [0 ] 0
 NO_W  Tokens [0 ] 0
 NO_W  Ack_All_Tokens [0 ] 0
-NO_W  Memory_Data [849 ] 849
+NO_W  Memory_Data [880 ] 880
 NO_W  DMA_READ [0 ] 0
 NO_W  DMA_WRITE [0 ] 0
 NO_W  DMA_WRITE_All_Tokens [0 ] 0
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 2c983b9e6..5d4c3c605 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:27:42
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:27:50
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 10:41:36
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:45:27
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 267511 because Ruby Tester completed
+Exiting @ tick 273851 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index cfbb882fc..a749dd61b 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -1,10 +1,10 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 213120                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
-host_tick_rate                                1709740                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210052                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
+host_tick_rate                                 516678                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.000268                       # Number of seconds simulated
-sim_ticks                                      267511                       # Number of ticks simulated
+sim_seconds                                  0.000274                       # Number of seconds simulated
+sim_ticks                                      273851                       # Number of ticks simulated
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index dda1ea910..24f058dce 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
@@ -1,29 +1,19 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
 children=directory memBuffer probeFilter
 buffer_size=0
 directory=system.dir_cntrl0.directory
-full_bit_dir_enabled=false
 memBuffer=system.dir_cntrl0.memBuffer
 memory_controller_latency=2
 number_of_TBEs=256
@@ -72,18 +62,17 @@ start_index_bit=6
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
-children=L2cacheMemory
-L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache
-L1IcacheMemory=system.ruby.cpu_ruby_ports.icache
+children=L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.sequencer.dcache
+L1IcacheMemory=system.l1_cntrl0.sequencer.icache
 L2cacheMemory=system.l1_cntrl0.L2cacheMemory
 buffer_size=0
 cache_response_latency=10
 issue_latency=2
-l2_cache_hit_latency=10
 no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
@@ -95,45 +84,20 @@ replacement_policy=PSEUDO_LRU
 size=512
 start_index_bit=6
 
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
-
-[system.ruby]
-type=RubySystem
-children=cpu_ruby_ports network profiler tracer
-block_size_bytes=64
-clock=1
-mem_size=134217728
-network=system.ruby.network
-no_mem_vec=false
-profiler=system.ruby.profiler
-random_seed=1234
-randomization=true
-stats_filename=ruby.stats
-tracer=system.ruby.tracer
-
-[system.ruby.cpu_ruby_ports]
+[system.l1_cntrl0.sequencer]
 type=RubySequencer
 children=dcache icache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
+dcache=system.l1_cntrl0.sequencer.dcache
 deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.icache
+icache=system.l1_cntrl0.sequencer.icache
 max_outstanding_requests=16
 physmem=system.physmem
 using_ruby_tester=true
 version=0
 physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
+port=root.cpuPort[0]
 
-[system.ruby.cpu_ruby_ports.dcache]
+[system.l1_cntrl0.sequencer.dcache]
 type=RubyCache
 assoc=2
 latency=2
@@ -141,7 +105,7 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
-[system.ruby.cpu_ruby_ports.icache]
+[system.l1_cntrl0.sequencer.icache]
 type=RubyCache
 assoc=2
 latency=2
@@ -149,6 +113,39 @@ replacement_policy=PSEUDO_LRU
 size=256
 start_index_bit=6
 
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=debug network profiler tracer
+block_size_bytes=64
+clock=1
+debug=system.ruby.debug
+mem_size=134217728
+network=system.ruby.network
+no_mem_vec=false
+profiler=system.ruby.profiler
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+tracer=system.ruby.tracer
+
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
+
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
@@ -163,9 +160,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
 num_int_nodes=3
 print_config=false
 
@@ -211,10 +208,3 @@ num_of_sequencers=1
 type=RubyTracer
 warmup_length=100000
 
-[system.tester]
-type=RubyTester
-checks_to_complete=100
-deadlock_threshold=50000
-wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
-
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 73a0cf1f9..57c443be3 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:21
+Real time: Aug/05/2010 14:46:32
 
 Profiler Stats
 --------------
@@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.36
-Virtual_time_in_minutes: 0.006
-Virtual_time_in_hours:   0.0001
-Virtual_time_in_days:    4.16667e-06
+Virtual_time_in_seconds: 0.69
+Virtual_time_in_minutes: 0.0115
+Virtual_time_in_hours:   0.000191667
+Virtual_time_in_days:    7.98611e-06
 
-Ruby_current_time: 210961
+Ruby_current_time: 213851
 Ruby_start_time: 0
-Ruby_cycles: 210961
+Ruby_cycles: 213851
 
-mbytes_resident: 33.418
-mbytes_total: 207.586
-resident_ratio: 0.16104
+mbytes_resident: 31.293
+mbytes_total: 31.3008
+resident_ratio: 1
 
-ruby_cycles_executed: [ 210962 ]
+ruby_cycles_executed: [ 213852 ]
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -65,17 +65,17 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016 | standard deviation: 1.14461 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 71 891 ]
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
-miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
-miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
-miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
+miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
+miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -85,14 +85,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average:
 miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-imcomplete_dir_Times: 859
-miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
-miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average:     2 | standard deviation: 0.816497 | 0 1 2 1 ]
-miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
-miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
-miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
-miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
+imcomplete_dir_Times: 854
+miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average:   2.5 | standard deviation: 1 | 0 0 1 1 ]
+miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average:    50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average:     3 | standard deviation: 0.707107 | 0 0 1 3 1 ]
+miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ]
+miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
 
 All Non-Zero Cycle SW Prefetch Requests
 ------------------------------------
@@ -124,127 +125,126 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9781
-page_faults: 0
+page_reclaims: 6929
+page_faults: 1882
 swaps: 0
-block_inputs: 16
+block_inputs: 0
 block_outputs: 0
 
 Network Stats
 -------------
 
-total_msg_count_Request_Control: 2577 20616
-total_msg_count_Response_Data: 2577 185544
-total_msg_count_Writeback_Data: 2301 165672
-total_msg_count_Writeback_Control: 5367 42936
-total_msg_count_Unblock_Control: 2574 20592
-total_msgs: 15396 total_bytes: 435360
+total_msg_count_Request_Control: 2568 20544
+total_msg_count_Response_Data: 2562 184464
+total_msg_count_Writeback_Data: 2281 164232
+total_msg_count_Writeback_Control: 5351 42808
+total_msg_count_Unblock_Control: 2559 20472
+total_msgs: 15321 total_bytes: 432520
 
 switch_0_inlinks: 2
 switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.138684
-  links_utilized_percent_switch_0_link_0: 0.0508566 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_0_link_1: 0.226511 bw: 160000 base_latency: 1
+links_utilized_percent_switch_0: 0.13593
+  links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_0_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
 
 switch_1_inlinks: 2
 switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.130027
-  links_utilized_percent_switch_1_link_0: 0.0566278 bw: 640000 base_latency: 1
-  links_utilized_percent_switch_1_link_1: 0.203426 bw: 160000 base_latency: 1
+links_utilized_percent_switch_1: 0.127495
+  links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_1_link_0_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_1_link_1_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1
 
 switch_2_inlinks: 2
 switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.214969
-  links_utilized_percent_switch_2_link_0: 0.203426 bw: 160000 base_latency: 1
-  links_utilized_percent_switch_2_link_1: 0.226511 bw: 160000 base_latency: 1
+links_utilized_percent_switch_2: 0.210637
+  links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1
 
-  outgoing_messages_switch_2_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1
-  outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.icache
-  system.ruby.cpu_ruby_ports.icache_total_misses: 52
-  system.ruby.cpu_ruby_ports.icache_total_demand_misses: 52
-  system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 57
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 57
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.icache_request_type_IFETCH:   100%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   100%
 
-  system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode:   52    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   57    100%
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 852
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 852
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.dcache
+  system.l1_cntrl0.sequencer.dcache_total_misses: 840
+  system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840
+  system.l1_cntrl0.sequencer.dcache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   5.28169%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   94.7183%
+  system.l1_cntrl0.sequencer.dcache_request_type_LD:   4.28571%
+  system.l1_cntrl0.sequencer.dcache_request_type_ST:   95.7143%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   852    100%
+  system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode:   840    100%
 
 Cache Stats: system.l1_cntrl0.L2cacheMemory
-  system.l1_cntrl0.L2cacheMemory_total_misses: 904
-  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 904
+  system.l1_cntrl0.L2cacheMemory_total_misses: 856
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856
   system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
   system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
 
-  system.l1_cntrl0.L2cacheMemory_request_type_LD:   4.97788%
-  system.l1_cntrl0.L2cacheMemory_request_type_ST:   89.2699%
-  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   5.75221%
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   4.20561%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   89.486%
+  system.l1_cntrl0.L2cacheMemory_request_type_IFETCH:   6.30841%
 
-  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   904    100%
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode:   856    100%
 
  --- L1Cache ---
  - Event Counts -
-Load [48 ] 48
-Ifetch [53 ] 53
-Store [888 ] 888
-L2_Replacement [854 ] 854
-L1_to_L2 [16074 ] 16074
-Trigger_L2_to_L1D [39 ] 39
-Trigger_L2_to_L1I [4 ] 4
-Complete_L2_to_L1 [43 ] 43
+Load [41 ] 41
+Ifetch [106 ] 106
+Store [906 ] 906
+L2_Replacement [849 ] 849
+L1_to_L2 [303164 ] 303164
+Trigger_L2_to_L1D [38 ] 38
+Trigger_L2_to_L1I [3 ] 3
+Complete_L2_to_L1 [41 ] 41
 Other_GETX [0 ] 0
 Other_GETS [0 ] 0
 Merged_GETS [0 ] 0
 Other_GETS_No_Mig [0 ] 0
-NC_DMA_GETS [0 ] 0
 Invalidate [0 ] 0
 Ack [0 ] 0
 Shared_Ack [0 ] 0
 Data [0 ] 0
 Shared_Data [0 ] 0
-Exclusive_Data [859 ] 859
-Writeback_Ack [852 ] 852
+Exclusive_Data [854 ] 854
+Writeback_Ack [848 ] 848
 Writeback_Nack [0 ] 0
 All_acks [0 ] 0
-All_acks_no_sharers [859 ] 859
+All_acks_no_sharers [853 ] 853
 
  - Transitions -
-I  Load [44 ] 44
-I  Ifetch [48 ] 48
-I  Store [769 ] 769
+I  Load [36 ] 36
+I  Ifetch [54 ] 54
+I  Store [766 ] 766
 I  L2_Replacement [0 ] 0
 I  L1_to_L2 [0 ] 0
 I  Trigger_L2_to_L1D [0 ] 0
@@ -252,7 +252,6 @@ I  Trigger_L2_to_L1I [0 ] 0
 I  Other_GETX [0 ] 0
 I  Other_GETS [0 ] 0
 I  Other_GETS_No_Mig [0 ] 0
-I  NC_DMA_GETS [0 ] 0
 I  Invalidate [0 ] 0
 
 S  Load [0 ] 0
@@ -265,7 +264,6 @@ S  Trigger_L2_to_L1I [0 ] 0
 S  Other_GETX [0 ] 0
 S  Other_GETS [0 ] 0
 S  Other_GETS_No_Mig [0 ] 0
-S  NC_DMA_GETS [0 ] 0
 S  Invalidate [0 ] 0
 
 O  Load [0 ] 0
@@ -279,50 +277,46 @@ O  Other_GETX [0 ] 0
 O  Other_GETS [0 ] 0
 O  Merged_GETS [0 ] 0
 O  Other_GETS_No_Mig [0 ] 0
-O  NC_DMA_GETS [0 ] 0
 O  Invalidate [0 ] 0
 
 M  Load [0 ] 0
-M  Ifetch [0 ] 0
-M  Store [3 ] 3
-M  L2_Replacement [85 ] 85
-M  L1_to_L2 [95 ] 95
-M  Trigger_L2_to_L1D [9 ] 9
+M  Ifetch [1 ] 1
+M  Store [1 ] 1
+M  L2_Replacement [87 ] 87
+M  L1_to_L2 [88 ] 88
+M  Trigger_L2_to_L1D [1 ] 1
 M  Trigger_L2_to_L1I [0 ] 0
 M  Other_GETX [0 ] 0
 M  Other_GETS [0 ] 0
 M  Merged_GETS [0 ] 0
 M  Other_GETS_No_Mig [0 ] 0
-M  NC_DMA_GETS [0 ] 0
 M  Invalidate [0 ] 0
 
-MM  Load [4 ] 4
+MM  Load [5 ] 5
 MM  Ifetch [4 ] 4
-MM  Store [92 ] 92
-MM  L2_Replacement [769 ] 769
+MM  Store [82 ] 82
+MM  L2_Replacement [762 ] 762
 MM  L1_to_L2 [804 ] 804
-MM  Trigger_L2_to_L1D [30 ] 30
-MM  Trigger_L2_to_L1I [4 ] 4
+MM  Trigger_L2_to_L1D [37 ] 37
+MM  Trigger_L2_to_L1I [3 ] 3
 MM  Other_GETX [0 ] 0
 MM  Other_GETS [0 ] 0
 MM  Merged_GETS [0 ] 0
 MM  Other_GETS_No_Mig [0 ] 0
-MM  NC_DMA_GETS [0 ] 0
 MM  Invalidate [0 ] 0
 
 IM  Load [0 ] 0
 IM  Ifetch [0 ] 0
 IM  Store [0 ] 0
 IM  L2_Replacement [0 ] 0
-IM  L1_to_L2 [9842 ] 9842
+IM  L1_to_L2 [275518 ] 275518
 IM  Other_GETX [0 ] 0
 IM  Other_GETS [0 ] 0
 IM  Other_GETS_No_Mig [0 ] 0
-IM  NC_DMA_GETS [0 ] 0
 IM  Invalidate [0 ] 0
 IM  Ack [0 ] 0
 IM  Data [0 ] 0
-IM  Exclusive_Data [767 ] 767
+IM  Exclusive_Data [764 ] 764
 
 SM  Load [0 ] 0
 SM  Ifetch [0 ] 0
@@ -332,11 +326,9 @@ SM  L1_to_L2 [0 ] 0
 SM  Other_GETX [0 ] 0
 SM  Other_GETS [0 ] 0
 SM  Other_GETS_No_Mig [0 ] 0
-SM  NC_DMA_GETS [0 ] 0
 SM  Invalidate [0 ] 0
 SM  Ack [0 ] 0
 SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
 
 OM  Load [0 ] 0
 OM  Ifetch [0 ] 0
@@ -347,7 +339,6 @@ OM  Other_GETX [0 ] 0
 OM  Other_GETS [0 ] 0
 OM  Merged_GETS [0 ] 0
 OM  Other_GETS_No_Mig [0 ] 0
-OM  NC_DMA_GETS [0 ] 0
 OM  Invalidate [0 ] 0
 OM  Ack [0 ] 0
 OM  All_acks [0 ] 0
@@ -363,35 +354,34 @@ ISM  All_acks_no_sharers [0 ] 0
 
 M_W  Load [0 ] 0
 M_W  Ifetch [0 ] 0
-M_W  Store [1 ] 1
+M_W  Store [0 ] 0
 M_W  L2_Replacement [0 ] 0
-M_W  L1_to_L2 [310 ] 310
+M_W  L1_to_L2 [483 ] 483
 M_W  Ack [0 ] 0
-M_W  All_acks_no_sharers [91 ] 91
+M_W  All_acks_no_sharers [89 ] 89
 
 MM_W  Load [0 ] 0
 MM_W  Ifetch [0 ] 0
-MM_W  Store [0 ] 0
+MM_W  Store [1 ] 1
 MM_W  L2_Replacement [0 ] 0
-MM_W  L1_to_L2 [4284 ] 4284
+MM_W  L1_to_L2 [10887 ] 10887
 MM_W  Ack [0 ] 0
-MM_W  All_acks_no_sharers [768 ] 768
+MM_W  All_acks_no_sharers [764 ] 764
 
 IS  Load [0 ] 0
 IS  Ifetch [0 ] 0
 IS  Store [0 ] 0
 IS  L2_Replacement [0 ] 0
-IS  L1_to_L2 [621 ] 621
+IS  L1_to_L2 [14644 ] 14644
 IS  Other_GETX [0 ] 0
 IS  Other_GETS [0 ] 0
 IS  Other_GETS_No_Mig [0 ] 0
-IS  NC_DMA_GETS [0 ] 0
 IS  Invalidate [0 ] 0
 IS  Ack [0 ] 0
 IS  Shared_Ack [0 ] 0
 IS  Data [0 ] 0
 IS  Shared_Data [0 ] 0
-IS  Exclusive_Data [92 ] 92
+IS  Exclusive_Data [90 ] 90
 
 SS  Load [0 ] 0
 SS  Ifetch [0 ] 0
@@ -412,22 +402,20 @@ OI  Other_GETX [0 ] 0
 OI  Other_GETS [0 ] 0
 OI  Merged_GETS [0 ] 0
 OI  Other_GETS_No_Mig [0 ] 0
-OI  NC_DMA_GETS [0 ] 0
 OI  Invalidate [0 ] 0
 OI  Writeback_Ack [0 ] 0
 
 MI  Load [0 ] 0
-MI  Ifetch [1 ] 1
-MI  Store [0 ] 0
+MI  Ifetch [36 ] 36
+MI  Store [5 ] 5
 MI  L2_Replacement [0 ] 0
 MI  L1_to_L2 [0 ] 0
 MI  Other_GETX [0 ] 0
 MI  Other_GETS [0 ] 0
 MI  Merged_GETS [0 ] 0
 MI  Other_GETS_No_Mig [0 ] 0
-MI  NC_DMA_GETS [0 ] 0
 MI  Invalidate [0 ] 0
-MI  Writeback_Ack [852 ] 852
+MI  Writeback_Ack [848 ] 848
 
 II  Load [0 ] 0
 II  Ifetch [0 ] 0
@@ -437,7 +425,6 @@ II  L1_to_L2 [0 ] 0
 II  Other_GETX [0 ] 0
 II  Other_GETS [0 ] 0
 II  Other_GETS_No_Mig [0 ] 0
-II  NC_DMA_GETS [0 ] 0
 II  Invalidate [0 ] 0
 II  Writeback_Ack [0 ] 0
 II  Writeback_Nack [0 ] 0
@@ -452,7 +439,6 @@ IT  Other_GETX [0 ] 0
 IT  Other_GETS [0 ] 0
 IT  Merged_GETS [0 ] 0
 IT  Other_GETS_No_Mig [0 ] 0
-IT  NC_DMA_GETS [0 ] 0
 IT  Invalidate [0 ] 0
 
 ST  Load [0 ] 0
@@ -465,7 +451,6 @@ ST  Other_GETX [0 ] 0
 ST  Other_GETS [0 ] 0
 ST  Merged_GETS [0 ] 0
 ST  Other_GETS_No_Mig [0 ] 0
-ST  NC_DMA_GETS [0 ] 0
 ST  Invalidate [0 ] 0
 
 OT  Load [0 ] 0
@@ -478,33 +463,30 @@ OT  Other_GETX [0 ] 0
 OT  Other_GETS [0 ] 0
 OT  Merged_GETS [0 ] 0
 OT  Other_GETS_No_Mig [0 ] 0
-OT  NC_DMA_GETS [0 ] 0
 OT  Invalidate [0 ] 0
 
 MT  Load [0 ] 0
 MT  Ifetch [0 ] 0
-MT  Store [2 ] 2
+MT  Store [10 ] 10
 MT  L2_Replacement [0 ] 0
-MT  L1_to_L2 [39 ] 39
-MT  Complete_L2_to_L1 [9 ] 9
+MT  L1_to_L2 [154 ] 154
+MT  Complete_L2_to_L1 [1 ] 1
 MT  Other_GETX [0 ] 0
 MT  Other_GETS [0 ] 0
 MT  Merged_GETS [0 ] 0
 MT  Other_GETS_No_Mig [0 ] 0
-MT  NC_DMA_GETS [0 ] 0
 MT  Invalidate [0 ] 0
 
 MMT  Load [0 ] 0
-MMT  Ifetch [0 ] 0
-MMT  Store [21 ] 21
+MMT  Ifetch [11 ] 11
+MMT  Store [41 ] 41
 MMT  L2_Replacement [0 ] 0
-MMT  L1_to_L2 [79 ] 79
-MMT  Complete_L2_to_L1 [34 ] 34
+MMT  L1_to_L2 [586 ] 586
+MMT  Complete_L2_to_L1 [40 ] 40
 MMT  Other_GETX [0 ] 0
 MMT  Other_GETS [0 ] 0
 MMT  Merged_GETS [0 ] 0
 MMT  Other_GETS_No_Mig [0 ] 0
-MMT  NC_DMA_GETS [0 ] 0
 MMT  Invalidate [0 ] 0
 
 Cache Stats: system.dir_cntrl0.probeFilter
@@ -516,42 +498,42 @@ Cache Stats: system.dir_cntrl0.probeFilter
 
 
 Memory controller: system.dir_cntrl0.memBuffer:
-  memory_total_requests: 1626
-  memory_reads: 859
-  memory_writes: 767
-  memory_refreshes: 440
-  memory_total_request_delays: 1086
-  memory_delays_per_request: 0.667897
-  memory_delays_in_input_queue: 156
-  memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 930
-  memory_stalls_for_bank_busy: 238
+  memory_total_requests: 1616
+  memory_reads: 856
+  memory_writes: 760
+  memory_refreshes: 446
+  memory_total_request_delays: 1108
+  memory_delays_per_request: 0.685644
+  memory_delays_in_input_queue: 161
+  memory_delays_behind_head_of_bank_queue: 2
+  memory_delays_stalled_at_head_of_bank_queue: 945
+  memory_stalls_for_bank_busy: 192
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 61
-  memory_stalls_for_bus: 358
+  memory_stalls_for_arbitration: 83
+  memory_stalls_for_bus: 395
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 169
-  memory_stalls_for_read_read_turnaround: 104
-  accesses_per_bank: 41  42  40  76  63  66  54  43  49  56  52  46  53  60  61  57  50  44  44  42  48  49  42  47  53  52  49  52  50  47  41  57  
+  memory_stalls_for_read_write_turnaround: 154
+  memory_stalls_for_read_read_turnaround: 121
+  accesses_per_bank: 34  44  48  84  67  62  61  53  41  30  54  49  46  47  41  52  49  35  67  45  67  44  44  46  55  52  53  50  44  47  56  49  
 
  --- Directory ---
  - Event Counts -
-GETX [767 ] 767
-GETS [93 ] 93
-PUT [907 ] 907
+GETX [770 ] 770
+GETS [91 ] 91
+PUT [909 ] 909
 Unblock [0 ] 0
 UnblockS [0 ] 0
-UnblockM [856 ] 856
+UnblockM [853 ] 853
 Writeback_Clean [0 ] 0
 Writeback_Dirty [0 ] 0
-Writeback_Exclusive_Clean [85 ] 85
-Writeback_Exclusive_Dirty [767 ] 767
+Writeback_Exclusive_Clean [86 ] 86
+Writeback_Exclusive_Dirty [760 ] 760
 Pf_Replacement [0 ] 0
 DMA_READ [0 ] 0
 DMA_WRITE [0 ] 0
-Memory_Data [859 ] 859
-Memory_Ack [767 ] 767
+Memory_Data [854 ] 854
+Memory_Ack [760 ] 760
 Ack [0 ] 0
 Shared_Ack [0 ] 0
 Shared_Data [0 ] 0
@@ -572,7 +554,7 @@ NX  DMA_WRITE [0 ] 0
 
 NO  GETX [0 ] 0
 NO  GETS [0 ] 0
-NO  PUT [852 ] 852
+NO  PUT [849 ] 849
 NO  Pf_Replacement [0 ] 0
 NO  DMA_READ [0 ] 0
 NO  DMA_WRITE [0 ] 0
@@ -591,8 +573,8 @@ O  Pf_Replacement [0 ] 0
 O  DMA_READ [0 ] 0
 O  DMA_WRITE [0 ] 0
 
-E  GETX [767 ] 767
-E  GETS [92 ] 92
+E  GETX [766 ] 766
+E  GETS [90 ] 90
 E  PUT [0 ] 0
 E  DMA_READ [0 ] 0
 E  DMA_WRITE [0 ] 0
@@ -629,9 +611,9 @@ NO_R  All_acks_and_data_no_sharers [0 ] 0
 
 NO_B  GETX [0 ] 0
 NO_B  GETS [0 ] 0
-NO_B  PUT [55 ] 55
+NO_B  PUT [60 ] 60
 NO_B  UnblockS [0 ] 0
-NO_B  UnblockM [856 ] 856
+NO_B  UnblockM [853 ] 853
 NO_B  Pf_Replacement [0 ] 0
 NO_B  DMA_READ [0 ] 0
 NO_B  DMA_WRITE [0 ] 0
@@ -642,8 +624,6 @@ NO_B_X  PUT [0 ] 0
 NO_B_X  UnblockS [0 ] 0
 NO_B_X  UnblockM [0 ] 0
 NO_B_X  Pf_Replacement [0 ] 0
-NO_B_X  DMA_READ [0 ] 0
-NO_B_X  DMA_WRITE [0 ] 0
 
 NO_B_S  GETX [0 ] 0
 NO_B_S  GETS [0 ] 0
@@ -667,7 +647,6 @@ O_B  GETX [0 ] 0
 O_B  GETS [0 ] 0
 O_B  PUT [0 ] 0
 O_B  UnblockS [0 ] 0
-O_B  UnblockM [0 ] 0
 O_B  Pf_Replacement [0 ] 0
 O_B  DMA_READ [0 ] 0
 O_B  DMA_WRITE [0 ] 0
@@ -680,7 +659,7 @@ NO_B_W  UnblockM [0 ] 0
 NO_B_W  Pf_Replacement [0 ] 0
 NO_B_W  DMA_READ [0 ] 0
 NO_B_W  DMA_WRITE [0 ] 0
-NO_B_W  Memory_Data [859 ] 859
+NO_B_W  Memory_Data [854 ] 854
 
 O_B_W  GETX [0 ] 0
 O_B_W  GETS [0 ] 0
@@ -790,14 +769,14 @@ O_DR_B  Shared_Ack [0 ] 0
 O_DR_B  All_acks_and_owner_data [0 ] 0
 O_DR_B  All_acks_and_data_no_sharers [0 ] 0
 
-WB  GETX [0 ] 0
-WB  GETS [0 ] 0
+WB  GETX [2 ] 2
+WB  GETS [1 ] 1
 WB  PUT [0 ] 0
 WB  Unblock [0 ] 0
 WB  Writeback_Clean [0 ] 0
 WB  Writeback_Dirty [0 ] 0
-WB  Writeback_Exclusive_Clean [85 ] 85
-WB  Writeback_Exclusive_Dirty [767 ] 767
+WB  Writeback_Exclusive_Clean [86 ] 86
+WB  Writeback_Exclusive_Dirty [760 ] 760
 WB  Pf_Replacement [0 ] 0
 WB  DMA_READ [0 ] 0
 WB  DMA_WRITE [0 ] 0
@@ -810,8 +789,8 @@ WB_O_W  DMA_READ [0 ] 0
 WB_O_W  DMA_WRITE [0 ] 0
 WB_O_W  Memory_Ack [0 ] 0
 
-WB_E_W  GETX [0 ] 0
-WB_E_W  GETS [1 ] 1
+WB_E_W  GETX [2 ] 2
+WB_E_W  GETS [0 ] 0
 WB_E_W  PUT [0 ] 0
 WB_E_W  Pf_Replacement [0 ] 0
 WB_E_W  DMA_READ [0 ] 0
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index a9851a25f..03174a5ad 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:12:45
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:21
-M5 executing on SC2B0617
+M5 compiled Aug  5 2010 14:43:33
+M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates
+M5 started Aug  5 2010 14:46:32
+M5 executing on svvint09
 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 210961 because Ruby Tester completed
+Exiting @ tick 213851 because Ruby Tester completed
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index aa22cbeca..6827d9d11 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -1,10 +1,10 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 212572                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
-host_tick_rate                                1840766                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209796                       # Number of bytes of host memory used
+host_seconds                                     0.44                       # Real time elapsed on the host
+host_tick_rate                                 485996                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-sim_seconds                                  0.000211                       # Number of seconds simulated
-sim_ticks                                      210961                       # Number of ticks simulated
+sim_seconds                                  0.000214                       # Number of seconds simulated
+sim_ticks                                      213851                       # Number of ticks simulated
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 247e64cce..2e46bddba 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
@@ -1,22 +1,13 @@
 [root]
 type=Root
 children=system
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
+dummy=0
 
 [system]
 type=System
-children=dir_cntrl0 l1_cntrl0 physmem ruby tester
+children=dir_cntrl0 l1_cntrl0 physmem ruby
 mem_mode=timing
 physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [system.dir_cntrl0]
 type=Directory_Controller
@@ -61,16 +52,38 @@ version=0
 
 [system.l1_cntrl0]
 type=L1Cache_Controller
+children=sequencer
 buffer_size=0
-cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cacheMemory=system.l1_cntrl0.sequencer.icache
 cache_response_latency=12
 issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
-sequencer=system.ruby.cpu_ruby_ports
+sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
 
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+children=icache
+dcache=system.l1_cntrl0.sequencer.icache
+deadlock_threshold=500000
+icache=system.l1_cntrl0.sequencer.icache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=true
+version=0
+physMemPort=system.physmem.port[0]
+port=root.cpuPort[0]
+
+[system.l1_cntrl0.sequencer.icache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -79,13 +92,14 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.cpu_ruby_ports.physMemPort
+port=system.l1_cntrl0.sequencer.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=cpu_ruby_ports network profiler tracer
+children=debug network profiler tracer
 block_size_bytes=64
 clock=1
+debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
 no_mem_vec=false
@@ -95,27 +109,13 @@ randomization=true
 stats_filename=ruby.stats
 tracer=system.ruby.tracer
 
-[system.ruby.cpu_ruby_ports]
-type=RubySequencer
-children=dcache
-access_phys_mem=true
-dcache=system.ruby.cpu_ruby_ports.dcache
-deadlock_threshold=500000
-icache=system.ruby.cpu_ruby_ports.dcache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=true
-version=0
-physMemPort=system.physmem.port[0]
-port=system.tester.cpuPort[0]
-
-[system.ruby.cpu_ruby_ports.dcache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-start_index_bit=6
+[system.ruby.debug]
+type=RubyDebug
+filter_string=none
+output_filename=none
+protocol_trace=false
+start_time=1
+verbosity_string=none
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -131,9 +131,9 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
-description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
+name=Crossbar
 num_int_nodes=3
 print_config=false
 
@@ -179,10 +179,3 @@ num_of_sequencers=1
 type=RubyTracer
 warmup_length=100000
 
-[system.tester]
-type=RubyTester
-checks_to_complete=100
-deadlock_threshold=50000
-wakeup_frequency=10
-cpuPort=system.ruby.cpu_ruby_ports.port[0]
-
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index e0cb89c71..4b8c316dc 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -13,7 +13,7 @@ RubySystem config:
 Network Configuration
 ---------------------
 network: SIMPLE_NETWORK
-topology: 
+topology: Crossbar
 
 virtual_net_0: active, ordered
 virtual_net_1: active, ordered
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/06/2011 20:42:47
+Real time: Aug/05/2010 10:10:57
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.33
-Virtual_time_in_minutes: 0.0055
-Virtual_time_in_hours:   9.16667e-05
-Virtual_time_in_days:    3.81944e-06
+Virtual_time_in_seconds: 0.29
+Virtual_time_in_minutes: 0.00483333
+Virtual_time_in_hours:   8.05556e-05
+Virtual_time_in_days:    3.35648e-06
 
 Ruby_current_time: 281031
 Ruby_start_time: 0
 Ruby_cycles: 281031
 
-mbytes_resident: 33.3125
-mbytes_total: 207.496
-resident_ratio: 0.160583
+mbytes_resident: 30.9531
+mbytes_total: 203.703
+resident_ratio: 0.15199
 
 ruby_cycles_executed: [ 281032 ]
 
@@ -122,7 +122,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9752
+page_reclaims: 9003
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -170,18 +170,18 @@ links_utilized_percent_switch_2: 0.169999
   outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1
 
-Cache Stats: system.ruby.cpu_ruby_ports.dcache
-  system.ruby.cpu_ruby_ports.dcache_total_misses: 957
-  system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 957
-  system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
-  system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
+Cache Stats: system.l1_cntrl0.sequencer.icache
+  system.l1_cntrl0.sequencer.icache_total_misses: 957
+  system.l1_cntrl0.sequencer.icache_total_demand_misses: 957
+  system.l1_cntrl0.sequencer.icache_total_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0
+  system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0
 
-  system.ruby.cpu_ruby_ports.dcache_request_type_LD:   4.91118%
-  system.ruby.cpu_ruby_ports.dcache_request_type_ST:   89.7597%
-  system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH:   5.32915%
+  system.l1_cntrl0.sequencer.icache_request_type_LD:   4.91118%
+  system.l1_cntrl0.sequencer.icache_request_type_ST:   89.7597%
+  system.l1_cntrl0.sequencer.icache_request_type_IFETCH:   5.32915%
 
-  system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode:   957    100%
+  system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode:   957    100%
 
  --- L1Cache ---
  - Event Counts -
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 29fe13e0e..566ba5c1a 100755
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout
+Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 20:42:22
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:42:46
+M5 compiled Aug  4 2010 17:29:21
+M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip
+M5 started Aug  5 2010 10:10:57
 M5 executing on SC2B0617
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 5bab9082f..104ae3de6 100644
--- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 212480                       # Number of bytes of host memory used
+host_mem_usage                                 208596                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
-host_tick_rate                                3252147                       # Simulator tick rate (ticks/s)
+host_tick_rate                                3195386                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000281                       # Number of seconds simulated
 sim_ticks                                      281031                       # Number of ticks simulated
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index e6d4ef8de..84f87c01b 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -3,24 +3,17 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/proj/radl_extra/users/bbeckman/noc_m5/configs/boot/netperf-server.rcS
+readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [drivesys.bridge]
 type=Bridge
@@ -98,7 +91,7 @@ table_size=65536
 
 [drivesys.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.disk2]
@@ -118,7 +111,7 @@ table_size=65536
 
 [drivesys.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [drivesys.intrctrl]
@@ -182,7 +175,7 @@ system=drivesys
 
 [drivesys.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.terminal]
@@ -644,9 +637,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=drivesys.disk0 drivesys.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
@@ -715,33 +706,24 @@ int1=drivesys.tsunami.ethernet.interface
 [root]
 type=Root
 children=drivesys etherdump etherlink testsys
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
 
 [testsys]
 type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=1
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
+console=/chips/pd/randd/dist/binaries/console
 init_param=0
-kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
-pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/proj/radl_extra/users/bbeckman/noc_m5/configs/boot/netperf-stream-client.rcS
+readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
 
 [testsys.bridge]
 type=Bridge
@@ -819,7 +801,7 @@ table_size=65536
 
 [testsys.disk0.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.disk2]
@@ -839,7 +821,7 @@ table_size=65536
 
 [testsys.disk2.image.child]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
 read_only=true
 
 [testsys.intrctrl]
@@ -903,7 +885,7 @@ system=testsys
 
 [testsys.simple_disk.disk]
 type=RawDiskImage
-image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.terminal]
@@ -1365,9 +1347,7 @@ SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
 config_latency=20000
-ctrl_offset=0
 disks=testsys.disk0 testsys.disk2
-io_shift=0
 max_backoff_delay=10000000
 min_backoff_delay=4000
 pci_bus=0
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index d5294a000..c18ca3505 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
@@ -2,10 +2,6 @@ warn: Sockets disabled, not accepting terminal connections
 For more information see: http://www.m5sim.org/warn/8742226b
 warn: Sockets disabled, not accepting gdb connections
 For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
-warn: Prefetch instrutions is Alpha do not do anything
-For more information see: http://www.m5sim.org/warn/3e0eccba
 warn: Obsolete M5 ivlb instruction encountered.
 For more information see: http://www.m5sim.org/warn/fcbd217d
 hack: be nice to actually delete the event here
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 6dfccbecc..2dcdfae87 100755
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
 M5 Simulator System
 
 Copyright (c) 2001-2008
@@ -5,13 +7,13 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Feb  6 2011 15:18:06
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb  6 2011 20:45:27
-M5 executing on SC2B0617
+M5 compiled Nov  2 2010 23:00:12
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov  2 2010 23:11:17
+M5 executing on aus-bc2-b15
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
-info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4300236804024 because checkpoint
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 5e2d23c72..9fb1ef54c 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -93,24 +93,8 @@ drivesys.cpu.kern.syscall::150                      1      4.55%    100.00% # nu
 drivesys.cpu.kern.syscall::total                   22                       # number of syscalls executed
 drivesys.cpu.not_idle_fraction               0.000010                       # Percentage of non-idle cycles
 drivesys.cpu.numCycles                   199571362884                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.num_busy_cycles             1954747.881971                       # Number of busy cycles
-drivesys.cpu.num_conditional_control_insts       161093                       # number of instructions that are conditional controls
-drivesys.cpu.num_fp_alu_accesses                 1278                       # Number of float alu accesses
-drivesys.cpu.num_fp_insts                        1278                       # number of float instructions
-drivesys.cpu.num_fp_register_reads                694                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes               698                       # number of times the floating registers were written
-drivesys.cpu.num_func_calls                    121650                       # number of times a function call or return occured
-drivesys.cpu.num_idle_cycles             199569408136.118042                       # Number of idle cycles
 drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
-drivesys.cpu.num_int_alu_accesses             1889973                       # Number of integer alu accesses
-drivesys.cpu.num_int_insts                    1889973                       # number of integer instructions
-drivesys.cpu.num_int_register_reads           2411030                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes          1442447                       # number of times the integer registers were written
-drivesys.cpu.num_load_insts                    394697                       # Number of load instructions
-drivesys.cpu.num_mem_refs                      625939                       # number of memory refs
-drivesys.cpu.num_store_insts                   231242                       # Number of store instructions
+drivesys.cpu.num_refs                          625939                       # Number of memory references
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -172,10 +156,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                              147484777                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 480356                       # Number of bytes of host memory used
-host_seconds                                     1.85                       # Real time elapsed on the host
-host_tick_rate                           107890886853                       # Simulator tick rate (ticks/s)
+host_inst_rate                              245765975                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 512700                       # Number of bytes of host memory used
+host_seconds                                     1.11                       # Real time elapsed on the host
+host_tick_rate                           179775828937                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -283,24 +267,8 @@ testsys.cpu.kern.syscall::118                       2      2.41%    100.00% # nu
 testsys.cpu.kern.syscall::total                    83                       # number of syscalls executed
 testsys.cpu.not_idle_fraction                0.000018                       # Percentage of non-idle cycles
 testsys.cpu.numCycles                    199569460393                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.num_busy_cycles              3558262.534294                       # Number of busy cycles
-testsys.cpu.num_conditional_control_insts       361828                       # number of instructions that are conditional controls
-testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
-testsys.cpu.num_fp_insts                        17380                       # number of float instructions
-testsys.cpu.num_fp_register_reads               11166                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes              10823                       # number of times the floating registers were written
-testsys.cpu.num_func_calls                     107994                       # number of times a function call or return occured
-testsys.cpu.num_idle_cycles              199565902130.465698                       # Number of idle cycles
 testsys.cpu.num_insts                         3560411                       # Number of instructions executed
-testsys.cpu.num_int_alu_accesses              3348322                       # Number of integer alu accesses
-testsys.cpu.num_int_insts                     3348322                       # number of integer instructions
-testsys.cpu.num_int_register_reads            4592571                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes           2442795                       # number of times the integer registers were written
-testsys.cpu.num_load_insts                     666253                       # Number of load instructions
-testsys.cpu.num_mem_refs                      1173234                       # number of memory refs
-testsys.cpu.num_store_insts                    506981                       # Number of store instructions
+testsys.cpu.num_refs                          1173234                       # Number of memory references
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
@@ -418,24 +386,8 @@ drivesys.cpu.kern.mode_ticks::idle                  0                       # nu
 drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
 drivesys.cpu.not_idle_fraction                      0                       # Percentage of non-idle cycles
 drivesys.cpu.numCycles                              0                       # number of cpu cycles simulated
-drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
-drivesys.cpu.num_busy_cycles                        0                       # Number of busy cycles
-drivesys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
-drivesys.cpu.num_fp_insts                           0                       # number of float instructions
-drivesys.cpu.num_fp_register_reads                  0                       # number of times the floating registers were read
-drivesys.cpu.num_fp_register_writes                 0                       # number of times the floating registers were written
-drivesys.cpu.num_func_calls                         0                       # number of times a function call or return occured
-drivesys.cpu.num_idle_cycles                        0                       # Number of idle cycles
 drivesys.cpu.num_insts                              0                       # Number of instructions executed
-drivesys.cpu.num_int_alu_accesses                   0                       # Number of integer alu accesses
-drivesys.cpu.num_int_insts                          0                       # number of integer instructions
-drivesys.cpu.num_int_register_reads                 0                       # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes                0                       # number of times the integer registers were written
-drivesys.cpu.num_load_insts                         0                       # Number of load instructions
-drivesys.cpu.num_mem_refs                           0                       # number of memory refs
-drivesys.cpu.num_store_insts                        0                       # Number of store instructions
+drivesys.cpu.num_refs                               0                       # Number of memory references
 drivesys.disk0.dma_read_bytes                       0                       # Number of bytes transfered via DMA reads (not PRD).
 drivesys.disk0.dma_read_full_pages                  0                       # Number of full page size DMA reads (not PRD).
 drivesys.disk0.dma_read_txs                         0                       # Number of DMA read transactions (not PRD).
@@ -479,10 +431,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                           146424656133                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 480356                       # Number of bytes of host memory used
+host_inst_rate                           151538155765                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 512700                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              399379065                       # Simulator tick rate (ticks/s)
+host_tick_rate                              415641460                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273374833                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
@@ -539,24 +491,8 @@ testsys.cpu.kern.mode_ticks::idle                   0                       # nu
 testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
 testsys.cpu.not_idle_fraction                       0                       # Percentage of non-idle cycles
 testsys.cpu.numCycles                               0                       # number of cpu cycles simulated
-testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
-testsys.cpu.num_busy_cycles                         0                       # Number of busy cycles
-testsys.cpu.num_conditional_control_insts            0                       # number of instructions that are conditional controls
-testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
-testsys.cpu.num_fp_insts                            0                       # number of float instructions
-testsys.cpu.num_fp_register_reads                   0                       # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes                  0                       # number of times the floating registers were written
-testsys.cpu.num_func_calls                          0                       # number of times a function call or return occured
-testsys.cpu.num_idle_cycles                         0                       # Number of idle cycles
 testsys.cpu.num_insts                               0                       # Number of instructions executed
-testsys.cpu.num_int_alu_accesses                    0                       # Number of integer alu accesses
-testsys.cpu.num_int_insts                           0                       # number of integer instructions
-testsys.cpu.num_int_register_reads                  0                       # number of times the integer registers were read
-testsys.cpu.num_int_register_writes                 0                       # number of times the integer registers were written
-testsys.cpu.num_load_insts                          0                       # Number of load instructions
-testsys.cpu.num_mem_refs                            0                       # number of memory refs
-testsys.cpu.num_store_insts                         0                       # Number of store instructions
+testsys.cpu.num_refs                                0                       # Number of memory references
 testsys.disk0.dma_read_bytes                        0                       # Number of bytes transfered via DMA reads (not PRD).
 testsys.disk0.dma_read_full_pages                   0                       # Number of full page size DMA reads (not PRD).
 testsys.disk0.dma_read_txs                          0                       # Number of DMA read transactions (not PRD).
-- 
2.30.2