From 1b6acf2339201a7464d052f1909b24a64021685b Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Thu, 11 Oct 2018 19:10:12 +0000 Subject: [PATCH] [AArch64] Fix PR87511 As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p should be evaluated as a HOST_WIDE_INT rather than int. Passes bootstrap & regress. gcc/ PR target/87511 * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p): Use HOST_WIDE_INT_1U for shift. testsuite/ PR target/87511 * gcc.target/aarch64/pr87511.c: Add new test. From-SVN: r265058 --- gcc/ChangeLog | 6 ++++++ gcc/config/aarch64/aarch64.c | 3 ++- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/aarch64/pr87511.c | 16 ++++++++++++++++ 4 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr87511.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8172fcd9276..b908601ce03 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-10-11 Wilco Dijkstra + + PR target/87511 + * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p): + Use HOST_WIDE_INT_1U for shift. + 2018-10-11 Doug Rupp Olivier Hainque diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d385b246a74..4c779082665 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8842,7 +8842,8 @@ aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode mode, rtx mask, return CONST_INT_P (mask) && CONST_INT_P (shft_amnt) && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode) && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0 - && (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0; + && (INTVAL (mask) + & ((HOST_WIDE_INT_1U << INTVAL (shft_amnt)) - 1)) == 0; } /* Calculate the cost of calculating X, storing it in *COST. Result diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a1ba7da09b8..f026cb26064 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-10-11 Wilco Dijkstra + + PR target/87511 + * gcc.target/aarch64/pr87511.c: Add new test. + 2018-10-11 David Malcolm PR c++/84993 diff --git a/gcc/testsuite/gcc.target/aarch64/pr87511.c b/gcc/testsuite/gcc.target/aarch64/pr87511.c new file mode 100644 index 00000000000..98064701594 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr87511.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ + +int a, d; +struct { + signed f5 : 26; + signed f6 : 12; +} b; +signed char c; +void fn1() { + signed char *e = &c; + d = a * 10; + *e = d; + b.f6 = c; + b.f5 = 8 <= 3; +} -- 2.30.2