From 1b6f4dde350e06d59468db270111252b4256904c Mon Sep 17 00:00:00 2001
From: Michael Meissner <gnu@the-meissners.org>
Date: Tue, 13 May 1997 22:04:32 +0000
Subject: [PATCH] Make sure r0 == 0; Return EINVAL for system calls that are
 defined but not provided; Provide traps 74-79 as debugging traps

---
 sim/tic80/ChangeLog |  9 +++++++++
 sim/tic80/insns     | 26 ++++++++++++++++++++++++++
 sim/tic80/interp.c  |  2 ++
 3 files changed, 37 insertions(+)

diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index c955fdcc7ca..8ef6feceb80 100644
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,12 @@
+Tue May 13 18:00:10 1997  Mike Meissner  <meissner@cygnus.com>
+
+	* insns (do_trap): For system calls that are defined, but not
+	provided return EINVAL. Temporarily add traps 74-79 to just print
+	the register state.
+
+	* interp.c (engine_{run_until_stop,step}): Before executing
+	instructions, make sure r0 == 0.
+
 Tue May 13 16:39:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* alu.h (IMEM): Take full cia not just IP as argument.
diff --git a/sim/tic80/insns b/sim/tic80/insns
index ea0a5f31794..270b5c4b071 100644
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -1005,6 +1005,7 @@ void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
 
 // trap
 void::function::do_trap:unsigned32 trap_number
+	int i;
 	TRACE_SINK1 (MY_INDEX, trap_number);
 	switch (trap_number)
 	  {
@@ -1041,6 +1042,12 @@ void::function::do_trap:unsigned32 trap_number
 	          break;
 	        }
 	      default:
+		/* For system calls which are defined, just return EINVAL instead of trapping */
+		if (GPR(15) <= 204)
+		  {
+		    GPR(2) = -22;		/* -EINVAL */
+		    break;
+		  }
 	        engine_error (SD, CPU, cia,
 	                      "0x%lx: unknown syscall %d",
 	                      (unsigned long) cia.ip, GPR(15));
@@ -1048,6 +1055,25 @@ void::function::do_trap:unsigned32 trap_number
 	    break;
 	  case 73:
 	    engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
+
+	  /* Add a few traps for now to print the register state */
+	  case 74:
+	  case 75:
+	  case 76:
+	  case 77:
+	  case 78:
+	  case 79:
+	    if (!TRACE_ALU_P (CPU))
+	      trace_one_insn (SD, CPU, cia.ip, 1, itable[MY_INDEX].file,
+			      itable[MY_INDEX].line_nr, "trap",
+			      "Trap %d", trap_number);
+
+	    for (i = 0; i < 32; i++)
+	      sim_io_eprintf (SD, "%s0x%.8lx%s", ((i % 8) == 0) ? "\t" : " ", (long)GPR(i),
+			      (((i+1) % 8) == 0) ? "\n" : "");
+	    sim_io_write_stderr (SD, "\n", 1);
+	    break;
+
 	  default:
 	    engine_error (SD, CPU, cia,
 	                  "0x%lx: unsupported trap %d",
diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c
index 24cfad13af4..e0133023c66 100644
--- a/sim/tic80/interp.c
+++ b/sim/tic80/interp.c
@@ -114,6 +114,7 @@ engine_run_until_stop (SIM_DESC sd,
       do
 	{
 	  instruction_word insn = IMEM (cia);
+	  cpu->reg[0] = 0;		/* force r0 to always contain 0 */
 	  cia = idecode_issue (sd, insn, cia);
 	}
       while (*keep_running);
@@ -135,6 +136,7 @@ engine_step (SIM_DESC sd)
       sd->restart_ok = 1;
       cia = cpu->cia;
       insn = IMEM (cia);
+      cpu->reg[0] = 0;		/* force r0 to always contain 0 */
       cia = idecode_issue (sd, insn, cia);
       engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
     }
-- 
2.30.2