From 1b78bc88e26f4fbf87faf3321fc5da582c857d34 Mon Sep 17 00:00:00 2001
From: Cole Poirier <colepoirier@gmail.com>
Date: Wed, 12 Aug 2020 11:55:20 -0700
Subject: [PATCH] mmu.py add skeleton sim and test functions from
 regfile/regfile.py

---
 src/soc/experiment/mmu.py | 48 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index f0b15bc3..9b36c17a 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -1152,3 +1152,51 @@ class MMU1(Elaboratable):
 
 #   end process;
 # end;
+
+
+def mmu_sim():
+    yield wp.waddr.eq(1)
+    yield wp.data_i.eq(2)
+    yield wp.wen.eq(1)
+    yield
+    yield wp.wen.eq(0)
+    yield rp.ren.eq(1)
+    yield rp.raddr.eq(1)
+    yield Settle()
+    data = yield rp.data_o
+    print(data)
+    assert data == 2
+    yield
+
+    yield wp.waddr.eq(5)
+    yield rp.raddr.eq(5)
+    yield rp.ren.eq(1)
+    yield wp.wen.eq(1)
+    yield wp.data_i.eq(6)
+    yield Settle()
+    data = yield rp.data_o
+    print(data)
+    assert data == 6
+    yield
+    yield wp.wen.eq(0)
+    yield rp.ren.eq(0)
+    yield Settle()
+    data = yield rp.data_o
+    print(data)
+    assert data == 0
+    yield
+    data = yield rp.data_o
+    print(data)
+
+def test_mmu():
+    dut = MMU()
+    rp = dut.read_port()
+    wp = dut.write_port()
+    vl = rtlil.convert(dut, ports=dut.ports())
+    with open("test_mmu.il", "w") as f:
+        f.write(vl)
+
+    run_simulation(dut, mmu_sim(), vcd_name='test_mmu.vcd')
+
+if __name__ == '__main__':
+    test_mmu()
-- 
2.30.2