From 1b8039a268e870d6aeab29afd6c3e3a470df2e60 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 12 May 2023 17:59:40 -0700 Subject: [PATCH] fix bugs in fcvt* pseudocode --- openpower/isa/fpcvt.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn index 0ce5e0a6..27bd09a5 100644 --- a/openpower/isa/fpcvt.mdwn +++ b/openpower/isa/fpcvt.mdwn @@ -117,11 +117,11 @@ Pseudo-code: case(0): # Signed 32-bit range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(1): # Unsigned 32-bit range_min <- bfp_CONVERT_FROM_UI32(0) range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(2): # Signed 64-bit range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) @@ -191,6 +191,7 @@ Pseudo-code: if xx_flag = 1 then SetFX(FPSCR.XX) vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag + overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined(0b00000) @@ -226,11 +227,11 @@ Pseudo-code: case(0): # Signed 32-bit range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(1): # Unsigned 32-bit range_min <- bfp_CONVERT_FROM_UI32(0) range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(2): # Signed 64-bit range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) @@ -300,6 +301,7 @@ Pseudo-code: if xx_flag = 1 then SetFX(FPSCR.XX) vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag + overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined(0b00000) -- 2.30.2