From 1b96d29174d7c56a14031bc117a7da5fa5192c81 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 17:02:20 -0700
Subject: [PATCH] No need to punch ports at all

---
 backends/aiger/xaiger.cc | 24 ++++++++++++++++++++++++
 passes/techmap/abc9.cc   | 13 -------------
 2 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 65792421f..4bdd54772 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -481,6 +481,7 @@ struct XAigerWriter
 					}
 				}
 
+				// Connect $currQ as an input to the flop box
 				if (box_module->get_bool_attribute("\\abc9_flop")) {
 					IdString port_name = "\\$currQ";
 					Wire *w = box_module->wire(port_name);
@@ -786,6 +787,29 @@ struct XAigerWriter
 					}
 				}
 
+				// For flops only, create an extra input for $currQ
+				if (box_module->get_bool_attribute("\\abc9_flop")) {
+					log_assert(holes_cell);
+
+					Wire *w = box_module->wire("\\$currQ");
+					Wire *holes_wire;
+					RTLIL::SigSpec port_wire;
+					for (int i = 0; i < GetSize(w); i++) {
+						box_inputs++;
+						holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+						if (!holes_wire) {
+							holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+							holes_wire->port_input = true;
+							holes_wire->port_id = port_id++;
+							holes_module->ports.push_back(holes_wire->name);
+						}
+						port_wire.append(holes_wire);
+					}
+					w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()), GetSize(w));
+					w->set_bool_attribute("\\hierconn");
+					holes_module->connect(w, port_wire);
+				}
+
 				write_h_buffer(box_inputs);
 				write_h_buffer(box_outputs);
 				write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index ce057566c..777ec6ac8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass {
 					Pass::call_on_module(design, derived_module, "proc");
 				SigMap derived_sigmap(derived_module);
 
-				Wire *currQ = derived_module->wire("\\$currQ");
-				if (currQ == NULL)
-					log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type));
-				log_assert(!currQ->port_output);
-				if (!currQ->port_input) {
-					currQ->port_input = true;
-					derived_module->ports.push_back(currQ->name);
-					currQ->port_id = GetSize(derived_module->ports);
-#ifndef NDEBUG
-					derived_module->check();
-#endif
-				}
-
 				SigSpec pattern;
 				SigSpec with;
 				for (auto &conn : cell->connections()) {
-- 
2.30.2