From 1bb2580779816f92439fc624c6ebf1b0f486397d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Jun 2015 19:35:00 +0200 Subject: [PATCH] sdram: use new Migen Converter in Minicon frontend and small cleanup --- misoclib/mem/sdram/core/minicon/__init__.py | 10 ++++++---- misoclib/soc/sdram.py | 11 ++--------- 2 files changed, 8 insertions(+), 13 deletions(-) diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py index 71be33fc..6789fd06 100644 --- a/misoclib/mem/sdram/core/minicon/__init__.py +++ b/misoclib/mem/sdram/core/minicon/__init__.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bus import wishbone from migen.genlib.fsm import FSM, NextState -from migen.genlib.misc import optree, Counter, WaitTimer +from migen.genlib.misc import optree, WaitTimer from misoclib.mem.sdram.phy import dfi as dfibus @@ -61,12 +61,14 @@ class MiniconSettings: def __init__(self): pass + class Minicon(Module): def __init__(self, phy_settings, geom_settings, timing_settings): if phy_settings.memtype in ["SDR"]: burst_length = phy_settings.nphases*1 # command multiplication*SDR elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: burst_length = phy_settings.nphases*2 # command multiplication*DDR + burst_width = phy_settings.dfi_databits*phy_settings.nphases address_align = log2_int(burst_length) # # # @@ -76,7 +78,7 @@ class Minicon(Module): phy_settings.dfi_databits, phy_settings.nphases) - self.bus = bus = wishbone.Interface() + self.bus = bus = wishbone.Interface(burst_width) rdphase = phy_settings.rdphase wrphase = phy_settings.wrphase @@ -203,11 +205,11 @@ class Minicon(Module): dfi.phases[rdphase].we_n.eq(1), NextState("POST-REFRESH") ) + fsm.delayed_enter("WRITE-LATENCY", "WRITE-ACK", phy_settings.write_latency-1) fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1) - fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1) fsm.delayed_enter("TRCD", "IDLE", timing_settings.tRCD-1) + fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1) fsm.delayed_enter("POST-REFRESH", "IDLE", timing_settings.tRFC-1) - fsm.delayed_enter("WRITE-LATENCY", "WRITE-ACK", phy_settings.write_latency-1) # DFI commands for phase in dfi.phases: diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index a6a8175c..fae706c7 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -70,15 +70,8 @@ class SDRAMSoC(SoC): # MINICON frontend elif isinstance(self.sdram_controller_settings, MiniconSettings): - burst_width = phy.settings.dfi_databits*phy.settings.nphases - if burst_width == 32: - self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size) - elif burst_width < 32: - self.submodules.downconverter = downconverter = wishbone.DownConverter(32, burst_width) - self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus) - self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size) - else: - raise NotImplementedError("Unsupported burst width of {} > 32".format(burst_width)) + self.submodules.converter = wishbone.Converter(wishbone.Interface(), self.sdram.controller.bus) + self.register_mem("main_ram", self.mem_map["main_ram"], self.converter.master, main_ram_size) def do_finalize(self): if not self.integrated_main_ram_size: -- 2.30.2