From 1bd8aec7746f3abc3a161010735aedb970a7652a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Oct 2018 16:01:04 +0100 Subject: [PATCH] clarify CSRs --- simple_v_extension/specification.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 064a901dc..0c8c243f0 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -69,7 +69,7 @@ tables which are used at the register decode phase. * A register CSR key-value table (typically 8 32-bit CSRs of 2 16-bits each) * A predication CSR key-value table (again, 8 32-bit CSRs of 2 16-bits each) * Small U-Mode and S-Mode register and predication CSR key-value tables - (2 16-bit entries each). + (2 32-bit CSRs of 2x 16-bit entries each). * An optional "reshaping" CSR key-value table which remaps from a 1D linear shape to 2D or 3D, including full transposition. -- 2.30.2