From 1bdde313926b698d9959294f1563264ead532b46 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 26 Sep 2019 10:34:51 -0700 Subject: [PATCH] nir: add address calc related opt rules Signed-off-by: Rob Clark Reviewed-by: Kristian H. Kristensen Reviewed-by: Eduardo Lima Mitev --- src/compiler/nir/nir_opt_algebraic.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 7bac217c3e1..fa9ae87b7d7 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/compiler/nir/nir_opt_algebraic.py @@ -1117,6 +1117,22 @@ optimizations.extend([ # for now, unconditionally convert amul to imul, this will # change in the following patch (('amul', a, b), ('imul', a, b)), + + (('imad24_ir3', a, b, 0), ('imul24', a, b)), + (('imad24_ir3', a, 0, c), (c)), + (('imad24_ir3', a, 1, c), ('iadd', a, c)), + + # if first two srcs are const, crack apart the imad so constant folding + # can clean up the imul: + # TODO ffma should probably get a similar rule: + (('imad24_ir3', '#a', '#b', c), ('iadd', ('imul', a, b), c)), + + # These will turn 24b address/offset calc back into 32b shifts, but + # it should be safe to get back some of the bits of precision that we + # already decided were no necessary: + (('imul24', a, '#b@32(is_pos_power_of_two)'), ('ishl', a, ('find_lsb', b)), '!options->lower_bitops'), + (('imul24', a, '#b@32(is_neg_power_of_two)'), ('ineg', ('ishl', a, ('find_lsb', ('iabs', b)))), '!options->lower_bitops'), + (('imul24', a, 0), (0)), ]) # bit_size dependent lowerings -- 2.30.2