From 1bdf255a6b52e5927c40732a6776acc78efb0a57 Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Thu, 25 Sep 2014 08:18:14 +0000 Subject: [PATCH] AVX-512. Add convert ps2pd and ps2dq. gcc/ * config/i386/sse.md (define_insn "fix_trunc2"): New. (define_insn "fix_truncv2sfv2di2"): Ditto. (define_insn "ufix_trunc2"): Ditto. (define_insn "sse2_cvtss2sd"): Change "nonimmediate_operand" to "". (define_insn "avx_cvtpd2ps256"): Add masking. (define_expand "sse2_cvtpd2ps_mask): New. (define_insn "*sse2_cvtpd2ps"): Add masking. (define_insn "sse2_cvtps2pd"): Add masking. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215586 --- gcc/ChangeLog | 22 ++++++++++++ gcc/config/i386/sse.md | 78 +++++++++++++++++++++++++++++++++--------- 2 files changed, 83 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e7a932f274b..68090de6f5c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2014-09-25 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_insn + "fix_trunc2"): + New. + (define_insn "fix_truncv2sfv2di2"): Ditto. + (define_insn "ufix_trunc2"): Ditto. + (define_insn "sse2_cvtss2sd"): Change + "nonimmediate_operand" to "". + (define_insn "avx_cvtpd2ps256"): Add masking. + (define_expand "sse2_cvtpd2ps_mask): New. + (define_insn "*sse2_cvtpd2ps"): Add masking. + (define_insn "sse2_cvtps2pd"): Add masking. + 2014-09-25 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b2e1d4fa6db..ac7b51b2517 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4659,6 +4659,38 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "fix_trunc2" + [(set (match_operand: 0 "register_operand" "=v") + (any_fix: + (match_operand:VF1_128_256VL 1 "" "")))] + "TARGET_AVX512DQ && " + "vcvttps2qq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "fix_truncv2sfv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") + (any_fix:V2DI + (vec_select:V2SF + (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_AVX512DQ && TARGET_AVX512VL" + "vcvttps2qq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "TI")]) + +(define_insn "ufix_trunc2" + [(set (match_operand: 0 "register_operand" "=v") + (unsigned_fix: + (match_operand:VF1_128_256VL 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512VL" + "vcvttps2udq\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "avx_cvttpd2dq256_2" [(set (match_operand:V8SI 0 "register_operand") (vec_concat:V8SI @@ -4713,7 +4745,7 @@ (vec_merge:V2DF (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 2 "nonimmediate_operand" "x,m,") + (match_operand:V4SF 2 "" "x,m,") (parallel [(const_int 0) (const_int 1)]))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] @@ -4741,14 +4773,14 @@ (set_attr "prefix" "evex") (set_attr "mode" "V8SF")]) -(define_insn "avx_cvtpd2ps256" - [(set (match_operand:V4SF 0 "register_operand" "=x") +(define_insn "avx_cvtpd2ps256" + [(set (match_operand:V4SF 0 "register_operand" "=v") (float_truncate:V4SF - (match_operand:V4DF 1 "nonimmediate_operand" "xm")))] - "TARGET_AVX" - "vcvtpd2ps{y}\t{%1, %0|%0, %1}" + (match_operand:V4DF 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX && " + "vcvtpd2ps{y}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "btver2_decode" "vector") (set_attr "mode" "V4SF")]) @@ -4761,16 +4793,28 @@ "TARGET_SSE2" "operands[2] = CONST0_RTX (V2SFmode);") -(define_insn "*sse2_cvtpd2ps" - [(set (match_operand:V4SF 0 "register_operand" "=x") +(define_expand "sse2_cvtpd2ps_mask" + [(set (match_operand:V4SF 0 "register_operand") + (vec_merge:V4SF + (vec_concat:V4SF + (float_truncate:V2SF + (match_operand:V2DF 1 "nonimmediate_operand")) + (match_dup 4)) + (match_operand:V4SF 2 "register_operand") + (match_operand:QI 3 "register_operand")))] + "TARGET_SSE2" + "operands[4] = CONST0_RTX (V2SFmode);") + +(define_insn "*sse2_cvtpd2ps" + [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand" "xm")) + (match_operand:V2DF 1 "nonimmediate_operand" "vm")) (match_operand:V2SF 2 "const0_operand")))] - "TARGET_SSE2" + "TARGET_SSE2 && " { if (TARGET_AVX) - return "vcvtpd2ps{x}\t{%1, %0|%0, %1}"; + return "vcvtpd2ps{x}\t{%1, %0|%0, %1}"; else return "cvtpd2ps\t{%1, %0|%0, %1}"; } @@ -4824,14 +4868,14 @@ (set_attr "prefix" "evex") (set_attr "mode" "V8DF")]) -(define_insn "sse2_cvtps2pd" - [(set (match_operand:V2DF 0 "register_operand" "=x") +(define_insn "sse2_cvtps2pd" + [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "xm") + (match_operand:V4SF 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1)]))))] - "TARGET_SSE2" - "%vcvtps2pd\t{%1, %0|%0, %q1}" + "TARGET_SSE2 && " + "%vcvtps2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "amdfam10_decode" "direct") (set_attr "athlon_decode" "double") -- 2.30.2