From 1c08a6770c2bcd42657f537594116797d0d2daa7 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 13 May 2015 20:01:27 +0200 Subject: [PATCH] i386.md (*mul3_1): Merge with *mulhi3_1 using SWIM248 mode iterator. * config/i386/i386.md (*mul3_1): Merge with *mulhi3_1 using SWIM248 mode iterator. (*mulv4): Use x86_64_sext_operand for operand[2] constraint. (*mulvhi4): mark operand[1] as commutative. Use nonimmediate_operand for operand[2] constraint. (*mulv4_1): Merge with *mulvhi4_1 using SWI248 mode iterator. From-SVN: r223173 --- gcc/ChangeLog | 9 +++ gcc/config/i386/i386.md | 159 +++++++++++++++------------------------- 2 files changed, 67 insertions(+), 101 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dc25116f57e..d34287c7781 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2015-05-13 Uros Bizjak + + * config/i386/i386.md (*mul3_1): Merge with *mulhi3_1 + using SWIM248 mode iterator. + (*mulv4): Use x86_64_sext_operand for operand[2] constraint. + (*mulvhi4): mark operand[1] as commutative. Use nonimmediate_operand + for operand[2] constraint. + (*mulv4_1): Merge with *mulvhi4_1 using SWI248 mode iterator. + 2015-05-13 Jakub Jelinek PR middle-end/66133 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 835e890fac1..7bec509f48c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6477,12 +6477,22 @@ ;; IMUL reg32/64, mem32/64 Direct ;; ;; On BDVER1, all above IMULs use DirectPath +;; +;; On AMDFAM10 +;; IMUL reg16, reg16, imm8 VectorPath +;; IMUL reg16, mem16, imm8 VectorPath +;; IMUL reg16, reg16, imm16 VectorPath +;; IMUL reg16, mem16, imm16 VectorPath +;; IMUL reg16, reg16 Direct +;; IMUL reg16, mem16 Direct +;; +;; On BDVER1, all HI MULs use DoublePath (define_insn "*mul3_1" - [(set (match_operand:SWI48 0 "register_operand" "=r,r,r") - (mult:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0") - (match_operand:SWI48 2 "" "K,,mr"))) + [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r") + (mult:SWIM248 + (match_operand:SWIM248 1 "nonimmediate_operand" "%rm,rm,0") + (match_operand:SWIM248 2 "" "K,,mr"))) (clobber (reg:CC FLAGS_REG))] "!(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ @@ -6497,15 +6507,21 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand")) + (ior (match_test "mode == HImode") + (match_operand 1 "memory_operand"))) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand")) + (ior (match_test "mode == HImode") + (match_operand 1 "memory_operand"))) (const_string "vector")] (const_string "direct"))) - (set_attr "bdver1_decode" "direct") + (set (attr "bdver1_decode") + (if_then_else + (match_test "mode == HImode") + (const_string "double") + (const_string "direct"))) (set_attr "mode" "")]) (define_insn "*mulsi3_1_zext" @@ -6539,42 +6555,6 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "SI")]) -;; On AMDFAM10 -;; IMUL reg16, reg16, imm8 VectorPath -;; IMUL reg16, mem16, imm8 VectorPath -;; IMUL reg16, reg16, imm16 VectorPath -;; IMUL reg16, mem16, imm16 VectorPath -;; IMUL reg16, reg16 Direct -;; IMUL reg16, mem16 Direct -;; -;; On BDVER1, all HI MULs use DoublePath - -(define_insn "*mulhi3_1" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0") - (match_operand:HI 2 "general_operand" "K,n,mr"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_HIMODE_MATH - && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "@ - imul{w}\t{%2, %1, %0|%0, %1, %2} - imul{w}\t{%2, %1, %0|%0, %1, %2} - imul{w}\t{%2, %0|%0, %2}" - [(set_attr "type" "imul") - (set_attr "prefix_0f" "0,0,1") - (set (attr "athlon_decode") - (cond [(eq_attr "cpu" "athlon") - (const_string "vector") - (eq_attr "alternative" "1,2") - (const_string "vector")] - (const_string "direct"))) - (set (attr "amdfam10_decode") - (cond [(eq_attr "alternative" "0,1") - (const_string "vector")] - (const_string "direct"))) - (set_attr "bdver1_decode" "double") - (set_attr "mode" "HI")]) - ;;On AMDFAM10 and BDVER1 ;; MUL reg8 Direct ;; MUL mem8 Direct @@ -6628,8 +6608,7 @@ (sign_extend: (match_operand:SWI48 1 "nonimmediate_operand" "%rm,0")) (sign_extend: - (match_operand:SWI48 2 "" - "We,mr"))) + (match_operand:SWI48 2 "x86_64_sext_operand" "We,mr"))) (sign_extend: (mult:SWI48 (match_dup 1) (match_dup 2))))) (set (match_operand:SWI48 0 "register_operand" "=r,r") @@ -6657,49 +6636,13 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "")]) -(define_insn "*mulv4_1" - [(set (reg:CCO FLAGS_REG) - (eq:CCO (mult: - (sign_extend: - (match_operand:SWI48 1 "nonimmediate_operand" "rm,rm")) - (match_operand: 3 "const_int_operand" "K,i")) - (sign_extend: - (mult:SWI48 (match_dup 1) - (match_operand:SWI48 2 - "x86_64_immediate_operand" "K,"))))) - (set (match_operand:SWI48 0 "register_operand" "=r,r") - (mult:SWI48 (match_dup 1) (match_dup 2)))] - "!(MEM_P (operands[1]) && MEM_P (operands[2])) - && CONST_INT_P (operands[2]) - && INTVAL (operands[2]) == INTVAL (operands[3])" - "imul{}\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "imul") - (set (attr "athlon_decode") - (cond [(eq_attr "cpu" "athlon") - (const_string "vector") - (eq_attr "alternative" "1") - (const_string "vector")] - (const_string "direct"))) - (set (attr "amdfam10_decode") - (cond [(match_operand 1 "memory_operand") - (const_string "vector")] - (const_string "direct"))) - (set_attr "bdver1_decode" "direct") - (set_attr "mode" "") - (set (attr "length_immediate") - (cond [(eq_attr "alternative" "0") - (const_string "1") - (match_test " == 8") - (const_string "4")] - (const_string "")))]) - (define_insn "*mulvhi4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:SI (sign_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "0")) + (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI - (match_operand:HI 2 "general_operand" "mr"))) + (match_operand:HI 2 "nonimmediate_operand" "mr"))) (sign_extend:SI (mult:HI (match_dup 1) (match_dup 2))))) (set (match_operand:HI 0 "register_operand" "=r") @@ -6713,37 +6656,51 @@ (set_attr "bdver1_decode" "double") (set_attr "mode" "HI")]) -(define_insn "*mulvhi4_1" +(define_insn "*mulv4_1" [(set (reg:CCO FLAGS_REG) - (eq:CCO (mult:SI - (sign_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "rm,rm")) - (match_operand:SI 3 "const_int_operand" "K,i")) - (sign_extend:SI - (mult:HI (match_dup 1) - (match_operand:HI 2 - "x86_64_immediate_operand" "K,n"))))) - (set (match_operand:HI 0 "register_operand" "=r,r") - (mult:HI (match_dup 1) (match_dup 2)))] + (eq:CCO (mult: + (sign_extend: + (match_operand:SWI248 1 "nonimmediate_operand" "rm,rm")) + (match_operand: 3 "const_int_operand" "K,i")) + (sign_extend: + (mult:SWI248 (match_dup 1) + (match_operand:SWI248 2 + "" "K,"))))) + (set (match_operand:SWI248 0 "register_operand" "=r,r") + (mult:SWI248 (match_dup 1) (match_dup 2)))] "!(MEM_P (operands[1]) && MEM_P (operands[2])) && CONST_INT_P (operands[2]) && INTVAL (operands[2]) == INTVAL (operands[3])" - "imul{w}\t{%2, %1, %0|%0, %1, %2}" + "imul{}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "imul") - (set_attr "prefix_0f" "0") + (set (attr "prefix_0f") + (if_then_else + (match_test "mode == HImode") + (const_string "0") + (const_string "*"))) (set (attr "athlon_decode") (cond [(eq_attr "cpu" "athlon") (const_string "vector") (eq_attr "alternative" "1") (const_string "vector")] (const_string "direct"))) - (set_attr "amdfam10_decode" "vector") - (set_attr "bdver1_decode" "double") - (set_attr "mode" "HI") + (set (attr "amdfam10_decode") + (cond [(ior (match_test "mode == HImode") + (match_operand 1 "memory_operand")) + (const_string "vector")] + (const_string "direct"))) + (set (attr "bdver1_decode") + (if_then_else + (match_test "mode == HImode") + (const_string "double") + (const_string "direct"))) + (set_attr "mode" "") (set (attr "length_immediate") (cond [(eq_attr "alternative" "0") - (const_string "1")] - (const_string "2")))]) + (const_string "1") + (match_test " == 8") + (const_string "4")] + (const_string "")))]) (define_expand "umulv4" [(parallel [(set (reg:CCO FLAGS_REG) -- 2.30.2