From 1c0ee4f786a77d8557c9dd462abc54982b7b639d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 27 Nov 2019 08:18:41 -0800 Subject: [PATCH] Do not replace constants with same wire --- passes/hierarchy/submod.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index cf27d2358..b21b0de01 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -34,7 +34,6 @@ struct SubmodWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap; - std::map replace_const; bool copy_mode; bool hidden_mode; @@ -231,7 +230,9 @@ struct SubmodWorker if (new_wire->port_id > 0) { // Prevents "ERROR: Mismatch in directionality ..." when flattening if (new_wire->port_output) - old_sig.replace(replace_const); + for (auto &b : old_sig) + if (!b.wire) + b = module->addWire(NEW_ID); new_cell->setPort(new_wire->name, old_sig); } } @@ -265,11 +266,6 @@ struct SubmodWorker if (wire->port_output) sigmap.add(wire); } - auto wire = module->addWire(NEW_ID); - replace_const.emplace(State::S0, wire); - replace_const.emplace(State::S1, wire); - replace_const.emplace(State::Sx, wire); - replace_const.emplace(State::Sz, wire); if (opt_name.empty()) { -- 2.30.2