From 1c14aa04fd6cac303ad6642ee97498064968e5f7 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Sat, 29 Aug 2020 15:32:38 -0700 Subject: [PATCH] mem_types.py arrange in alphabetical order for ease of reference, align formatting --- src/soc/experiment/mem_types.py | 119 +++++++++++++++----------------- 1 file changed, 57 insertions(+), 62 deletions(-) diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py index 47aa0f85..95d1bf1f 100644 --- a/src/soc/experiment/mem_types.py +++ b/src/soc/experiment/mem_types.py @@ -7,86 +7,81 @@ from nmutil.iocontrol import RecordObject from nmigen import Signal -class LoadStore1ToMmuType(RecordObject): +class DcacheToLoadStore1Type(RecordObject): def __init__(self): super().__init__() - self.valid = Signal() - self.tlbie = Signal() - self.slbia = Signal() - self.mtspr = Signal() - self.iside = Signal() - self.load = Signal() - self.priv = Signal() - self.sprn = Signal(10) - self.addr = Signal(64) - self.rs = Signal(64) + self.valid = Signal() + self.data = Signal() + self.store_done = Signal() + self.error = Signal() + self.cache_paradox = Signal() -class MmuToLoadStore1Type(RecordObject): +class DcacheToMmuType(RecordObject): def __init__(self): super().__init__() - self.done = Signal() - self.err = Signal() - self.invalid = Signal() - self.badtree = Signal() - self.segerr = Signal() - self.perm_error = Signal() - self.rc_error = Signal() - self.sprval = Signal(64) + self.stall = Signal() + self.done = Signal() + self.err = Signal() + self.data = Signal(64) - -class MmuToDcacheType(RecordObject): +class LoadStore1ToDcacheType(RecordObject): def __init__(self): super().__init__() - self.valid = Signal() - self.tlbie = Signal() - self.doall = Signal() - self.tlbld = Signal() - self.addr = Signal(64) - self.pte = Signal(64) - + self.valid = Signal() + self.load = Signal() # this is a load + self.dcbz = Signal() + self.nc = Signal() + self.nc = Signal() + self.reserve = Signal() + self.virt_mode = Signal() + self.priv_mode = Signal() + self.addr = Signal() + self.data = Signal() + self.byte_sel = Signal() -class DcacheToMmuType(RecordObject): +class LoadStore1ToMmuType(RecordObject): def __init__(self): super().__init__() - self.stall = Signal() - self.done = Signal() - self.err = Signal() - self.data = Signal(64) - - + self.valid = Signal() + self.tlbie = Signal() + self.slbia = Signal() + self.mtspr = Signal() + self.iside = Signal() + self.load = Signal() + self.priv = Signal() + self.sprn = Signal(10) + self.addr = Signal(64) + self.rs = Signal(64) -class MmuToIcacheType(RecordObject): +class MmuToLoadStore1Type(RecordObject): def __init__(self): super().__init__() - self.tlbld = Signal() - self.tlbie = Signal() - self.doall = Signal() - self.addr = Signal(64) - self.pte = Signal(64) - + self.done = Signal() + self.err = Signal() + self.invalid = Signal() + self.badtree = Signal() + self.segerr = Signal() + self.perm_error = Signal() + self.rc_error = Signal() + self.sprval = Signal(64) -class LoadStore1ToDcacheType(RecordObject): +class MmuToDcacheType(RecordObject): def __init__(self): super().__init__() - self.valid = Signal() - self.load = Signal() # this is a load - self.dcbz = Signal() - self.nc = Signal() - self.nc = Signal() - self.reserve = Signal() - self.virt_mode = Signal() - self.priv_mode = Signal() - self.addr = Signal() - self.data = Signal() - self.byte_sel = Signal() - + self.valid = Signal() + self.tlbie = Signal() + self.doall = Signal() + self.tlbld = Signal() + self.addr = Signal(64) + self.pte = Signal(64) -class DcacheToLoadStore1Type(RecordObject): +class MmuToIcacheType(RecordObject): def __init__(self): super().__init__() - self.valid = Signal() - self.data = Signal() - self.store_done = Signal() - self.error = Signal() - self.cache_paradox = Signal() + self.tlbld = Signal() + self.tlbie = Signal() + self.doall = Signal() + self.addr = Signal(64) + self.pte = Signal(64) + -- 2.30.2