From 1c300aa269485debd09869ee15e4dcf8a93eee24 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 5 Sep 2022 21:00:15 +0300 Subject: [PATCH] power_insn: disassemble extra index --- src/openpower/decoder/power_insn.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index f160a67e..e9a51625 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -603,11 +603,14 @@ class DynamicOperandTargetAddrBD(DynamicOperand): @_dataclasses.dataclass(eq=True, frozen=True) class DynamicOperandGPR(DynamicOperandReg): def disassemble(self, value, record, verbose=False): + svp64 = isinstance(value, SVP64Instruction) span = record.fields[self.name] value = value[span] if verbose: yield f"{int(value):0{value.bits}b}" yield repr(span) + if svp64: + yield repr(self.extra_idx(record)) else: yield f"r{str(int(value))}" @@ -615,11 +618,14 @@ class DynamicOperandGPR(DynamicOperandReg): @_dataclasses.dataclass(eq=True, frozen=True) class DynamicOperandFPR(DynamicOperandReg): def disassemble(self, value, record, verbose=False): + svp64 = isinstance(value, SVP64Instruction) span = record.fields[self.name] value = value[span] if verbose: yield f"{int(value):0{value.bits}b}" yield repr(span) + if svp64: + yield repr(self.extra_idx(record)) else: yield f"f{str(int(value))}" -- 2.30.2