From 1c34b4a015c02076b92a594fd70278a67410b3a0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Jun 2019 12:57:10 +0200 Subject: [PATCH] cpu/vexriscv: update submodule --- litex/soc/cores/cpu/vexriscv/verilog | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog index 4b5a515d..cfbd3e08 160000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -1 +1 @@ -Subproject commit 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470 +Subproject commit cfbd3e0871e1f85336c6a7adbc75f3702b365e1d -- 2.30.2