From 1c39d100a02dce4c60a92d29a8c47fe7a6a99b11 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 29 Mar 2021 18:57:06 +0100 Subject: [PATCH] must not add bus width parameter --- ls180soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ls180soc.py b/ls180soc.py index 8d2789f..44a4ce8 100755 --- a/ls180soc.py +++ b/ls180soc.py @@ -362,7 +362,7 @@ class LibreSoCSim(SoCCore): cpu_type = "microwatt", cpu_cls = LibreSoC if cpu == "libresoc" \ else Microwatt, - bus_data_width = 64, + #bus_data_width = 64, # don't add this! stops conversion csr_address_width = 14, # limit to 0x8000 cpu_variant = variant, csr_data_width = 8, -- 2.30.2