From 1c450dc2e7626eb7643e5a370b4d5fe3b10f34ed Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Fri, 11 Aug 2023 03:09:58 +0000 Subject: [PATCH] RISC-V: Add reference to Zve32* Before actual vlen handling, this commit fixes its description to allow vlen less than 16 (but 4 or greater), to support vector subset extensions for embedded environment ('Zve32*'). --- gdb/arch/riscv.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index 54610ed6c16..d5ea1a55b21 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -47,9 +47,10 @@ struct riscv_gdbarch_features int flen = 0; /* The size of the v-registers in bytes. The value 0 indicates a target - with no vector registers. The minimum value for a standard compliant - target should be 16, but GDB doesn't currently mind, and will accept - any vector size. */ + with no vector registers. The minimum value for a 'V'-extension compliant + target should be 16 and 4 for an embedded subset compliant target (with + 'Zve32*' extension), but GDB doesn't currently mind, and will accept any + vector size. */ int vlen = 0; /* When true this target is RV32E. */ -- 2.30.2