From 1c45541c7f26926df8e0d55ec9684e7da866d994 Mon Sep 17 00:00:00 2001 From: Andreas Baierl Date: Thu, 4 Jul 2019 17:35:09 +0200 Subject: [PATCH] lima/ppir: Add fddx and fddy Lower fddx and fddy and set the right bits in codegen. Signed-off-by: Andreas Baierl Reviewed-by: Vasily Khoruzhick Reviewed-by: Erico Nunes --- src/gallium/drivers/lima/ir/pp/codegen.c | 24 ++++++++++++++++++++++++ src/gallium/drivers/lima/ir/pp/lower.c | 20 ++++++++++++++++++++ src/gallium/drivers/lima/ir/pp/nir.c | 2 ++ src/gallium/drivers/lima/ir/pp/node.c | 14 ++++++++++++++ 4 files changed, 60 insertions(+) diff --git a/src/gallium/drivers/lima/ir/pp/codegen.c b/src/gallium/drivers/lima/ir/pp/codegen.c index 615438cfcce..ebf034fac33 100644 --- a/src/gallium/drivers/lima/ir/pp/codegen.c +++ b/src/gallium/drivers/lima/ir/pp/codegen.c @@ -350,6 +350,12 @@ static void ppir_codegen_encode_vec_add(ppir_node *node, void *code) case ppir_op_min: f->op = ppir_codegen_vec4_acc_op_min; break; + case ppir_op_ddx: + f->op = ppir_codegen_vec4_acc_op_dFdx; + break; + case ppir_op_ddy: + f->op = ppir_codegen_vec4_acc_op_dFdy; + break; default: break; } @@ -426,6 +432,12 @@ static void ppir_codegen_encode_scl_add(ppir_node *node, void *code) case ppir_op_select: f->op = ppir_codegen_float_acc_op_sel; break; + case ppir_op_ddx: + f->op = ppir_codegen_float_acc_op_dFdx; + break; + case ppir_op_ddy: + f->op = ppir_codegen_float_acc_op_dFdy; + break; default: break; } @@ -658,6 +670,18 @@ static int encode_instr(ppir_instr *instr, void *code, void *last_code) if (instr->slots[PPIR_INSTR_SLOT_TEXLD]) ctrl->sync = true; + if (instr->slots[PPIR_INSTR_SLOT_ALU_VEC_ADD]) { + ppir_node *node = instr->slots[PPIR_INSTR_SLOT_ALU_VEC_ADD]; + if (node->op == ppir_op_ddx || node->op == ppir_op_ddy) + ctrl->sync = true; + } + + if (instr->slots[PPIR_INSTR_SLOT_ALU_SCL_ADD]) { + ppir_node *node = instr->slots[PPIR_INSTR_SLOT_ALU_SCL_ADD]; + if (node->op == ppir_op_ddx || node->op == ppir_op_ddy) + ctrl->sync = true; + } + for (int i = 0; i < 2; i++) { if (instr->constant[i].num) { uint16_t output[4] = {0}; diff --git a/src/gallium/drivers/lima/ir/pp/lower.c b/src/gallium/drivers/lima/ir/pp/lower.c index d52644b98b1..44c06bdd2f8 100644 --- a/src/gallium/drivers/lima/ir/pp/lower.c +++ b/src/gallium/drivers/lima/ir/pp/lower.c @@ -114,6 +114,24 @@ static bool ppir_lower_load(ppir_block *block, ppir_node *node) return true; } +static bool ppir_lower_ddxy(ppir_block *block, ppir_node *node) +{ + assert(node->type == ppir_node_type_alu); + ppir_alu_node *alu = ppir_node_to_alu(node); + + alu->src[1] = alu->src[0]; + if (node->op == ppir_op_ddx) + alu->src[1].negate = !alu->src[1].negate; + else if (node->op == ppir_op_ddy) + alu->src[0].negate = !alu->src[0].negate; + else + assert(0); + + alu->num_src = 2; + + return true; +} + static bool ppir_lower_texture(ppir_block *block, ppir_node *node) { ppir_load_texture_node *load_tex = ppir_node_to_load_texture(node); @@ -299,6 +317,8 @@ static bool (*ppir_lower_funcs[ppir_op_num])(ppir_block *, ppir_node *) = { [ppir_op_abs] = ppir_lower_abs, [ppir_op_neg] = ppir_lower_neg, [ppir_op_const] = ppir_lower_const, + [ppir_op_ddx] = ppir_lower_ddxy, + [ppir_op_ddy] = ppir_lower_ddxy, [ppir_op_lt] = ppir_lower_swap_args, [ppir_op_le] = ppir_lower_swap_args, [ppir_op_load_texture] = ppir_lower_texture, diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c index 7c8352cb82c..f3fd578c813 100644 --- a/src/gallium/drivers/lima/ir/pp/nir.c +++ b/src/gallium/drivers/lima/ir/pp/nir.c @@ -150,6 +150,8 @@ static int nir_to_ppir_opcodes[nir_num_opcodes] = { [nir_op_inot] = ppir_op_not, [nir_op_ftrunc] = ppir_op_trunc, [nir_op_fsat] = ppir_op_sat, + [nir_op_fddx] = ppir_op_ddx, + [nir_op_fddy] = ppir_op_ddy, }; static ppir_node *ppir_emit_alu(ppir_block *block, nir_instr *ni) diff --git a/src/gallium/drivers/lima/ir/pp/node.c b/src/gallium/drivers/lima/ir/pp/node.c index 602d4625138..ff70bb0d2db 100644 --- a/src/gallium/drivers/lima/ir/pp/node.c +++ b/src/gallium/drivers/lima/ir/pp/node.c @@ -145,6 +145,20 @@ const ppir_op_info ppir_op_infos[] = { PPIR_INSTR_SLOT_END }, }, + [ppir_op_ddx] = { + .name = "ddx", + .slots = (int []) { + PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD, + PPIR_INSTR_SLOT_END + }, + }, + [ppir_op_ddy] = { + .name = "ddy", + .slots = (int []) { + PPIR_INSTR_SLOT_ALU_SCL_ADD, PPIR_INSTR_SLOT_ALU_VEC_ADD, + PPIR_INSTR_SLOT_END + }, + }, [ppir_op_and] = { .name = "and", .slots = (int []) { -- 2.30.2