From 1c50e34b30e08e46b311c9b1fb4ed0ccc7fd7422 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Apr 2019 05:12:46 +0100 Subject: [PATCH] add comments to FIFOControl --- src/add/singlepipe.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 62eb7d89..95ca82a4 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -1025,7 +1025,19 @@ class FIFOControl(ControlBase): """ * iospecfn: specification for incoming and outgoing data * depth : number of entries in the FIFO - NOTE: FPGAs may have trouble with the defaults for SyncFIFO + NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO + + NOTE 2: i_data *must* have a shape function. it can therefore + be a Signal, or a Record, or a RecordObject. + + data is processed (and located) as follows: + + self.p self.stage temp fn temp fn temp fp self.n + i_data->process()->result->flatten->din.FIFO.dout->flatten(o_data) + + yes, really: flatten produces a Cat() which can be assigned to. + this is how the FIFO gets de-flattened without needing a de-flatten + function """ self.fdepth = depth @@ -1034,6 +1046,7 @@ class FIFOControl(ControlBase): def elaborate(self, platform): self.m = m = ControlBase._elaborate(self, platform) + # make a FIFO with a signal of equal width to the o_data. (fwidth, _) = self.n.o_data.shape() fifo = SyncFIFO(fwidth, self.fdepth) m.submodules.fifo = fifo -- 2.30.2