From 1c8f6f21b4e88ed58de5819054dee1ff9bcf2b82 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 31 Jan 2014 12:48:31 +0100 Subject: [PATCH] Progress on presentation --- manual/PRESENTATION_ExSyn.tex | 89 ++++++++++++++++++++++++++++ manual/PRESENTATION_Intro.tex | 108 ++++++++++++++++++++++++++++++++-- manual/presentation.tex | 2 + 3 files changed, 194 insertions(+), 5 deletions(-) create mode 100644 manual/PRESENTATION_ExSyn.tex diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex new file mode 100644 index 000000000..53208eecf --- /dev/null +++ b/manual/PRESENTATION_ExSyn.tex @@ -0,0 +1,89 @@ + +\section{Yosys by example -- Synthesis} + +\begin{frame} +\sectionpage +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Typical Phases of a Synthesis Flow} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Design elaboration} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{High-Level Synthesis} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{The ``proc'' commands} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{The ``memory'' commands} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{The ``fsm'' commands} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Low-Level Synthesis} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{The ``techmap'' command} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{The ``abc'' command} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Other special-purpose mapping commands} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 6df65a24f..ee82a7515 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -540,18 +540,116 @@ endmodule \subsection{Verification} -\begin{frame}{\subsecname{} -- VlogHammer} -TBD +\begin{frame}{\subsecname} +Contiously checking the correctness of Yosys and making sure that new features +do not break old ones is a high priority in Yosys. + +\bigskip +There are two external test suites build for Yosys: VlogHammer and yosys-bigsim +(see next slides) + +\bigskip +In addition to that, yosys comes with $\approx\!200$ test cases used in ``{\tt make test}''. + +\bigskip +A debug build of Yosys also contains a lot of asserts and checks the integrity of +the internal state after each command. +\end{frame} + +\begin{frame}[fragile]{\subsecname{} -- VlogHammer} +VlogHammer is a Verilog regression test suite developed to test the different +subsystems in Yosys by comparing them to each other and the implementations +generated by some proprietary tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...). + +\bigskip +Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping, +simulation models, SAT models. + +\bigskip +Thousands of auto-generated test cases containing code such as: +\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=Verilog] +assign y9 = $signed(((+$signed((^(6'd2 ** a2))))<$unsigned($unsigned(((+a3)))))); +assign y10 = (-((+((+{2{(~^p13)}})))^~(!{{b5,b1,a0},(a1&p12),(a4+a3)}))); +assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))})); +\end{lstlisting} + +\bigskip +Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 20 bugs in +the proprietary tools used as external reference where found and reported. \end{frame} \begin{frame}{\subsecname{} -- yosys-bigsim} -TBD +yosys-bigsim is a collection of real-world open-source Verilog designs and test +benches. yosys-bigsim compares the testbench outpus of simulations of the original +Verilog code and synthesis results. + +\bigskip +The following designs are part of yosys-bigsim: +\begin{itemize} +\item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU +\item {\tt aes\_5cycle\_2stage} -- an AES encryption core +\item {\tt softusb\_navre} -- an AVR compatible 8 bit CPU +\item {\tt amber23} -- an ARMv2 compatible 32 bit CPU +\item {\tt lm32} -- another 32 bit CPU from Lattice Semiconductor +\item {\tt verilog-pong} -- a hardware pong game with VGA output +\item {\tt elliptic\_curve\_group} -- ECG point-add and point-scalar-mul core +\item {\tt reed\_solomon\_decoder} -- a Reed-Solomon Error Correction Decoder +\end{itemize} \end{frame} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \subsection{Benefits of Open Source HDL Synthesis} -\begin{frame}{\subsecname} -TBD +\begin{frame}{\subsecname{} -- 1/3} +\begin{itemize} +\item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par +Today the cost for a mask set in $\unit[180]{nm}$ technology is far less than +the cost for the design tools needed to design the mask layouts. Open Source +ASIC flows are an important enabler for ASIC-level Open Source Hardware. + +\bigskip +\item Availablity and Reproducability: \smallskip\par +If you are a researcher who is publishing, you want to use tools that everyone +else can also use. Even if most universities have access to all major +commercial tools, you usually do not have easy access to the version that was +used in a research project a couple of years ago. With Open Source tools you +can even release the source code of the tool you have used alongside your data. +\end{itemize} +\end{frame} + +\begin{frame}{\subsecname{} -- 2/3} +\begin{itemize} +\item Framework: \smallskip\par +Yosys is not only a tool. It is a framework that can be used as basis for other +developments, so researchers and hackers alike do not need to re-invent the +basic functionality. Extensibility was one of Yosys' design goals. + +\bigskip +\item All-in-one: \smallskip\par +Because of the framework characterisitcs of Yosys, an increasing number of features +become available in one tool. Yosys not only can be used for circuit synthesis but +also for formal equivialence checking, SAT solving, and for circuit analysis, to +name just a few other application domains. With propritaery software one needs to +learn a new tool for each of this applications. +\end{itemize} +\end{frame} + +\begin{frame}{\subsecname{} -- 3/3} +\begin{itemize} +\item Educational Tool: \smallskip\par +Propritaery synthesis tools are at times where secretive about their inner +workings. They often are ``black boxes'' where a design goes in and synthesis +results come out. Yosys is very open about its internals and it is easy to +observe the different steps of synthesis. +\end{itemize} + +\bigskip +\begin{block}{BTW: Yosys is licensed under the ISC license:} +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. +\end{block} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/manual/presentation.tex b/manual/presentation.tex index 1b09b7de0..bfd09a498 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -25,6 +25,7 @@ \usepackage{listings} \usepackage{setspace} \usepackage{skull} +\usepackage{units} \usepackage{tikz} \usetikzlibrary{calc} @@ -100,5 +101,6 @@ Outline of this presentation: \end{frame} \include{PRESENTATION_Intro} +\include{PRESENTATION_ExSyn} \end{document} -- 2.30.2