From 1c9a1bb4f8c0674b5b8fde741236b57b0661c0bd Mon Sep 17 00:00:00 2001 From: lkcl Date: Tue, 4 Apr 2023 23:32:10 +0100 Subject: [PATCH] RM EXTRA2/3 corrections --- openpower/sv/svp64.mdwn | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 38e193559..d704266f6 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -837,6 +837,12 @@ augmented to 7 bits in length. `RM-2P-2S` is for `stw` etc. and is Rsrc1 Rsrc2. +| Field Name | Field bits | Description | +|------------|------------|----------------------------| +| Rsrc1_EXTRA3 | `10:12` | extends Rsrc1 | +| Rsrc2_EXTRA3 | `13:15` | extends Rsrc2 | +| MASK_SRC | `16:18` | Execution Mask for Source | + ### RM-1P-2S1D single-predicate, three registers (2 read, 1 write) @@ -863,14 +869,13 @@ and STORE operations. see [[sv/ldst]] for detailed anslysis. **RM-2P-1S2D:** -For RM-2P-1S2D the EXTRA2 dest and src names are switched (Rsrc_EXTRA2 -is in bits 10:11, Rdest1_EXTRA2 in 12:13) +For RM-2P-1S2D dest2 is in bits 14:15 | Field Name | Field bits | Description | |------------|------------|----------------------------| -| Rsrc2_EXTRA2 | `10:11` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | +| Rdest_EXTRA2 | `10:11` | extends Rdest (R\*\_EXTRA2 Encoding) | | Rsrc1_EXTRA2 | `12:13` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | -| Rdest_EXTRA2 | `14:15` | extends Rdest (R\*\_EXTRA2 Encoding) | +| Rdest2_EXTRA2 | `14:15` | extends Rdest22 (R\*\_EXTRA2 Encoding) | | MASK_SRC | `16:18` | Execution Mask for Source | **RM-2P-3S:** -- 2.30.2