From 1caeda95ed30f8a01b6f87b56431ecc06003f5de Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Mon, 6 Dec 2021 22:31:21 +0000 Subject: [PATCH] Started working on jtag bs chain test --- src/spec/testing_stage1.py | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index fe51431..e121ee1 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -21,9 +21,9 @@ from nmigen.sim import Simulator, Delay, Settle, Tick, Passive from nmutil.util import wrap -#from soc.debug.jtagutils import (jtag_read_write_reg, -# jtag_srv, jtag_set_reset, -# jtag_set_ir, jtag_set_get_dr) +from soc.debug.jtagutils import (jtag_read_write_reg, + jtag_srv, jtag_set_reset, + jtag_set_ir, jtag_set_get_dr) from c4m.nmigen.jtag.tap import TAP, IOType from c4m.nmigen.jtag.bus import Interface as JTAGInterface @@ -635,6 +635,26 @@ def test_i2c(): print("I2C Test PASSED!") +def test_jtag_bs_chain(): + print () + print ("bs pad keys", top.jtag.boundary_scan_pads.keys()) + print () + uart_rx_pad = top.jtag.boundary_scan_pads['uart_0__rx']['i'] + uart_tx_pad = top.jtag.boundary_scan_pads['uart_0__tx']['o'] + + jtag_set_reset(top.jtag) + + print(top.jtag.ios.keys()) + yield Settle() + + top.jtag.ios['uart_0__rx'].core.i.eq(1) + top.jtag.ios['uart_0__rx'].pad.i.eq(0) + yield + top.jtag.ios['uart_0__rx'].core.i.eq(0) + top.jtag.ios['uart_0__rx'].pad.i.eq(1) + + print("JTAG Boundary Scan Chain Test PASSED!") + yield def test_debug_print(): @@ -754,8 +774,9 @@ if __name__ == '__main__': #sim.add_sync_process(wrap(test_case0())) #sim.add_sync_process(wrap(test_gpios())) - sim.add_sync_process(wrap(test_uart())) - sim.add_sync_process(wrap(test_i2c())) + #sim.add_sync_process(wrap(test_uart())) + #sim.add_sync_process(wrap(test_i2c())) + sim.add_sync_process(wrap(test_jtag_bs_chain())) #sim.add_sync_process(wrap(test_debug_print())) with sim.write_vcd("blinker_test.vcd"): -- 2.30.2