From 1cc281ca6fc4035a8f48fd7b7a0289cb580c3f4c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 18 Apr 2022 09:10:28 +0200 Subject: [PATCH] verific: allow memories to be inferred in loops (vhdl) --- frontends/verific/verific.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b53bad7da..284d5db31 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2553,6 +2553,7 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); + RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); -- 2.30.2