From 1cc2e0cc6b47bd5efbf2af266405060785085e6b Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 7 Apr 2018 23:40:26 -0400 Subject: [PATCH] radeonsi: fully enable 2x DCC MSAA for array and non-array textures MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The clear code is exactly the same as for 1 sample buffers - just clear the whole thing. Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeonsi/si_clear.c | 13 +++++++------ src/gallium/drivers/radeonsi/si_pipe.c | 5 +---- src/gallium/drivers/radeonsi/si_pipe.h | 1 - src/gallium/drivers/radeonsi/si_texture.c | 15 ++++++++++++--- 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index b08a9558b4d..f2df9483c12 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -211,19 +211,20 @@ void vi_dcc_clear_level(struct si_context *sctx, if (sctx->chip_class >= GFX9) { /* Mipmap level clears aren't implemented. */ assert(rtex->resource.b.b.last_level == 0); - /* MSAA needs a different clear size. */ - assert(rtex->resource.b.b.nr_samples <= 1); + /* 4x and 8x MSAA needs a sophisticated compute shader for + * the clear. See AMDVLK. */ + assert(rtex->resource.b.b.nr_samples <= 2); clear_size = rtex->surface.dcc_size; } else { unsigned num_layers = util_num_layers(&rtex->resource.b.b, level); /* If this is 0, fast clear isn't possible. (can occur with MSAA) */ assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size); - /* Layered MSAA DCC fast clears need to clear dcc_fast_clear_size - * bytes for each layer. This is not currently implemented, and - * therefore MSAA DCC isn't even enabled with multiple layers. + /* Layered 4x and 8x MSAA DCC fast clears need to clear + * dcc_fast_clear_size bytes for each layer. A compute shader + * would be more efficient than separate per-layer clear operations. */ - assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1); + assert(rtex->resource.b.b.nr_samples <= 2 || num_layers == 1); dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size * diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 327dd7c4242..3eb89ff0287 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -90,7 +90,6 @@ static const struct debug_named_value debug_options[] = { { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." }, { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" }, { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" }, - { "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" }, { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" }, /* Tests: */ @@ -984,9 +983,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } sscreen->dcc_msaa_allowed = - !(sscreen->debug_flags & DBG(NO_DCC_MSAA)) && - (sscreen->debug_flags & DBG(DCC_MSAA) || - sscreen->info.chip_class == VI); + !(sscreen->debug_flags & DBG(NO_DCC_MSAA)); sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 351c9f4cd38..f73e0d1aac3 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -154,7 +154,6 @@ enum { DBG_NO_DCC_CLEAR, DBG_NO_DCC_FB, DBG_NO_DCC_MSAA, - DBG_DCC_MSAA, DBG_NO_FMASK, /* Tests: */ diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 0a2939bdd16..9ff0ba3e9a8 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -268,9 +268,18 @@ static int si_init_surface(struct si_screen *sscreen, if (sscreen->info.chip_class >= VI && (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC || ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT || - /* DCC MSAA array textures are disallowed due to incomplete clear impl. */ - (ptex->nr_samples >= 2 && - (!sscreen->dcc_msaa_allowed || ptex->array_size > 1)))) + (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed))) + flags |= RADEON_SURF_DISABLE_DCC; + + /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */ + if (sscreen->info.chip_class == VI && + ptex->nr_samples >= 4 && + ptex->array_size > 1) + flags |= RADEON_SURF_DISABLE_DCC; + + /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */ + if (sscreen->info.chip_class >= GFX9 && + ptex->nr_samples >= 4) flags |= RADEON_SURF_DISABLE_DCC; if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) { -- 2.30.2